Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on January 30th, 2026. Claims 1-7, 9-16, and 18-22 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-16, AND 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over Dewitt et al. (USPGPUB No. 2015/0347012 A1, hereinafter referred to as Dewitt) in view of Walsh et al. (USPGPUB No. 2013/0054901 A1, hereinafter referred to as Walsh) and further in view of Dalal et al. (USPGPUB No. 2013/0318277 A1, hereinafter referred to as Dalal’277) and further in view of Dalal et al. (USPGPUB No. 2017/0235699 A1, hereinafter referred to as Dalal) and further in view of Chua et al. (USPGPUB No. 2011/0032995 A1, hereinafter referred to as Chua).
Referring to claim 1, Dewitt discloses a method {“utilized to communicate…”, see Fig. 1, [0019].}, comprising:
receiving metadata describing a first buffer {“second buffer 118”, see Fig. 1, [0019].}; generating a descriptor based on the metadata {“SGL descriptors”, last 3 lines of [0019], see Fig. 1.};
and storing the descriptor in an element {“memory 110 hosts the data structures”, see Fig. 1, [0019].}, wherein the element is configured to store a predetermined number of descriptors {“creates SGL descriptors that provide information”, see Fig. 1, [0019].}, and wherein the element comprises an amount of memory corresponding to a burst size {“burst count field”, see Fig. 2a-2b, [0021].} of a component configured to read the metadata to control access to the first buffer {“application data is provided to the first buffer 116”, [0019].}.
Dewitt does not appear to explicitly disclose determining a burst size of a component; selecting a predetermined number of descriptors based on the determined burst size; and storing the predetermined number of descriptors in an element; the data component is component configured to read the metadata to control access to the first buffer; a number of buffers, including the first buffer, are variably allocated based on the burst size.
However, Walsh discloses determining a burst size {“each memory window… define its size” (Col 179, lines 1-3) including when PCI master decides/determines to burst as claimed (“multiple data phases such as burst cycles”, see Fig. 9, Col 78, lines 47-48.} corresponding to a data component {“PCI bus bridge 716 provides the interface between the rest of [data component] MPU 102 and the PCI bus 104”, see Fig. 9, Col 77, lines 65-67.}; by reading from a memory associated with the data component {memory “DRAM (dynamic random access memory) 106,” associated with “coupled to a 32-bit 104” and “MPU 102”, see Figs. 5-7, Col 10, lines 45-47.};
selecting a predetermined number of descriptors {descriptors “DMA requests DREQ1 OR DREQ2 from a peripheral 1310 or 1312”, see Fig. 11, Col 114, lines 31-32.} based on the determined burst size {“single or multiple DMA transfers” (Col 114, lines 43-44) and their respective burst size “sequence of DMA cycles until the word count reaches FFFFh” (Col 114, lines 62-64}, and storing the predetermined number of descriptors and the pointer in an element {element “DMA control block 910 receives [stores]” descriptors “DMA request” as claimed, see Fig. 11, Col 114, lines 31-32.}; the data component is component configured to read the metadata {“Auto initialization is enabled by a bit in the Mode Register”, see Fig. 11, Col 115, lines 24-25.} to control access to the first buffer {“DMA subsystem completes transfer” and the respective first buffer”, see Fig. 11, Col 114, lines 45-46.}; a number of buffers {“Serial interfaces 936A and 936B each have a 16-byte FIFO for queuing and buffering the serial data to be transmitted and received”, see Fig. 11, Col 17, lines 48-52.}, including the first buffer, are variably allocated based on the burst size {“Parallel interface 938 has a 16-byte datapath FIFO buffer and provides DMA transfer”, see Fig. 11, Col 17, lines 53-55.}.
Dewitt and Walsh are analogous art because they are from the same field of endeavor, managing peripheral devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Dewitt and Walsh before him or her, to modify Dewitt’s “buffer 118” incorporating Walsh’s “PPU 110” single chip solution and corresponding DMA circuitry (see Fig. 11, Col 15, lines 40-41).
The suggestion/motivation for doing so would have been to incorporate circuitry responsive to the system activity signals and supplies weighted activity output signals adjustably weighting the system activity levels including filter circuitry continually responds to the weighted activity output signals (Walsh Col 2, lines 23-27).
Therefore, it would have been obvious to combine Walsh with Dewitt to obtain the invention as specified in the instant claim(s).
Neither Dewitt or Walsh appears to explicitly disclose reserving a pointer size in an element, the pointer size corresponding to an amount of memory associated with a pointer; selecting a predetermined number of descriptors based on the determined burst size and the pointer size; the pointer points to a next element creating a dynamic queue of elements;
However, Dalal’277 discloses reserving a pointer size in an element {“capacities of the memories can be precisely [reserved] allocated to support context switching” ([0056]) such as “Allocating a specific I/O space to a device can include allocating said IO space a specific physical memory space occupied” ([0115}}, the pointer size corresponding to an amount of memory {Examiner’s interpretation: the term “corresponding” treated similar to “coupled to” as the claim does not explicitly define correlating 1:1 ratio, 1:m one to many, or m:m many to many correlation “may create a virtual I/O address space for each VF during runtime and allocate part of the physical address space to it” ([0114] 1st sentence,} associated with a pointer {“perform a mmap operation, wherein a pointer to the entry in the page cache”, see Fig. 1, [0026] last two sentences}; selecting a predetermined number of descriptors {“the device driver may write I/O descriptors into a descriptor queue”, see Fig. 6-1, 2nd sentence} based on the determined burst size and the pointer size {“bursting of traffic (buffering and bursting” with the appropriate pointer via page cache (see Fig. 6-1, [0126], 3rd sentence)}; the pointer points to a next element creating a dynamic queue of elements {“allowing hardware context switching synchronized with [dynamic] network queuing. In this way, there can be a one-to-one mapping between thread and queues” (see Fig. 4-5 [0047]); queues “created” in “RLDRAM 438” ([0047]); Examiner’s note: the term “creating” appears to be new matter as the original specification does not appear to recite “creating” or equivalent term/language/functionality};
Dewitt/Walsh and Dalal’277 are analogous because they are from the same field of endeavor, metadata buffer description techniques.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Dewitt/Walsh and Dalal’277 before him or her, to modify Dewitt/Walsh’s device incorporating Dalal’277 “system 601” (see Fig. 6-1) and corresponding “RLDRAM 438” and queue allocation.
The suggestion/motivation for doing so would have been to implement an architecture that supports both structured and unstructured queries can better handle current and emerging Big Data applications (Dalal’277 [0004] last sentence) while also provide simple and effective access to both structured and unstructured data are seen as necessary for maximizing the value of enterprise informational resources (Dalal’277 [0003], last sentence).
Therefore, it would have been obvious to combine Dalal’277 with Smith/Walsh to obtain the invention as specified in the instant claim(s).
Neither one in the group consisting of Dewitt, Walsh, and Dalal appears to explicitly disclose wherein the metadata including a pointer and a buffer size associated with the first buffer; wherein the element comprises an amount of memory corresponding to a burst size of the data component and the point size; wherein a number of buffers, including the first buffer, are variably allocated based on the burst size and on the data component;
However, Dalal discloses the metadata including a pointer and a buffer size {“can affect the traffic shape of flows and micro-flows through delay (buffering), bursting of traffic (buffering and bursting [size]), smoothing of traffic (buffering and rate-limiting flows)”, see Fig. 6-1 [0125]} associated with the first buffer {“prefetch data stored in a buffer memory 610b”, see Fig. 6-1 [0123]};
wherein the element comprises an amount of memory {“processor 608i can allocate execution resources such as processor cycles and [an amount of] memory to a particular queue it is currently handling”, see Fig. 6-1 [0127]} corresponding to a burst size of the data component and the pointer size {bursty size “Packets from a certain source”, see Fig. 6-1, [0124]}; wherein a number of buffers {“[number of buffers] output queues are managed [variably allocated] using a scheduling discipline”, see Fig. 6-1 [0126]}, including the first buffer, are variably allocated {“flowing to a certain [data component] socket … as part of a session flow and are classified using session metadata.”, see Fig. 6-1 [0124]} based on the burst size and on the data component {“incoming packets can be reordered based on their session metadata [burst size].”, see Fig. 6-1 [0125], 1st sentence}.
Dewitt/Walsh/Dalal’277 and Dalal are analogous because they are from the same field of endeavor, metadata buffer description techniques.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Dewitt/Walsh/Dalal’277 and Dalal before him or her, to modify Dewitt/Walsh’s/Dalal’277 device incorporating Dalal’s “buffer memory 610b” and corresponding scheduling circuitry (see Fig. 6-1).
The suggestion/motivation for doing so would have been to implement an architecture that supports both structured and unstructured queries can better handle current and emerging Big Data applications thereby facilitating robustness and reliability by allowing different to share resources when handling structured and unstructured data (Dalal [0004] paraphrased).
Therefore, it would have been obvious to combine Dalal with Smith/Walsh/Dalal’277 to obtain the invention as specified in the instant claim(s).
Neither one in the group consisting of Dewitt, Walsh, Dalal, and Dalal’699 appears to explicitly disclose wherein the pointer points to a next memory element that comprises a similar structure to the first memory element, creating a dynamic queue of variably-sized memory elements;
However, Chua discloses wherein the pointer points {“decoding parameters 161” (see Fig. 1, [0043]) or equivalently “decoding parameters 301” (see Fig. 3 [0081], [0082]} to a next memory element {“derives block buffer addresses according to decoding parameters”, see Fig. 3 [0072]} that comprises a similar structure to the first memory element {“interpolated data by [similar structure] applying pre-defined interpolation filters to buffered pixel data”, see Fig. 3 [0074], last sentence}, creating a dynamic queue {“Direct memory access means 160 generates block [creates a dynamic queue] memory addresses”, see Fig. 1 [0043]; see Fig. 3, similarly [0071]} of variably-sized memory elements {“specified by maximum DMA constraints and system resource limitation specified by block buffer size constraints” (see Fig. 3 [0073]) also referred as “Variable-size block buffer 340 has input terminals to receive reference pixel data and block buffer addresses” ([0075], 1st sentence)}.
Dewitt/Walsh/Dalal’277/Dalal and Chua are analogous because they are from the same field of endeavor, metadata buffer description techniques.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Dewitt/Walsh/Dalal and Dalal before him or her, to modify Dewitt/Walsh’s/Dalal’277/Dalal’s system incorporating Chua’s “motion compensation device 101B” (see Fig. 3, [0070]).
The suggestion/motivation for doing so would have been to implement a buffering mechanism for use with motion compensation that does not create a performance bottleneck without adding undue complexity to a video decoder (Chua [0006]) as part of an efficient system architectures that surpass conventional performance capabilities and yet is able to keep cost at a low level have been sought (Chua [0002], last sentence).
Therefore, it would have been obvious to combine Chua with Smith/Walsh/Dalal’277/Dalal to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Dewitt discloses further comprising, in response to the predetermined number of descriptors being stored in the first memory element {“creates SGL descriptors that provide information”, see Fig. 1, [0019].}:
storing, in the first memory element, the pointer to a next memory element {“write command from inbound queue 112”, see Fig. 1, [0022].}}, wherein the next memory element comprises an amount of memory {“NVM device 106 retrieves all blocks of application data”, see Fig. 1, [0023].} corresponding to the burst size of the component {“first buffer interleave burst length 204”, see Fig. 2a-2b, [0026].}.
As per claim 3, the rejection of claim 2 is incorporated and Dewitt discloses wherein a memory capacity to store the predetermined number of descriptors combined with a memory capacity to store the pointer is substantially equal {“identifies the size of each block of application data”, [0027].} to the burst size {“first buffer interleave burst length 204”, see Fig. 2a-2b, [0026].}.
As per claim 4, the rejection of claim 1 is incorporated and Dewitt discloses wherein the descriptor comprises a memory location of the first buffer {“first buffer address field 202”, see Fig. 2a-2b, [0027].}.
As per claim 5, the rejection of claim 1 is incorporated and Dewitt discloses wherein the descriptor comprises a size of the first buffer {“identifies the size of each block of application data”, [0027].}.
As per claim 6, the rejection of claim 1 is incorporated and Dewitt discloses further comprising:
receiving second metadata describing a second buffer {“command buffer 112”, see Fig. 1, [0023].};
generating a second descriptor based on the second metadata {“creates SGL descriptors that provide information”, see Fig. 1, [0019].}; and storing the second descriptor in the first memory element {“SGL buffer 124”, see Fig. 1.}.
As per claim 7, the rejection of claim 6 is incorporated and Dewitt discloses wherein a size of the first buffer is not equal to a size of the second buffer {“identifies the size of each block of application data”, [0027].}.
As per claim 9, the rejection of claim 8 is incorporated and Dewitt discloses further comprising:
determining that a burst size of the component has changed to a second burst size {“identifies the size of each block of application data”, [0027].}; and selecting a new predetermined number of descriptors based on the second burst size {“creates SGL descriptors that provide information”, see Fig. 1, [0019].}.
Referring to claims 10-16, and 18 are apparatus claim reciting claim functionality corresponding to the method claim of claims 1-7, AND 9, respectively, thereby rejected under the same rationale as claims 1-7, AND 9 recited above.
Referring to claims 19-22 are system apparatus claim reciting claim functionality corresponding to the method claim of claims 1-7, and 9, respectively, thereby rejected under the same rationale as claims 1-7, and 9 recited above, inter alia, Dewitt discloses the first memory comprises dynamic random access memory (DRAM) {“DRAM 110”, see Fig. 1, [0019].}, the second memory comprises DRAM {see claim 6, “SGL stored in DRAM”}, and third memory comprises SRAM {“Nonvolatile memory 126”, see Fig. 1, [0023].}.
Response to Arguments
Applicant’s arguments filed on 01/30/2026 have been considered but deemed moot in view of the new ground of the rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative of the current state of the art regarding claim 1’s “metadata”, “pointer size”, or “descriptors”: US 12530299 B2, US 20250086129 A1, US 20230308199 A1, US 11620246 B1, US 11526767 B2, US 20210157312 A1, US 20180203815 A1, US 10013373 B1, and US 20110032995 A1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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