DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Amendments
Acknowledgment of receiving amendments to the claims, which were received by the Office on 10/21/2025.
Response to Arguments
Applicant’s arguments with respect to claims 1-9, 12, 14-19 and 21 have been considered but are moot because the arguments do not apply to the same combination of references being used in the current rejection. Applicant’s arguments are directed solely to the claimed invention as amended 10/21/2025 which has been rejected under new ground of rejection necessitated by amendment. See rejection below for full detail.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-9, 12, 14-19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 6,903,670 B1) in view of Rysinski et al. (US 2012/0169909 A1) in view of Blanquart (US 2009/0322912 A1) in view of Higuchi et al. (US 2006/0170795 A1) in view of Ueno (US 2013/0100326 A1) in view of Wang et al. (US 2017/0054931 A1).
Regarding claim 19, Lee et al. (hereafter referred as Lee) teaches an electronic apparatus comprising: an imaging device (Lee, Fig. 3) that includes:
a signal processing circuit configured to process a signal output from the imaging device (Lee, Column 6, Lines 36-47, “An arithmetic logic unit or other processor”);
a pixel array that includes a plurality of pixels (Lee, Fig. 3, Pixel array, Column, 2, Lines 25-37, Column 3, Lines 7-15);
a voltage source configured to output a specific signal of a specific voltage (Lee, Column 7, Lines 11-25, “test input” voltage);
a first switch (Lee, Fig. 3, TEST transistors and ISOLATION transistors (35-43), Column 8, Lines 1-36, The switch is a first switch.), wherein the first switch is controlled to output one of the specific signal (Lee, Fig. 3, Test Input, Column 5, Lines 66-67, Column 6, lines 1-19, Column 7, Lines 15-25) or the pixel signal (Lee, Column, 2, Lines 25-37, Column 3, Lines 7-15); and
a column readout circuit that includes a plurality of analog-to-digital (AD) converters (Lee, Fig. 3, CDS, MUX, and ADC), wherein
the first switch to connects the column readout circuit and the voltage source (Lee, Fig. 3),
an AD converter of the plurality of AD converters is configured to
execute an AD conversion, based on output of one of the specific signal or the pixel signal (Lee, Column 3, Lines 7-15, Column 6, lines 1-19, Column 7, Lines 15-25, The AD conversion is based on the pixel signals in imaging mode and based on the specific signal in test mode.); and
output a digital signal based on the executed AD conversion (Lee, Fig. 3, ADC 19 and 21, The ADC outputs a digital value.), and
the signal processing circuit (Lee, Column 6, Lines 36-47, “An arithmetic logic unit or other processor”) further configured to:
measure an error of a gain on the digital signal output by the AD converter (Lee, Column 7, Lines 35-40);
calculate a correction value (Lee, Column 7, Lines 10-46, The correction value is the stored data that is used to correct the gain errors.) based on:
the measured error of the gain (Lee, Column 7, Lines 35-40), and
the connection of the column readout circuit and the voltage source (Lee, Column 7, Lines 10-46, The correction value is the stored data that is used to correct the gain errors. The stored data is based on the measured gain error determined when the “test input” voltage is set.);
execute, based on the calculated correction value, a correction process on the output digital signal (Lee, Colum 6, Lines 36-47, Column 7, Lines 40-46, The correction process is interpreted as correcting the pixel signals), wherein
the correction process is executed to correct an analog characteristic of the column readout circuit (Lee, Colum 6, Lines 36-47, Column 7, Lines 40-46),
the correction process is executed at startup of the imaging device based on a first output timing (Lee, Column 6, Lines 48-67, Column 7, Lines 1-10, The correction process is performed during initial power up. The correction process may be performed a plurality of times and averaged together.), and
a relationship between a light amount and a digital value that correspond to the digital signal is uniform between the plurality of AD converters based on the executed correction process (Lee, Column 6, Lines 1-47, The correction values to correct for the column to column offsets of the correlated double sampling amplifiers and A/D converters produces uniform outputs between the A/D converters. Therefore, the relationship between light amount and the digital value after A/D conversion for the light amount is uniform for the A/D converters. That is, a specific light amount received at pixels of different columns would output the same A/D conversion result. Column 7, Lines 46-60, Correcting for non-linearity in the A/D converter provides for a uniform conversion between a given light amount and the digital value after A/D conversion for the light amount.); and
and re-execute the correction process based on occurrence of an event at a second output timing (Lee, Column 6, Lines 48-67, Column 7, Lines 1-10, The correction process may be re-executed to produce new calibration data. The event is the timing for producing new calibration data.), wherein
an execution time of the re-executed correction process at the second output timing is shorter than an execution time of the correction process at the first output timing (Lee, Column 6, Lines 48-67, Column 7, Lines 1-10, A running average may be used to minimization of the time needed to build a mean offset value between frames. Therefore, obtaining additional data for the running average at the second timing is shorter than performing an average at the startup (first output timing) which would require multiple measurements.).
However, Lee does not explicitly state a wherein a pixel of the plurality of pixels includes a photoelectric conversion element, and the photoelectric conversion element is configured to: convert incident light to an amount of charge; and accumulate the converted amount of charge; a vertical scanning circuit configured to: perform an operation to discharge the accumulated amount of charge of the photoelectric conversion element and start new light exposure; and read out a pixel signal that corresponds to an amount of incident light after the performed operation; circuitry configured to control the first switch to connected the column readout circuit and the voltage source, and does not teach the plurality of AD converters includes a comparator, the comparator includes: a differential amplifier that includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; a second switch connected between a drain of the first NMOS transistor and a gate of the first NMOS transistor; a first capacitor that includes a first end and a second end; a second capacitor connected to the gate of the first NMOS transistor; and a third capacitor, the first end of the first capacitor is connected to the first switch, the second end of the first capacitor is connected to the second switch and the second capacitor, a source of the first NMOS transistor is connected to a source of the second NMOS transistor and a drain of the third NMOS transistor, a source of the third NMOS transistor is connected to a ground, the third capacitor is connected between a gate of the second NMOS transistor and the ground, a first voltage at the gate of the second NMOS transistor is associated with charge accumulated on the third capacitor; the differential amplifier is configured to: output, at a first time, an output signal at a first level based on a second voltage at the gate of the first NMOS transistor, and one of the specific signal or the pixel signal, wherein the second voltage is less than the first voltage; and output, at a second time, the output signal at a second level based on the second voltage, and one of the specific signal or the pixel signal, wherein the second voltage is greater than the first voltage, and the second level is higher than the first level; the AD converter is configured to: execute an AD conversion based on one of the output signal at the first level or the output signal at the second level; the correction process is executed at a vertical synchronization signal, the circuitry is further configured to detect occurrence of an event subsequent to the correction process; and control the signal processing circuit and the vertical scanning circuit based on the detection of the occurrence of the event; re-execute the correction process based on the detection of the occurrence of the event; wherein the correction process is re-executed at a second output timing of the vertical synchronization signal; the event for the re-execution of the correction process is based on an instruction to execute a new correction process.
In reference to Rysinski et al. (hereafter referred as Rysinski), Rysinski teaches a vertical scanning circuit (Rysinski, Fig. 1, row control module 120, Paragraph 0025);
circuitry configured to control an imaging device (Rysinski, Fig. 1 row control module 120 and digital control module 140, Paragraph 0025);
the circuitry is further configured to control the vertical scanning circuit based on the detection of the occurrence of an event (Rysinski, Paragraph 0025, Specified control of the pixel array is the event.)
These arts are analogous since they are both related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the invention of Lee with the explicit teaching of circuitry to control the imaging device (pixels/readout circuits).
"A person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense" KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 USPQ2d 1385 (2007).
It would have been obvious to a person of ordinary skill, when pursuing the known options within his or her technical grasp (See KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 USPQ2d 1385 (2007)), to have modified the invention of Lee with the explicit teaching of circuitry to control the imaging device (pixels/readout circuits) to provide appropriate signals and timings to the imaging device and would provide similar and expected results for controlling the imaging device. Further, the circuitry would control the first switch since the first switch is part of the imaging device.
However, the combination of Lee and Rysinski does not explicitly state a wherein a pixel of the plurality of pixels includes a photoelectric conversion element, and the photoelectric conversion element is configured to: convert incident light to an amount of charge; and accumulate the converted amount of charge; the vertical scanning circuit configured to: perform an operation to discharge the accumulated amount of charge of the photoelectric conversion element and start new light exposure; and read out a pixel signal that corresponds to an amount of incident light after the performed operation; and does not teach the plurality of AD converters includes a comparator, the comparator includes: a differential amplifier that includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; a second switch connected between a drain of the first NMOS transistor and a gate of the first NMOS transistor; a first capacitor that includes a first end and a second end; a second capacitor connected to the gate of the first NMOS transistor; and a third capacitor, the first end of the first capacitor is connected to the first switch, the second end of the first capacitor is connected to the second switch and the second capacitor, a source of the first NMOS transistor is connected to a source of the second NMOS transistor and a drain of the third NMOS transistor, a source of the third NMOS transistor is connected to a ground, the third capacitor is connected between a gate of the second NMOS transistor and the ground, a first voltage at the gate of the second NMOS transistor is associated with charge accumulated on the third capacitor; the differential amplifier is configured to: output, at a first time, an output signal at a first level based on a second voltage at the gate of the first NMOS transistor, and one of the specific signal or the pixel signal, wherein the second voltage is less than the first voltage; and output, at a second time, the output signal at a second level based on the second voltage, and one of the specific signal or the pixel signal, wherein the second voltage is greater than the first voltage, and the second level is higher than the first level; the AD converter is configured to: execute an AD conversion based on one of the output signal at the first level or the output signal at the second level; the correction process is executed at a vertical synchronization signal, the circuitry is further configured to detect occurrence of an event subsequent to the correction process; re-execute the correction process based on the detection of the occurrence of the event; wherein the correction process is re-executed at a second output timing of the vertical synchronization signal; the event for the re-execution of the correction process is based on an instruction to execute a new correction process.
In reference to Blanquart, Blanquart teaches a correction process is executed at a vertical synchronization signal (Blanquart, Fig. 5, Paragraphs 0053-0055) at a first output timing (Blanquart, Paragraphs 0041 and 0043),
the circuitry is further configured: to detect occurrence of an event subsequent to the correction process (Blanquart, Paragraph 0043, After calibration, an event of a change in temperature can trigger calibration again.);
re-execute the correction process based on the detection of the occurrence of the event (Blanquart, Paragraphs 0043), wherein
the correction process is re-executed at a second output timing of the vertical synchronization signal (Blanquart, Fig. 5, Paragraphs 0053-0055),
the event for the re-execution of the correction process is based on an instruction to execute a new correction process (Blanquart, Paragraph 0043, Any of a periodically effectuate calibration, a user provided input, and monitored condition is considered to be an instruction to execute a new correction process.).
These arts are analogous since they are all related to correcting column fixed-pattern noise. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Lee and Rysinski with the teaching of using the vertical sync signals to perform the correction process as seen in Blanquart to synchronize the frame readout (Blanquart, Fig. 6, 0056) and allow the amount of time for light integration can be increased for low light conditions (Blanquart, Paragraph 0054) and to perform re-execution of the correction process in response a detected event to update the calibration data in response to changes in temperature, or when decided by the user.
However, the combination of Lee, Rysinski and Blanquart does not explicitly state a wherein a pixel of the plurality of pixels includes a photoelectric conversion element, and the photoelectric conversion element is configured to: convert incident light to an amount of charge; and accumulate the converted amount of charge; the vertical scanning circuit configured to: perform an operation to discharge the accumulated amount of charge of the photoelectric conversion element and start new light exposure; and read out a pixel signal that corresponds to an amount of incident light after the performed operation; and does not teach the plurality of AD converters includes a comparator, the comparator includes: a differential amplifier that includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; a second switch connected between a drain of the first NMOS transistor and a gate of the first NMOS transistor; a first capacitor that includes a first end and a second end; a second capacitor connected to the gate of the first NMOS transistor; and a third capacitor, the first end of the first capacitor is connected to the first switch, the second end of the first capacitor is connected to the second switch and the second capacitor, a source of the first NMOS transistor is connected to a source of the second NMOS transistor and a drain of the third NMOS transistor, a source of the third NMOS transistor is connected to a ground, the third capacitor is connected between a gate of the second NMOS transistor and the ground, a first voltage at the gate of the second NMOS transistor is associated with charge accumulated on the third capacitor; the differential amplifier is configured to: output, at a first time, an output signal at a first level based on a second voltage at the gate of the first NMOS transistor, and one of the specific signal or the pixel signal, wherein the second voltage is less than the first voltage; and output, at a second time, the output signal at a second level based on the second voltage, and one of the specific signal or the pixel signal, wherein the second voltage is greater than the first voltage, and the second level is higher than the first level; the AD converter is configured to: execute an AD conversion based on one of the output signal at the first level or the output signal at the second level.
In reference to Higuchi et al. (hereafter referred as Higuchi), Higuchi teaches a an AD converters includes a comparator (Higuchi, Fig. 1, differential amplifier AMP, Paragraph 0031),
the comparator includes:
a differential amplifier (Higuchi, Fig. 1, differential amplifier AMP, Paragraph 0031);
a first capacitor that includes a first end and a second end (Higuchi, Fig. 1, Capacitor C2, Paragraph 0031),
the differential amplifier includes a positive terminal and a negative terminal (Higuchi, Fig. 1),
a second capacitor (Higuchi, Fig. 1, Capacitor C1) connected to the positive terminal of a differential amplifier (Higuchi, Fig. 1, AMP); and
a third capacitor (Higuchi, Fig. 1, Capacitor C2)
the third capacitor is connected between the negative terminal and the ground (Higuchi, Fig. 1, Capacitor C2),
a first voltage at the gate of the negative terminal is associated with charge accumulated on the third capacitor (Higuchi, Fig. 1, Capacitor C2, Paragraph 0034);
the differential amplifier is configured to:
output, at a first time, an output signal at a first level based on a second voltage at the positive terminal, and the pixel signal, wherein the second voltage is less than the first voltage at the negative terminal (Higuchi, Fig. 2, When voltage at N1 (positive terminal) is less than the voltage at N2 (negative terminal), the output at N3 (output) is at a low level.); and
output, at a second time, the output signal at a second level based on the second voltage, and the pixel signal at the positive terminal, wherein the second voltage is greater than the voltage at the negative terminal, the second level is higher than the first level (Higuchi, Fig. 2, When voltage at N1 (positive terminal) is greater than the voltage at N2 (negative terminal), the output at N3 (output) is at a high level),
the AD converter is configured to: execute an AD conversion based on one of the output signals at the first level or the output signal at the second level(Higuchi, Fig. 2, “A/D conversion operation”, Paragraph 0036).
These arts are analogous since they are both related to ADC circuits in image sensors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination Lee, Rysinski and Blanquart with the ADC circuit as seen in Higuchi to reduce a scale of a data read circuit of a solid-state imaging device and hence to reduce the production costs thereof without lowering a data read speed of the data read circuit. It is another object of the present invention to reduce current consumption of the data read circuit of the solid-state imaging device (Higuchi, Paragraph 0008).
However, the combination of Lee, Rysinski, Blanquart and Higuchi does not explicitly state a wherein a pixel of the plurality of pixels includes a photoelectric conversion element, and the photoelectric conversion element is configured to: convert incident light to an amount of charge; and accumulate the converted amount of charge; the vertical scanning circuit configured to: perform an operation to discharge the accumulated amount of charge of the photoelectric conversion element and start new light exposure; and read out a pixel signal that corresponds to an amount of incident light after the performed operation; and does not teach the differential amplifier that includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; a second switch connected between a first drain of the first NMOS transistor and a first gate of the first NMOS transistor; the second capacitor connected to the gate of the first NMOS transistor; the first end of the first capacitor is connected to the first switch, the second end of the first capacitor is connected to the second switch and the second capacitor, a source of the first NMOS transistor is connected to a source of the second NMOS transistor and a drain of the third NMOS transistor, a source of the third NMOS transistor is connected to a ground, the third capacitor is connected to a gate of the second NMOS transistor, a first voltage at the gate of the second NMOS transistor is associated with charge accumulated on the third capacitor; the differential amplifier is configured to: output, at a first time, an output signal at a first level based on a second voltage at the gate of the first NMOS transistor, and one of the specific signal or pixel signal, wherein the second voltage is less than the first voltage; and output, at a second time, the output signal at a second level based on the second voltage, and one of the specific signal or the pixel signal, wherein the second voltage is greater than the first voltage.
In reference to Ueno, Ueno teaches a differential amplifier (Ueno, Fig. 22 and 23) includes a first NMOS transistor (Ueno, Fig. 22-23, NMOS transistors NT511, Paragraph 0271, The first NMOS transistor is the positive terminal.), a second NMOS transistor (Ueno, Fig. 22-23, NMOS transistors NT512, Paragraph 0271, The second NMOS transistor is the negative terminal.), and a third NMOS transistor (Ueno, Fig. 22, NMOS transistors NT513, Paragraph 0273),
a second switch connected between a drain of the first NMOS transistor and a gate of the first NMOS transistor (Ueno, Fig. 22, transistor PT513);
a first capacitor that includes a first end and a second end (Ueno, Fig. 22, Capacitor C511);
the second end of the first capacitor is connected to the second switch (Ueno, Fig. 22, Capacitor C511 is connected to transistor PT513);
a source of the first NMOS transistor is connected to a source of the second NMOS transistor and a drain of the third NMOS transistor (Ueno, Fig. 22),
a source of the third NMOS transistor is connected to a ground (Ueno, Fig. 22, NMOS transistors NT513, Paragraph 0273).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combination of Lee, Rysinski, Blanquart and Higuchi with construction of the differential amplifier according to Ueno.
"A person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense" KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 USPQ2d 1385 (2007).
It would have been obvious to a person of ordinary skill, when pursuing the known options within his or her technical grasp (See KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 USPQ2d 1385 (2007)), to have modified the combination of Lee, Rysinski, Blanquart and Higuchi with construction of the differential amplifier according to Ueno since it is a known circuit diagram for a differential amplifier and would provide similar and expected results as a comparator and to reduces noise by greatly limiting a band using a mirror capacitance (Ueno, Paragraph 0262). The limitation “a second capacitor connected to the gate of the first NMOS transistor” is met since the gate of the first NMOS transistor is the positive terminal. The limitation “the first end of the first capacitor is connected to the first switch” is met since the signal to the differential amplifier of the ADC is from the first switch. The limitation “the second end of the first capacitor is connected to the second switch and the second capacitor“ is met since both the first and second capacitors are connected to the positive terminal. Further, since the gate of the first NMOS transistor is the positive terminal and the gate of the second NMOS transistor is the negative terminal of the differential amplifier, the limitations “the third capacitor is connected between a gate of the second NMOS transistor and the ground, a first voltage at the gate of the second NMOS transistor is associated with charge accumulated on the third capacitor; the differential amplifier is configured to: output, at a first time, an output signal at a first level based on a second voltage at the gate of the first NMOS transistor, and one of the specific signal or pixel signal, wherein the second voltage is less than the first voltage; and output, at a second time, the output signal at a second level based on the second voltage, and one of the specific signal or pixel signal, wherein the second voltage is greater than the first voltage” are met.
However, the combination of Lee, Rysinski, Blanquart, Higuchi and Ueno does not explicitly state a wherein a pixel of the plurality of pixels includes a photoelectric conversion element, and the photoelectric conversion element is configured to: convert incident light to an amount of charge; and accumulate the converted amount of charge; the vertical scanning circuit configured to: perform an operation to discharge the accumulated amount of charge of the photoelectric conversion element and start new light exposure; and read out a pixel signal that corresponds to an amount of incident light after the performed operation.
In reference to Wang et al. (hereafter referred as Wang), Wang teaches a wherein a pixel of the plurality of pixels includes a photoelectric conversion element (Wang, Fig. 2, photodiode PD, Paragraph 0023), and
the photoelectric conversion element is configured to:
convert incident light to an amount of charge (Wang, Paragraph 0025); and
accumulate the converted amount of charge (Wang, Paragraph 0025);
a vertical scanning circuit (Wang, Fig. 1, Control circuitry 120, Paragraph 0020) configured to:
perform an operation to discharge the accumulated amount of charge of the photoelectric conversion element and start new light exposure (Wang, Paragraphs 0024-0025); and
read out a pixel signal that corresponds to an amount of incident light after the performed operation (Wang, Paragraphs 0024-0025).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Lee, Rysinski, Blanquart, Higuchi and Ueno with the explicit teaching of the extremely common and basic operations of reading out a pixel as seen in Wang since it is an extremely well-known method of reading a signal from a pixel and would provide similar and expected results for reading pixel signals.
Claims 1 and 18 are rejected for the same reasons as claim 19.
Regarding claim 2, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the circuitry (Rysinski, Fig. 1 row control module 120 and digital control module 140 Paragraph 0025) is further configured to control, based on a specific condition associated with the event, the first switch to output the specific signal to the AD converter, (Lee, Column 6, Lines 59-67, Column 7, Lines 1-10, The specific condition is test mode. The combination of Lee and Rysinski controls the switches with the circuitry (row control module 120 and digital control module 140). Blanquart, Paragraph 0043).
Regarding claim 3, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 2 (see claim 2 analysis), wherein the control circuitry is further configured to control the first switch to output the specific signal to the AD converter at a specific period (Lee, Column 6, Lines 59-67, Column 7, Lines 1-10, A predetermined period may be during initial power up, between the imager array frame periods, at the time of imager array power up, for use with each frame of data after each frame, for use with a next subsequent frame or frames).
Regarding claim 6, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the circuitry is further configured to control the first switch to output the specific signal that has a specific voltage value of a plurality of voltage values (Lee, Fig. 3, Test Input, Column 5, Lines 66-67, Column 6, lines 1-19, Column 7, Lines 15-25).
Regarding claim 7, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the circuitry is further configured to control the first switch to output a plurality of signals, and a first signal of the plurality of signals has a first voltage value different from a second voltage value of a second signal of the plurality of signals (Lee, Fig. 3, Test Input, Column 5, Lines 66-67, Column 6, lines 1-19, Column 7, Lines 15-25).
Regarding claim 8, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the AD converter is further configured to convert the pixel signal to the digital signal (Higuchi, Fig. 1, Paragraph 0032), based on a result of comparison between a third voltage (Higuchi, Fig. 1, voltage at N1) and a fourth voltage (Higuchi, Fig. 1, voltage at N2),
the third voltage is associated with a first signal (Higuchi, Fig. 1, voltage at N1)
the first signal that corresponds to a sum of the pixel signal (Higuchi, Fig. 1, Signal from pixel circuit PC1) and a ramp signal (Higuchi, Fig. 1, ramp signal RMP, Paragraph 0032),
the ramp signal linearly changes in a direction opposite to the pixel signal (Higuchi, Fig. 2, Paragraph 0035, The reference signal changes linearly in a positive direction. Further, as seen in Figures 1 and 2, after transistor Q2 is turned on by signal TG, and while switch SW1 is on, the pixel signal reduces the voltage at N1 in the negative direction to the S+N level. Therefore, reference signal linearly changes in a direction opposite to the pixel signal), and
the fourth voltage serves as a reference (Higuchi, Fig. 2, Voltage at N2 is a reference).
Regarding claim 9, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 8 (see claim 8 analysis), wherein the comparator is configured to: perform the comparison between the third voltage and the fourth voltage; and output a second signal that indicates the result of the comparison (Higuchi, Fig. 2, Paragraphs 0035-0036).
Regarding claim 12, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the signal processing circuit is further configured to execute the correction process on the digital signal based on the control of the first switch to output the pixel signal to the AD converter (Lee, Colum 6, Lines 35-45, Column 7, Lines 35-46).
Regarding claim 14, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the circuitry is further configured to:
output a ramp signal (Higuchi, Fig. 1, ramp signal RMP) to the first NMOS transistor (Ueno, Fig. 22-23, NMOS transistors NT511); and
control the first switch to output one of the specific signal (Lee, Fig. 3, “test input” voltage) or the pixel signal (Lee, Fig. 3, pixel signal, Higuchi, Fig. 1, signal from pixel PC1) to the first NMOS transistor (Ueno, Fig. 22-23, NMOS transistors NT511).
Regarding claim 15, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 14 (see claim 14 analysis), wherein the second NMOS transistor is connected to a reference voltage (Higuchi, Fig. 2, Paragraph 0035-0036, Voltage at N2 is a reference voltage).
Regarding claim 16, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 15 (see claim 15 analysis), wherein the circuitry is further configured to:
output the ramp signal to the second capacitor (Higuchi, Fig. 1, RMP is output to capacitor C1 (second capacitor); and
control the first switch to output one of the pixel signal or the specific signal (Lee, Fig. 3, Test and Isolation Transistors select the pixel or specific signal as the signal to input to the ADC) to the first capacitor (Ueno, Fig. 22, Capacitor C511).
Regarding claim 17, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 16 (see claim 16 analysis), wherein the reference voltage is a ground voltage (Higuchi, Fig. 1, The reference voltage is ground since C2 is connected to ground).
Regarding claim 21, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the comparator further includes a third switch (Ueno, Fig. 22, transistor PT514) connected between a drain of the second NMOS transistor and the gate of the second NMOS transistor (Ueno, Fig. 22, transistor PT514, Paragraph 0277-0281).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 6,903,670 B1) in view of Rysinski et al. (US 2012/0169909 A1) in view of Blanquart (US 2009/0322912 A1) in view of Higuchi et al. (US 2006/0170795 A1) in view of Ueno (US 2013/0100326 A1) in view of Wang et al. (US 2017/0054931 A1) in view of Higuchi et al. (US 5,121,119).
Regarding claim 4, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 2 (see claim 2 analysis), wherein the circuitry is further configured to:
detect the event corresponding to a temperature change (Blanquart, Paragraph 0043); and
control, based on the temperature change, the first switch to output the specific signal to the AD converter (Lee, Column 7, Lines 11-25, “test input” voltage, The calibration is performed by controlling the switch to output the specific signal to the AD converter).
However, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang does not explicitly teach a specific temperature change.
In reference to Higuchi et al. (US 5,121,119 hereafter referred as Higuchi2), Higuchi teaches correcting an ADC in response to detection of a specific temperature change (Higuchi2, Column 7, Lines 27-31).
These arts are analogous since they are all related to calibrating analog to digital converters. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang with the explicit teaching of using a specific temperature change as seen in Higuchi2 to apply the known technique of using a specific temp change to yield the predictable results of knowing when to calibrate. Further, Lee teaches performing ADC calibration by controlling the switch to output the specific signal to the AD converter. Therefore, the limitation “detect a specific temperature change, and control the switch to output the specific signal to the AD converter, based on the specific temperature change” is met.
Claims 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 6,903,670 B1) in view of Rysinski et al. (US 2012/0169909 A1) in view of Blanquart (US 2009/0322912 A1) in view of Higuchi et al. (US 2006/0170795 A1) in view of Ueno (US 2013/0100326 A1) in view of Wang et al. (US 2017/0054931 A1) in view of Kim et al. (US 2015/0303903 A1).
Alternatively, regarding claim 4, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang teaches the imaging device according to claim 2 (see claim 2 analysis), wherein the circuitry is further configured to:
detect the event corresponding to a temperature change (Blanquart, Paragraphs 0043); and
control, based on the temperature change, the first switch to output the specific signal to the AD converter (Lee, Column 7, Lines 11-25, “test input” voltage, The calibration is performed by controlling the switch to output the specific signal to the AD converter).
However, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang does not teach the circuitry is further configured to: detect the event corresponding to a specific temperature change, and control, based on the specific temperature change, the first switch to output the specific signal to the AD converter.
In reference to Kim et al. (US 2015/0303903 A1, hereafter referred as Kim2), Kim2 teaches circuitry configured to detect an event corresponding to a specific temperature change (Kim2, Paragraph 0040, temperature sensing circuit 142); and performing, in response to detection of a specific temperature change, calibration for analog-to-digital converters (Kim2, Paragraph 0002 and 0043).
These arts are analogous since they are both related to calibrating analog-to-digital converters to correct for gain and offset (Kim2, Paragraph 0002-0003). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang with the teaching of performing calibration in response to a specific temperature change as seen in Kim2 to correct the AD conversion processing unit in response to changes due to temperature (Kim2, Paragraph 0006-0007). Additionally, Examiner notes it is well known that temperature changes also affect the readout of AD conversion processing units in image sensors (see conclusion).
Regarding claim 5, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang the imaging device according to claim 2 (see claim 2 analysis), wherein the circuitry is further configured to control the first switch to output the specific signal to the AD converter to perform calibration (Lee, Column 6, Lines 59-67, Column 7, Lines 1-10).
However, the combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang does not teach wherein the circuitry is further configured to: detect the event corresponding to a specific voltage change, and control, based on the specific voltage change, the first switch to output the specific signal to the AD converter.
In reference to Kim2, Kim2 teaches circuitry configured to detect an event corresponding to a specific voltage change (Kim2, Paragraph 0040, voltage sensing circuit 140); and performing calibration for analog-to-digital converters in response to detection of a specific voltage change (Kim2, Paragraph 0002 and 0043).
These arts are analogous since they are both related to calibrating analog-to-digital converters to correct for gain and offset (Kim2, Paragraph 0002-0003). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify combination of Lee, Rysinski, Blanquart, Higuchi, Ueno and Wang with the teaching of performing calibration in response to a predetermined voltage change as seen in Kim2 to correct the AD conversion processing unit in response to changes due to voltage (Kim2, Paragraph 0006-0007). Additionally, Examiner notes it is well known that voltage supply changes also affect the readout of AD conversion processing units in image sensors (see conclusion).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WESLEY JASON CHIU whose telephone number is (571)270-1312. The examiner can normally be reached Mon-Fri: 8am-4pm.
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/WESLEY J CHIU/ Examiner, Art Unit 2639
/TWYLER L HASKINS/ Supervisory Patent Examiner, Art Unit 2639