DETAILED ACTION
1. This office action is in response to the Application No. 15931664 filed on 08/27/2025. Claims 15 and 20 have been cancelled. Claims 1-14 and 16-19 are presented for examination and are currently pending.
Response to Arguments
2. Upon further review, the arguments of the Applicant have been considered and are persuasive, as a result, the prior art rejection has been withdrawn.
However, a new 112(a) rejection has been issued. The 112(a) have to be overcome for the claims to be allowed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
3. Claims 1-14 and 16-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “splitting an input layer or an output layer of a first neural network into constituent portions”. This limitation does not appear to have support in instant specification of the Applicant.
Claim 1 further recites “splitting an input layer or an output layer of a second neural network into constituent portions”. This limitation does not appear to have support in instant specification of the Applicant.
The Applicant’s specification at [0045] discloses that “In some embodiments, the control circuitry 220 can control splitting the entire neural networks into the constituent portions or sub-sets. By allowing for a neural network to be split into smaller constituent portions or sub-sets, storing and/or training of neural networks can be realized within the storage limitations of a memory device 204 that includes multiple memory banks 221-0 to 221-N”.
The Applicant’s specification discloses as cited above splitting a neural network into subsets which can be understood to include splitting a neural network into input, hidden and output layers into subsets. However, splitting an entire neural network which the Applicant has support for is different from splitting an input layer which is a subset of a neural network.
Claims 2-7 that are not specifically mentioned are rejected due to dependency.
Claim 8 recites “control splitting an input layer or an output layer of a first trained neural network into constituent portions”. This limitation does not appear to have support in instant specification of the Applicant.
Claim 8 further recites “control splitting an input layer or an output layer of a second untrained neural network into constituent portions”. This limitation does not appear to have support in instant specification of the Applicant.
The Applicant’s specification at [0045] discloses that “In some embodiments, the control circuitry 220 can control splitting the entire neural networks into the constituent portions or sub-sets. By allowing for a neural network to be split into smaller constituent portions or sub-sets, storing and/or training of neural networks can be realized within the storage limitations of a memory device 204 that includes multiple memory banks 221-0 to 221-N”.
The Applicant’s specification discloses as cited above control splitting a neural network into subsets which can be understood to include splitting a neural network into input, hidden and output layers into subsets. However, control splitting an entire neural network which the Applicant has support for is different from control splitting an input layer which is a subset of a neural network.
Claim 14 recites “control splitting an input layer or an output layer of the trained or untrained neural network into constituent portions”. This limitation does not appear to have support in instant specification of the Applicant.
The Applicant’s specification at [0045] discloses that “In some embodiments, the control circuitry 220 can control splitting the entire neural networks into the constituent portions or sub-sets. By allowing for a neural network to be split into smaller constituent portions or sub-sets, storing and/or training of neural networks can be realized within the storage limitations of a memory device 204 that includes multiple memory banks 221-0 to 221-N”.
The Applicant’s specification discloses as cited above control splitting a neural network into subsets which can be understood to include splitting a neural network into input, hidden and output layers into subsets. However, control splitting an entire neural network which the Applicant has support for is different from control splitting an input layer which is a subset of a neural network.
Claims 9-13 and 16-19 that are not specifically mentioned are rejected due to dependency.
Allowable Subject Matter
4. Claims 1-14 and 16-19 would be allowable if rewritten to overcome the 35 USC 112(a) rejection.
The closest prior art of record is Lea modified by Lee and Luo.
Lea discloses the write circuitry 148 can be used to write data to the memory array 130 [0029]; on one or more memory banks 521 of a memory device 520 [0078]; each bank 521-1, . . . , 521-7 (referred to generally as 521) ... Eight banks are shown in the example of FIG. 5 [0078], Fig. 5; As shown in the example embodiment of FIG. 2, a plurality of neural networks 296-1, . . . , 296-M in a memory device 220 can receive a particular portion of data and a controller 240 [0044]; on one or more memory banks 521 of a memory device 520 [0078]; each bank 521-1, . . . , 521-7 (referred to generally as 521) ... Eight banks are shown in the example of FIG. 5 [0078], Fig. 5; additional logic circuitry 170 associated with the array of memory cells 130, e.g., DRAM arrays, shown in FIG. 1A [0083]; As such, sensing circuitry 150, compute unit, and logic 170 shown in FIG. 1A can be associated to the arrays of memory cells 130 using shared I/O line shown as 555-1, . . . , 555-7 in FIG. 5. The controllers 540-1, . . . , 540-7 may control regular DRAM operations for the arrays such as a read, write, copy, and/or erase operations, etc [0082]; As such, various compute functions can be performed using, and within, sensing circuitry 150 rather than (or in association with) being performed by processing resources external to the sensing circuitry 150 (e.g., by a processor associated with host 110 [0032]; For example, the sensing circuitry 150 described herein can be formed on a same pitch as a pair of complementary sense lines (e.g., digit lines) [0035]); Additional compute circuitry, as described herein, can be coupled to the sensing circuitry 150 and can be used in combination with the sense amplifiers to …, perform compute functions (e.g., operations) [0029]; In a number of embodiments, a plurality of neural networks can be operated simultaneously on a particular portion of data [0015];
Lee teaches Accordingly, the processor 110 of the neural network quantization apparatus 10 quantizes the floating-point neural network 410 to a fixed-point neural network 420, for example, a 16-bit or low fixed-point type [0090]; Furthermore, the processor 110 retrains the fixed-point type neural network 1620 using new or existing training set data and test set data to increase an accuracy of the quantized neural network 1620 [0162]; he memory 120 is hardware for storing various pieces of data processed in the neural network quantization apparatus 10 [0079];
Luo teaches cooperative learning neural network 126 [0011], Fig. 1; Training may involve supervised training—e.g., comparing the classification of the input values with a known actual classification of the input values [0033]; (sensor(s) 108 and sensor(s) 118 [0011], Fig. 1); memory 114 and memory 124 [0011], Fig. 1; Memory which may be used to implement cooperative learning neural networks described herein generally may include any number or type of memory devices, including … DRAM [0020]; cooperative learning neural network 128 [0011], Fig. 1; In some examples, training may involve unsupervised training [0033]; Sensor data may be received by cooperative learning neural network 126, for example from sensor(s) 108 … Sensor data from vehicle 104 may be provided to cooperative learning neural network 126 (e.g., from sensor(s) 118 [0023]; Both sets of sensor data, separately or in combination, may be used to train the cooperative learning neural network 126 to develop a set of weights indicative of a precursor to the collision condition [0023].
However, neither Lea modified by Lee and Luo, disclose, as argued by the Applicant on page 18 of the Applicant’s remark dated 08/27/2025, “the neural network data is split into constituent portions and stored across a plurality of memory banks within the memory and within a plurality of periphery sense amplifiers coupled to the memory such that each memory bank stores at least one constituent portion of the neural network and the plurality of periphery sense amplifiers stores at least one constituent portion of the neural network”, in combination with the other limitations of the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MORIAM MOSUNMOLA GODO whose telephone number is (571)272-8670. The examiner can normally be reached Monday-Friday 8am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michelle T Bechtold can be reached on (571) 431-0762. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.G./Examiner, Art Unit 2148
/MICHELLE T BECHTOLD/Supervisory Patent Examiner, Art Unit 2148
Prosecution Insights