DETAILED ACTION
Claims 1-20 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 8, 10, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 2014/0152675 A1 to Martin et al. in view of U.S. Pub. No. 2011/0078417 A1 to Fahs et al.
As to claim 1, Martin teaches a processor comprising:
a plurality of compute units, where each of the compute units comprises circuitry configured to execute instructions (SEs 106/CU 202 paragraph 0078); and
dispatch (WD 102/IA 104/VGT 108) the individual wavefronts (prim group/wavefronts) of the first workgroup (workgroup/thread groups) to separate multiple two or more compute units of the plurality of compute units (SEs 106/CU 202/SEs 106 use multiple compute units)) (“...In an embodiment, WD 102 distributes the work to other components in a graphics pipeline for parallel processing. WD 102 receives patches from a driver that include instructions for rendering primitives on a display screen. The driver receives patches from a graphics application. Once the driver receives patches from the graphics application, it uses a communication interface, such as a communication bus, to transmit patches to a graphics pipeline that begins with WD 102. In an embodiment, WD 102 divides patches into multiple work groups that are processed in parallel using multiple SEs 106...In an embodiment, to transmit work groups to SEs 106, WD 102 passes work groups to IAs 104. In an embodiment, there may be multiple IAs 104 connected to WD 102. IAs 104 divide workgroups into primitive group (also referred to as "prim groups"). IA 104 then passes the prim groups to SEs 106. In an embodiment, each IA 104 is coupled to two SEs 106. IAs 104 may also retrieve data that is manipulated using instructions in the patches, and performs other functions that prepare patches for processing using SEs 106...In another embodiment, WD 102 may distribute prim groups directly to SEs 106. In this embodiment, the functionality of IA 104 may be included in WD 102 or in SE 106. In this case, WD 102 divides a draw call into multiple prim groups and passes a prim group to SE 106 for processing. This configuration allows WD 102 to scale the number of prim groups to the number of SEs 106 that are included in the graphics pipeline...In an embodiment, SEs 106 process prim groups. For example, SEs 106 use multiple compute units to manipulate the data in each prim group so that it is displayed as objects on a display screen...In an embodiment, VGTs 108 begin processing each thread group from a prim group that it receives from IA 104. VGTs 108 divide thread groups into wave fronts (also referred to as "waves"), where each wave front includes a number of threads that are processed in parallel. VGT 108 then launches the waves to other components in SEs 106, such as SPI 110 and compute unit…” paragraphs 0024-0027/0036);
wherein the processor comprises circuitry configured to:
dispatch individual wavefronts (prim group/wavefronts) of a first workgroup (workgroup/thread groups) to two or more compute units of the plurality of compute units (SEs 106 use multiple compute units) such that the first workgroup is not allocated entirely to any single compute unit of the plurality of compute units (WD 102 divides patches into multiple work groups that are processed in parallel using multiple SEs 106) (“...In an embodiment, WD 102 distributes the work to other components in a graphics pipeline for parallel processing. WD 102 receives patches from a driver that include instructions for rendering primitives on a display screen. The driver receives patches from a graphics application. Once the driver receives patches from the graphics application, it uses a communication interface, such as a communication bus, to transmit patches to a graphics pipeline that begins with WD 102. In an embodiment, WD 102 divides patches into multiple work groups that are processed in parallel using multiple SEs 106...In an embodiment, to transmit work groups to SEs 106, WD 102 passes work groups to IAs 104. In an embodiment, there may be multiple IAs 104 connected to WD 102. IAs 104 divide workgroups into primitive group (also referred to as "prim groups"). IA 104 then passes the prim groups to SEs 106. In an embodiment, each IA 104 is coupled to two SEs 106. IAs 104 may also retrieve data that is manipulated using instructions in the patches, and performs other functions that prepare patches for processing using SEs 106...In another embodiment, WD 102 may distribute prim groups directly to SEs 106. In this embodiment, the functionality of IA 104 may be included in WD 102 or in SE 106. In this case, WD 102 divides a draw call into multiple prim groups and passes a prim group to SE 106 for processing. This configuration allows WD 102 to scale the number of prim groups to the number of SEs 106 that are included in the graphics pipeline...In an embodiment, SEs 106 process prim groups. For example, SEs 106 use multiple compute units to manipulate the data in each prim group so that it is displayed as objects on a display screen... In an embodiment, VGTs 108 begin processing each thread group from a prim group that it receives from IA 104. VGTs 108 divide thread groups into wave fronts (also referred to as "waves"), where each wave front includes a number of threads that are processed in parallel. VGT 108 then launches the waves to other components in SEs 106, such as SPI 110 and compute unit…” paragraphs 0024-0027/0036) and
store state information for the first workgroup (HS data), the state information identifying the two or more compute units (“…CU 202 stores the HS data generated using the HS wave as HS output 218 in LDS 210…In an embodiment, once CU 202 completes processing an HS wave of a thread group, HS 206 may copy the tessellation factors and HS output 218 from LDS 210 to global memory 212. For example, global memory 212 may also store HS output 218…” paragraphs 0051/0056).
Martin is silent with reference to the state information indicating a count of wavefronts of the first workgroup that have reached a synchronization point;
receive indications that corresponding wavefronts of the first workgroup have reached the synchronization point and
in response to the count equaling a total number of wavefronts of the first workgroup, convey a control signal to the two or more compute units identified by the state information to enable continued execution of the wavefronts of the first workgroup.
Fahs teaches the state information indicating a count (Arrival Counter 504) of wavefronts of the first workgroup that have reached a synchronization point (“…When the selected instruction is a barrier instruction, barrier detection circuit 512 directs the instruction to barrier instruction execution unit 500; otherwise, barrier detection circuit 512 forwards the instruction to the next issue stage for eventual delivery to execution units 302. Barrier instruction execution unit 500 includes an arrival counter 504, a target register 503, a comparison circuit 506, wait/go registers 508, and an aggregation unit 515. The arrival counter 504 tracks the number of threads that have arrived at the barrier point. The target register 503 stores a target value which corresponds to the number threads (or thread groups) that participate in the instruction, i.e., are expected to arrive at the barrier point. In one embodiment, the target value is supplied as an immediate operand with the barrier instruction and is loaded into the target register 503 by barrier detection circuit 512 when the barrier instruction is first executed by a thread (when a barrier instruction is received and the arrival counter is zero). Once loaded, the target value advantageously remains stored in the target register 503 until the target register is reset. When the first thread participating in the barrier instruction that specifies a reduction or scan operation reaches the barrier instruction, the aggregation unit 515 and any registers storing the aggregation result value are initialized…The comparison circuit 506 determines whether the number of arriving threads counted by the counter 504 has reached the target value stored in the target register 503. If the target value has been reached, then the comparison circuit 506 issues a reset signal to the arrival counter 504, the target register, and the wait/go registers to release the barrier…” paragraphs 0067/0068),
receive indications that corresponding wavefronts of the first workgroup have reached the synchronization point (“…When the selected instruction is a barrier instruction, barrier detection circuit 512 directs the instruction to barrier instruction execution unit 500; otherwise, barrier detection circuit 512 forwards the instruction to the next issue stage for eventual delivery to execution units 302. Barrier instruction execution unit 500 includes an arrival counter 504, a target register 503, a comparison circuit 506, wait/go registers 508, and an aggregation unit 515. The arrival counter 504 tracks the number of threads that have arrived at the barrier point. The target register 503 stores a target value which corresponds to the number threads (or thread groups) that participate in the instruction, i.e., are expected to arrive at the barrier point. In one embodiment, the target value is supplied as an immediate operand with the barrier instruction and is loaded into the target register 503 by barrier detection circuit 512 when the barrier instruction is first executed by a thread (when a barrier instruction is received and the arrival counter is zero). Once loaded, the target value advantageously remains stored in the target register 503 until the target register is reset. When the first thread participating in the barrier instruction that specifies a reduction or scan operation reaches the barrier instruction, the aggregation unit 515 and any registers storing the aggregation result value are initialized…The comparison circuit 506 determines whether the number of arriving threads counted by the counter 504 has reached the target value stored in the target register 503. If the target value has been reached, then the comparison circuit 506 issues a reset signal to the arrival counter 504, the target register, and the wait/go registers to release the barrier…” paragraphs 0067/0068), and
in response to the count equaling a total number of wavefronts of the first workgroup, convey a control signal (Aggregation Result 515) to the compute units identified by the state information to enable continued execution of the wavefronts of the first workgroup (Comparison Circuit 506) (“…The comparison circuit 506 determines whether the number of arriving threads counted by the counter 504 has reached the target value stored in the target register 503. If the target value has been reached, then the comparison circuit 506 issues a reset signal to the arrival counter 504, the target register, and the wait/go registers to release the barrier… In operation, when the barrier instruction execution unit 500 receives a first barrier aggregation instruction, the target value is loaded into the target register 503 and the aggregation unit 515 may be initialized as needed for the aggregation operation. Alternatively, the aggregation unit 515 may be initialized when the last thread participating in a barrier instruction receives the barrier aggregation instruction. The aggregation unit 515 performs the aggregation operations and updates an aggregation result value stored in the aggregation unit 515 when each thread group executes the barrier instruction…The comparison circuit 506 compares the current value in the counter 504 to the target value stored in the target register 503. If the current value matches the target value, then the threads are properly synchronized and execution of any waiting threads can resume. Accordingly, the comparison circuit 506 generates a reset signal. The reset signal resets the counter 504 to zero, resets the target register 503 to an "unloaded" state (so that a new target value can be read in when the next barrier instruction is encountered), and resets the wait/go registers 508 such that the bits corresponding to all of the thread groups that were formerly waiting at the barrier point, allowing execution of those thread groups to proceed beyond the barrier point…The comparison circuit 536 determines whether the number of threads counted by the arrival counter 534 for any one of the B barrier points has reached the corresponding target value stored in the target register 535. If a target value is reached for a particular BarID, the comparison circuit 536 issues a reset signal to the arrival counter 534, the target register 535, and the wait/go registers 538 associated with the BarID…” paragraphs 0068/0070/0074/0079).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Martin with the teaching of Fahs because the teaching of Fahs would improve the system of Martin by providing a counter for tracking and accumulating the number of threads that have reached a synchronization or barrier point and totaling the number of thread for optimal computation.
As to claim 3, Fahs teaches the processor as recited in claim 1, wherein the processor further comprises a scoreboard or other state-tracking circuitry (Arrival Counter 504), and wherein the processor is further configured to:
allocate an entry in the scoreboard to track wavefronts of the first workgroup (Arrival Counter 504);
track, in the entry, a number of wavefronts of the first workgroup which have reached a given barrier synchronization point (Arrival Counter 504); and
initiate synchronization among two or more compute units of the plurality of compute units to allow wavefronts of the first workgroup to proceed when the number of wavefronts of the first workgroup which have reached the synchronization point is equal to a total number of wavefronts in the first workgroup (“…When the selected instruction is a barrier instruction, barrier detection circuit 512 directs the instruction to barrier instruction execution unit 500; otherwise, barrier detection circuit 512 forwards the instruction to the next issue stage for eventual delivery to execution units 302. Barrier instruction execution unit 500 includes an arrival counter 504, a target register 503, a comparison circuit 506, wait/go registers 508, and an aggregation unit 515. The arrival counter 504 tracks the number of threads that have arrived at the barrier point. The target register 503 stores a target value which corresponds to the number threads (or thread groups) that participate in the instruction, i.e., are expected to arrive at the barrier point. In one embodiment, the target value is supplied as an immediate operand with the barrier instruction and is loaded into the target register 503 by barrier detection circuit 512 when the barrier instruction is first executed by a thread (when a barrier instruction is received and the arrival counter is zero). Once loaded, the target value advantageously remains stored in the target register 503 until the target register is reset. When the first thread participating in the barrier instruction that specifies a reduction or scan operation reaches the barrier instruction, the aggregation unit 515 and any registers storing the aggregation result value are initialized…The comparison circuit 506 determines whether the number of arriving threads counted by the counter 504 has reached the target value stored in the target register 503. If the target value has been reached, then the comparison circuit 506 issues a reset signal to the arrival counter 504, the target register, and the wait/go registers to release the barrier…” paragraphs 0067/0068).
As to claims 8 and 15, see the rejection of claim 1, expect for a processor and a memory.
Martin teaches a processor and a memory (“...The embodiments are also directed to computer program products comprising software stored on any computer-usable medium. Such software, when executed in one or more data processing devices, causes a data processing device(s) to operate as described herein or, as noted above, allows for the synthesis and/or manufacture of computing devices (e.g., ASICs, or processors) to perform embodiments described herein. Embodiments employ any computer-usable or -readable medium, known now or in the future. Examples of computer-usable mediums include, but are not limited to, primary storage devices (e.g., any type of random access memory), secondary storage devices (e.g., hard drives, floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices, optical storage devices, MEMS, nano-technological storage devices, etc.), and communication mediums (e.g., wired and wireless communications networks, local area networks, wide area networks, intranets, etc.)...” paragraph 0091).
As to claims 10 and 17, see the rejection of claim 3 above.
Claims 2, 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Claims 1, 3, 8, 10, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 2014/0152675 A1 to Martin et al. in view of U.S. Pub. No. 2011/0078417 A1 to Fahs et al.
as applied to claims 1, 8 and 15 above, and further in view of U.S. Pub. No. 2012/0229481 A1 to McCrary et al.
As to claim 2, Martin as modified by Fahs teaches the processor as recited in claim 1, however it is silent with reference to wherein the individual wavefronts of the first workgroup are dispatched to the two or more compute units in response to the first workgroup not fitting within currently available resources of any single compute unit of the plurality of compute units
McCrary teaches wherein the individual wavefronts of the first workgroup are dispatched to the two or more compute units in response to the first workgroup not fitting within currently available resources of any single compute unit of the plurality of compute units (A disruption in the QoS occurs when all work-items are unable to access APD resources) (“…A disruption in the QoS occurs when all work-items are unable to access APD resources. Embodiments of the present invention facilitate efficiently and simultaneously launching two or more tasks to resources within APD 104, enabling all work-items to access various APD resources. In one embodiment, an APD input scheme enables all work-items to have access to the APD's resources in parallel by managing the APD's workload. When the APD's workload approaches maximum levels, (e.g., during attainment of maximum I/O rates), this APD input scheme assists in that otherwise unused processing resources can be simultaneously utilized in many scenarios. A serial input stream, for example, can be abstracted to appear as parallel simultaneous inputs to the APD…By way of example, each of the CPs 124 can have one or more tasks to submit as inputs to other resources within APD 104, where each task can represent multiple wavefronts. After a first task is submitted as an input, this task may be allowed to ramp up, over a period of time, to utilize all the APD resources necessary for completion of the task. By itself, this first task may or may not reach a maximum APD utilization threshold. However, as other tasks are enqueued and are waiting to be processed within the APD 104, allocation of the APD resources can be managed to ensure that all of the tasks can simultaneously use the APD 104, each achieving a percentage of the APD's maximum utilization. This simultaneous use of the APD 104 by multiple tasks, and their combined utilization percentages, ensures that a predetermined maximum APD utilization threshold is achieved…” paragraphs 0085/0086).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Martin and Fahs with the teaching of McCrary because the teaching of McCrary would improve the system of Martin and Fahs by providing adequate resources for executing a task.
As to claims 9 and 16, see rejection of claim 2 above.
Claims 4, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 2014/0152675 A1 to Martin et al. in view of U.S. Pub. No. 2018/0286005 A1 et al. to Koker et al. and further in view of U.S. Pub. No. 20150309845 A1 to Wilson et al. as applied to claims 1, 8 and 15 above, and further in view of U.S. Pub. No. 2021/0373899 A1 to Vembu et al.
As to claim 4, Martin as modified by Fahs teaches the processor as recited in claim 1, however it is silent with reference to wherein the processor is further configured to determine the process for dispatching the individual wavefronts of the first workgroup to compute units of the plurality of compute units.
Vembu teaches wherein the processor is further configured to determine the process (scheduling policy) for dispatching the individual wavefronts (threads/wavefronts) of the first workgroup to separate compute units of the plurality of compute units (plurality of compute units) (“…At processing block 750, scheduler 613 performs thread scheduling based on a scheduling policy that includes both barrier usage and usual multiprocessor load balancing… wherein the graphics processor includes: a plurality of workgroup processors, each workgroup processor including a plurality of compute units for execution of threads in a plurality of wavefronts, each wavefront including a plurality of threads, and a scheduler to schedule a plurality of wavefronts for execution by the plurality of workgroup processors according to a scheduling policy, the scheduling policy being based at least in part on the barrier usage data, wherein the scheduler is to prioritize scheduling of a set of wavefronts of the plurality of wavefronts to a same workgroup processor of the plurality of workgroup processors upon a determination that the barrier usage data indicates a high magnitude of barrier messages in the set of wavefronts…wherein the scheduling policy is further based on load balancing of wavefronts across the plurality of workgroup processors...” paragraph 0147/claims 21/23).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Martin and Fahs with the teaching of Vembu because the teaching of Vembu would improve the system of Martin and Fahs by providing a load balancing process of distributing a set of tasks over a set of resources to allow for optimal use of computing resources.
As to claims 11 and 18, see the rejection of claim 4 above.
Claims 5, 6, 12, 13, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 2014/0152675 A1 to Martin et al. in view of U.S. Pub. No. 2011/0078417 A1 to Fahs et al. as applied to claims 1, 8 and 15 above, and further in view of U.S. Pat. No. 9,189,282 B2 issued to Conte et al.
As to claim 5, Martin as modified by Fahs teaches the processor as recited in claim 1, however it is silent with reference the processor is further configured to allocate wavefronts of the first workgroup to the plurality of compute units based on load-ratings for each compute units and each resource calculated based on a plurality of monitoring performance counters.
Conte teaches the processor is further configured to allocate wavefronts of the first workgroup to the plurality of compute units based on load-ratings for each compute units and each resource calculated based on a plurality of monitoring performance counters (“...FIG. 6a is a schematic illustration of a system for performing methods for multi-core thread mapping in accordance with the present disclosure. As shown in FIG. 6a, a computer system 600 may include a processor 605 configured for performing an example of a method for mapping threads to execution to processor cores. In other examples, various operations or portions of various operations of the method may be performed outside of the processor 605. In operation 602, the method may include executing at least one software application program resulting in at least one thread of execution. In operation 603, the method may include collecting data relating to the performance of the multi-core processor using a performance counter. In operation 604, the method may include using a core controller to map the thread of execution to a processor core based at least in part on the data collected by the performance counter...FIG. 6b is a schematic illustration of a computer accessible medium having stored thereon computer executable instructions for performing a procedure for mapping threads of execution to processor cores in a multi-core processing system. As shown in FIG. 6b, a computer accessible medium 600 may have stored thereon computer accessible instructions 605 configured for performing an example procedure for mapping threads to execution to processor cores. In operation 602, the procedure may include executing at least one software application program resulting in at least one thread of execution. In operation 603, the procedure may include collecting data relating to the performance of the multi-core processor using a performance counter. In operation 604, the procedure may include using a core controller to map the thread of execution to a processor core based at least in part on the data collected by the performance counter...” Col. 5 Ln. 57 – 67, Col. 6 Ln. 1 – 21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Martin and Fahs with the teaching of Conte because the teaching of Conte would improve the system of Martin and Fahs by providing a technique of mapping threads to execution to processor cores.
As to claim 6, Martin as modified by Fahs teaches the processor as recited in claim 5, however it is silent with reference to wherein the processor is further configured to select a first compute unit of the plurality of compute units as a candidate for dispatch responsive to determining the first compute unit has a lowest load-rating among the plurality of compute units for a first resource.
Conte teaches wherein the processor is further configured to select a first compute unit of the plurality of compute units as a candidate for dispatch responsive to determining the first compute unit has a lowest load-rating among the plurality of compute units for a first resource (“...FIG. 6a is a schematic illustration of a system for performing methods for multi-core thread mapping in accordance with the present disclosure. As shown in FIG. 6a, a computer system 600 may include a processor 605 configured for performing an example of a method for mapping threads to execution to processor cores. In other examples, various operations or portions of various operations of the method may be performed outside of the processor 605. In operation 602, the method may include executing at least one software application program resulting in at least one thread of execution. In operation 603, the method may include collecting data relating to the performance of the multi-core processor using a performance counter. In operation 604, the method may include using a core controller to map the thread of execution to a processor core based at least in part on the data collected by the performance counter...FIG. 6b is a schematic illustration of a computer accessible medium having stored thereon computer executable instructions for performing a procedure for mapping threads of execution to processor cores in a multi-core processing system. As shown in FIG. 6b, a computer accessible medium 600 may have stored thereon computer accessible instructions 605 configured for performing an example procedure for mapping threads to execution to processor cores. In operation 602, the procedure may include executing at least one software application program resulting in at least one thread of execution. In operation 603, the procedure may include collecting data relating to the performance of the multi-core processor using a performance counter. In operation 604, the procedure may include using a core controller to map the thread of execution to a processor core based at least in part on the data collected by the performance counter...” Col. 5 Ln. 57 – 67, Col. 6 Ln. 1 – 21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Martin and Fahs with the teaching of Conte because the teaching of Conte would improve the system of Martin and Fahs by providing a technique of mapping threads to execution to processor cores.
As to claims 12 and 19, see the rejection of claim 5 above.
As to claims 13 and 20, see the rejection of claim 6 above.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 2014/0152675 A1 to Martin et al. in view of U.S. Pub. No. 2011/0078417 A1 to Fahs et al. and further in view of U.S. Pat. No. 9,189,282 B2 issued to Conte et al. as applied to claim 5 above, and further in view of U.S. Pub. No. 2017/0031719 A1 to Clark et al.
As to claim 7, Martin as modified by Fahs and Conte teaches the processor as recited in claim 5, however it is silent with reference to wherein the plurality of performance counters track two or more of vector arithmetic logic unit (VALU) execution bandwidth, scalar ALU (SALU) execution bandwidth, local data share (LDS) bandwidth, Load Store Bus bandwidth, Vector Register File (VRF) bandwidth, Scalar Register File (SRF) bandwidth, cache subsystem capacity, cache bandwidth, and translation lookaside buffer (TLB) bandwidth.
Clark teaches wherein the plurality of performance counters track two or more of vector arithmetic logic unit (VALU) execution bandwidth, scalar ALU (SALU) execution bandwidth, local data share (LDS) bandwidth, Load Store Bus bandwidth, Vector Register File (VRF) bandwidth, Scalar Register File (SRF) bandwidth, cache subsystem capacity, cache bandwidth, and translation lookaside buffer (TLB) bandwidth (Cache Bandwidth 450D, Cache Capacity 450E) (“...Performance counter values 450 may include a plurality of values associated with a given guest VM or a given vCPU of a guest VM, depending on the embodiment. A guest VM may include a plurality of performance counter values 450, and the guest VM may include a different set of performance counter values for a plurality of vCPUs in use by the guest VM. In various embodiments, the performance counter values 450 may include one or more of CPU time 450A, instructions retired 450B, floating point operations (FLOPs) 450C, cache bandwidth 450D, cache capacity 450E, memory bandwidth 450F, memory capacity 450G, I/O bandwidth 450H, and/or fixed function IP usage 450J...” paragraph 0052).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Martin, Fahs and Conte with the teaching of Clark because the teaching of Clark would improve the system of Martin, Fahs and Conte by providing a set of special-purpose registers built into modern microprocessors to store the counts of hardware-related activities within computer systems.
As to claim 14, see the rejection of claim 7 above.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection relies on additional references not applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CHARLES E ANYA/Primary Examiner, Art Unit 2194
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