DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In view of the “Appeal Brief” filed on 10/24/2025 PROSECUTION IS HEREBY REOPENED. A new ground of rejection is set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/DERRICK W FERRIS/Supervisory Patent Examiner, Art Unit 2411
Response to Remarks
This communication is considered fully responsive to the amendment filed on 10/24/2025.
Claims 1-20 is pending and examined.
No claim has been amended.
No claim has been added and no claim has been cancelled.
Response to Arguments
Applicant’s arguments, filed 10/24/2025 , with respect to the rejection(s) of claim(s) under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of BASU et al. (US 7420987 B1; hereinafter as “BASU”).
Allowable Subject Matter
Claims 8-10, 15-17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 11-14, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over FAIRHURST et al. (US 20190334837 A1; hereinafter as “FAIRHURST”) in view of BASU et al. (US 7420987 B1; hereinafter as “BASU”).
Regarding claim 1, FAIRHURST teaches an apparatus (==network switch, Fig. 1-2, Fig. 7) comprising:
a plurality of queues , each configured to store candidate packets of a respective type (see fig. 1; multiple OutPUT Accumulated to FIFOs : [0078]; also fig. 8: multiple Queues : VoQ0, VoQ2… VoQ7 : [0082]-[0083] Queues with Queue blocks C0, C1, C2, … C7 in Fig. 9 (==candidate packets): );
a buffer configured to store a link packet, the link packet comprising data storage space for storing multiple candidate packets ( Queue Block LINK in Fig. 9 ; “ Each cell (or packet) within a VoQ is assigned a slot entry in a Queue Block to hold the cell/packet's control state. The VoQ structure for the VoQ in FIG. 9 is constructed of a linked list of Queue Blocks, where the Queue Block Link database is used to create the links”: [0087]);
a communication fabric interface comprising circuitry configured to transfer data on a link (interface from queues to Queue Block Link database:: [0087]) ;
a packing buffer arbiter comprising circuitry configured to (see fig. 7: Arbiter ):
insert, into the link packet, a candidate packet of a given type from a given queue of the plurality of queues (see fig. 7 Arbiter takes packet from each queues and inset to ToQ / a ToQ block (CQE Queuing), “ The OQS arbiter 720 may use a FIFO ager scheme. The FIFO ager scheme is used to raise the priority of aged FIFOs with shallow fill levels above other non-aged FIFOs also with shallow fill levels. FIFO(s) with high fill levels (aged or not) have highest priority as these have efficient dequeues that provide over speed when selected and free up dequeue bandwidth for less efficient shallow dequeues. The output FIFO ager scheme of the OQS arbiter 720 may further be able to set the ager timer based upon the output port speed and queue high/low priority configuration”: [0081]:) , based at least in part on:
a number of packets of the given type in the link packet ( “OQS arbiter 720 may generate a serial stream of packets.”: [0080]; “ The output FIFO ager scheme of the OQS arbiter 720 may further be able to set the ager timer based upon the output port speed and queue high/low priority configuration. Hence, for example, an output FIFO ager scheme may be used to minimize the delay through the output stage for packets requiring low latency”: [0081]; “ Each cell (or packet) within a VoQ is assigned a slot entry in a Queue Block to hold the cell/packet's control state. The VoQ structure for the VoQ in FIG. 9 is constructed of a linked list of Queue Blocks, where the Queue Block Link database is used to create the links. This VoQ structure has the benefit of allowing multiple cells or packets within a single Queue Block to be read in one access while still supporting the flexible and dynamic allocation of Queue depth to active VoQs. Thus, backlogged queue is constructed of dynamically allocated Queue Blocks. For example, this VoQ structure in FIG. 9 includes a Queue Block implementation containing 8 cells or packets per Queue Block. The cell control holds cell payload memory address. Up to 8 cells can be written to a VoQ Queue Block per clock cycle.”: [0087]).
While FAIRHURST teaches “insert, into the link packet, a candidate packet of a given type from a given queue of the plurality of queues ” FAIRHURST does not expressively disclose:
a minimum number of cycles between transmission of link packets that include packets of the given type to prevent data collision at a receiver that receives the link packet.
BASU, in the same field of endeavor, discloses:
a minimum number of cycles between transmission of link packets that include packets of the given type to prevent data collision at a receiver that receives the link packet (aforesaid Arbiter “ configured to perform arbitration on the respective vectors V0-V2. Vector arbiters 540-560 may be configured to perform round-robin arbitration on each vector V0-V2 in an implementation consistent with principles of the invention. Other types of arbitration (e.g., linear or daisy-chain) are possible. The arbiter 540 outputs the position of the next available queue in mutually exclusive vector V0”: col.5 lines 3-27; NOTE: Arbiter insets packets to OUTPUT QUEUE/Link Packet based on ROUND-ROBIN to avoid collision.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of FAIRHURST to include the above recited limitations as taught by BASU. The suggestion/motivation would be provide an effective routing function of the arbiter.
Regarding claim 2, FAIRHURST in view of BASU teaches claim 1 as above. Furthermore BASU teaches, wherein the minimum number of cycles is based at least in part on the given type ( fig. 1. “ Typically, arbiter 120 performs a certain type of arbitration (e.g., round robin) to pick one FIFO queue 110 and then routes the data in the FIFO queue based on some criteria (e.g., packet size of the data). Other criteria are possible for the routing function of the arbiter 120.”:col.1 lines 24-39 ).
Regarding claim 3, FAIRHURST in view of BASU teaches claim 1 as above. Furthermore FAIRHURST teaches, wherein in response to determining the candidate packet of the give type from the given queue does not satisfy conditions for insertion, the packing buffer arbiter is further configured to reduce a priority of the given queue until detecting one of: a candidate packet is inserted into the link packet; and the link packet is sent (“ The OQS arbiter 720 may use a FIFO ager scheme. The FIFO ager scheme is used to raise the priority of aged FIFOs with shallow fill levels above other non-aged FIFOs also with shallow fill levels. FIFO(s) with high fill levels (aged or not) have highest priority as these have efficient dequeues that provide over speed when selected and free up dequeue bandwidth for less efficient shallow dequeues. The output FIFO ager scheme of the OQS arbiter 720 may further be able to set the ager timer based upon the output port speed and queue high/low priority configuration. Hence, for example, an output FIFO ager scheme may be used to minimize the delay through the output stage for packets requiring low latency.”: [0081]).
Regarding claim 4, FAIRHURST in view of BASU teaches claim 1 as above. Furthermore FAIRHURST teaches, wherein one or more of the plurality of queues has a respective limit on a number of packets that are inserted in the link packet in the buffer before the link packet is sent on an available link, wherein each respective limit of the one or more of the plurality of queues is stored in a configuration and status register (“control the buffer space allocated to a logical queue that has several physical queues (VoQs) each using up space. ”: [0041]; “ As discussed above, the packets received via the input ports 520A-520H may be divided into cells via packet processing, such that the cells may be stored and queued at the hybrid-shared traffic manager 510.”:[0046]).
Regarding claim 5, FAIRHURST in view of BASU teaches claim 4 as above. Furthermore FAIRHURST teaches: wherein the packing buffer arbiter is further configured to insert the candidate packet of the give type from the given queue into the link packet in the buffer, in further response to available data storage space in the link packet is aligned to a given boundary of the candidate packet (see fig. 7: arbiter : “ ] The output accumulation FIFOs may be sized to typically avoid creating back pressure when a large packet is written in to an output accumulation FIFO. The OQS arbiter 720 may dequeue more cells per clock cycle from an Output Accumulation FIFO than are written in a clock cycle. This prevents the output accumulation FIFO reaching its maximum fill level and provides additional dequeue bandwidth to read Output Accumulation FIFOs with shallow fill levels. In one or more implementations, each output port or set of output ports may be mapped to an output accumulation FIFO.
[0080] The OQS arbiter 720 can make up to N FIFO selections per clock cycle to attempt to read Y cells per clock where Y may contain overspeed compared to the number of cells received by the ITM from its Ingress Pipelines in one clock cycle. Different implementations may have different values of N and Y to meet the switch requirements. In an example, N may be 1 and Y may be 6, in another example N may be 2 and Y may be 8. The OQS arbiter 720 may generate a serial stream of packets. For example, the OQS arbiter 720 may completely drain one output accumulation FIFO to end of packet before switching to a different output accumulation FIFO. The output accumulation FIFOs with the deepest fill level (quantized) may have the highest priority followed by FIFOs that have been in a non-empty state the longest.
[0081] The OQS arbiter 720 may use a FIFO ager scheme. The FIFO ager scheme is used to raise the priority of aged FIFOs with shallow fill levels above other non-aged FIFOs also with shallow fill levels. FIFO(s) with high fill levels (aged or not) have highest priority as these have efficient dequeues that provide over speed when selected and free up dequeue bandwidth for less efficient shallow dequeues. The output FIFO ager scheme of the OQS arbiter 720 may further be able to set the ager timer based upon the output port speed and queue high/low priority configuration. Hence, for example, an output FIFO ager scheme may be used to minimize the delay through the output stage for packets requiring low latency.
”: [0079]-[0081]).
10 Regarding claim 6, FAIRHURST in view of BASU teaches claim 1 as above. Furthermore BASU teaches, wherein the minimum number of cycles has: a first value for packets of the given type; and a second value different from the first value, for packets of a type different than the given type (Col. 5 lines 1-34).
15 Regarding claim 7, FAIRHURST in view of BASU teaches claim 1 as above. Furthermore FAIRHURST teaches, wherein, the packing buffer arbiter is further configured to maintain each of:
a first count of enabled network cycles, each allowing a next link packet to use the link; and a second count of a number of candidate packets of a given type inserted in a link packet; and in response to a sum based on at least in part on the second count being less than the first count, insert the candidate packet of the given type into the next link packet ([0070]-[[082]).
Regarding claim 11, FAIRHURST in view of BASU teaches claim 2 as above. Furthermore FAIRHURST teaches, wherein the packing buffer arbiter is further configured to: select a first queue of the plurality of queues, in response to the first queue having a highest priority of the plurality of queues; and send the link packet from the buffer to a receiver, via the link, without inserting a candidate packet from the first queue into the link packet, in response to: the link is available; and the link packet in the buffer is non-empty ([0070]-[[082]).
Regarding claim 12, the claim is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 13, the claim is interpreted and rejected for the same reason as set forth in claim 2.
Regarding claim 14, the claim is interpreted and rejected for the same reason as set forth in claim 7.
Regarding claim 18, the claim is interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 19, the claim is interpreted and rejected for the same reason as set forth in claim 4.
Regarding claim 20, the claim is interpreted and rejected for the same reason as set forth in claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to M MOSTAZIR RAHMAN whose telephone number is (571)272-4785. The examiner can normally be reached 8:30am-5:00pm PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Derrick Ferris can be reached at 571-272-3123. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M Mostazir Rahman/Examiner, Art Unit 2411
/DERRICK W FERRIS/Supervisory Patent Examiner, Art Unit 2411
Prosecution Insights