DETAILED ACTION
Examiner Remarks
In light of Applicant’s Remarks filed on 01/19/2026, Examiner has withdrawn the objections to claim 9 and has also withdrawn the l 12(b) rejections for claims 29-36.
Response to Arguments
Applicant argues that none of the prior art references teach the newly added claim limitations of claim 9. See pgs., 2-3 of Applicant’s Remarks filed on 01/19/2026.
Examiner respectfully disagrees. With respect to the newly added claim limitation of a single parallel processor having an input buffer sized for a plurality of feature vectors from a same stream of data or different streams of data the prior art of Merrill in view of Kim teaches this claim limitation. As detailed in the Non-Final Rejection of 09/24/2025 the prior art of Merrill teaches the claim limitation of a single parallel processor. See the Current Office Action for the detailed teaching. Furthermore, the prior art of Kim pgs., 8-12 teaches the claim elements of having an input buffer sized for a plurality of feature vectors from a same stream of data or different streams of data. See the Current Office Action for the detailed teaching.
Applicant however argues that the prior art of Kim does not teach the above claim elements because Kim does not teach batch accumulation in an input buffer. See pgs., 8-9 of Applicant’s Remarks submitted on 01/19/2026 (stating that Kim does not teach batch accumulation in an input buffer)(Emphasis added). In response to Applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which Applicant relies upon (i.e., batch accumulation in an input buffer) are not recited in the above claim elements. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
With respect to the second newly added claim limitation of storage storing weight datasets for a neural network evaluation, wherein the plurality of feature vectors is evaluated as a batch by the parallel processor based on a weight dataset loaded once from the storage for the neural network evaluation the prior art of Merrill in view of Kim teaches this claim limitation. As detailed in the Non-Final Rejection of 09/24/2025 the prior art of Merrill teaches the claim limitation of storage storing weight datasets for a neural network evaluation and the parallel processor. See the Current Office Action for the detailed teaching. The prior art of Kim pgs., 6-8 teaches the claim elements of wherein the plurality of feature vectors is evaluated as a batch and based on a weight dataset loaded once from the storage for the neural network evaluation. See the Current Office Action for the detailed teaching.
Applicant however argues that the prior art of Kim does not teach the above claim elements because Kim does not teach the claimed loaded once element since repeated weight accesses and modifications of the weights is what Kim teaches. See pgs., 9-10 of Applicant’s Remarks submitted on 01/19/2026 (stating that Kim never teaches loading a neural-network weight dataset once from the storage and then performing batch inference on multiple feature vectors using that same weight dataset since forming
∆
(WY) updates across a training batch involves repeated weight accesses and modification during training)(Emphasis added). In response to Applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which Applicant relies upon (i.e., batch inference on multiple feature vectors using that same weight dataset) are not recited in the above claim elements. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Applicant’s assertion that Kim does not load the weights once and are held fixed for batch evaluation is wrong. As Kim recites on page 8, “[a]fter training is complete, the network may be run in execution-only mode, during which output activities h are computed as in phases 1 and 2, but no weight updates are performed....”(Emphasis added). Accordingly, once training is complete, the neural network is run in execution-only mode, in which the weights are loaded in one time and held fixed to compute the output for h.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-12, 29-33, 35-41 and 43-44 are rejected under 35 U.S.C. 103 as being unpatentable over Merrill et al. US 2016/0210550 Al (“Merrill”) in view of Kim, Lok-Won et al.,"A fully pipelined fpga architecture of a factored restricted boltzmann machine artificial neural network." ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7.1 (2014)(“Kim”).
Regarding claim 9, Merrill teaches a system comprising:
a single parallel processor [having an input buffer sized for a plurality of feature vectors from a same stream of data or different streams of data](Merrill, paras. 0030-0035, see also figs. 2 and 5, “Reference is now made to FIG. 2, a diagram of a simple neural network processor (NNP) architecture, which may comprise a plurality of inner product units (IPUs) 26, each of which may be driven in parallel by an input bus 25[a single parallel processor]);1
and storage storing weight datasets for a neural network evaluation [wherein the plurality of feature vectors is evaluated as a batch] by the parallel processor [based on a weight dataset loaded once from the storage for the neural network evaluation](Merrill paras. 0052-0053, see also fig. 12, “[M]ultiple copies of the NNP[by the parallel processor] may be configured to each compute one respective layer of a neural network[for a neural network evaluation]… the Global Controller 20 may control the transfer of neural network weights from the I/O Interface 22 to one or more Queues 127 [and storage storing weight datasets, including the particular weight dataset]in each of one or more chips containing the IPUs 26.”).2
While Merrill does teach the parallel processor, Merrill does not teach: an input buffer sized for a plurality of feature vectors from a same stream of data or different streams of data; wherein the plurality of feature vectors is evaluated as a batch based on a weight dataset loaded once from the storage for the neural network evaluation.
However, Kim teaches:
an input buffer sized for a plurality of feature vectors from a same stream of data or different streams of data(Kim, pgs., 8, see also figs., 3 and 4, As figs 3 and 4 detail as shown below:
PNG
media_image1.png
447
781
media_image1.png
Greyscale
During the Generate Phase a two-dimensional batch of input cases X and Y are buffered as shown by the blue square of fig. 3 and by the Buffer of Phase 1 of fig. 4[an input buffer sized for a plurality of feature vectors] & Kim, pgs., 19, “[T]he bit-streams are downloaded into the FPGA[from a same stream of data or different streams of data]....” );3
wherein the plurality of feature vectors is evaluated as a batch based on a weight dataset loaded once from the storage for the neural network evaluation(Kim, pgs., 4-12, see also fig. 4 “[W]e deal with the implementation of a conditional fRBM[Factored Restricted Boltzmann Machine]... [w]e will label each input pair...by a “presentation” (or “case”)... [and] [w]e will use
N
c
to denote the number of presentations (cases) in each batch[wherein the plurality of feature vectors is evaluated as a batch]... [a]fter training is complete, the network may be run in execution-only mode[for the neural network evaluation], during which output activities h are computed as in phases 1 and 2, but no weight updates are performed[based on a weight dataset loaded once]... [t]he RAM blocks for storing weight values are in turn divided into two categories, for connection weight values such as WX,WY, and WH and for bias weight values such as WYB and WHB [from the storage]. ”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Merrill with the teachings of Kim the motivation to do so would be to implement mini-batch training using a parallel processor such as a field programmable gate array (FPGA) for streaming data(Kim, pg., 2, “We present a design that exploits the use of “mini-batch” ANN training (common in software implementations) by using a fully pipelined parallel architecture that allows input data to be streamed while keeping the pipeline nearly full at all times. This design significantly increases performance and decreases intermediate result memory requirements, by comparison with alternative ANN architectures that either operate on a single input case at a time…or duplicate hardware to operate independently on multiple cases in parallel.”).
Regarding claim 10, Merrill in view of Kim teaches the system of claim 9, wherein the parallel processor is a field programmable gate array (FPGA)(Merrill, para. 0051, “[A] Neural Network Processor may be distributed across multiple FPGAs…or multiple Neural Network Processors may reside within one FPGA[wherein the parallel processor is a field programmable gate array (FPGA)]….”).
Regarding claim 11, Merrill in view of Kim teaches the system of claim 10, further comprising: a plurality of processing cores operatively coupled to the parallel processor, the plurality of processing cores executing audio, speech, or image processing(Merrill, paras. 0065-0067, see also fig. 15, “The user requests may be, for example, queries with respect to textual, sound and/or visual data, which require some form of pattern recognition…data associated with each user request may be sent through the NetworkAPI 158 to an initiator 155, which may be tightly coupled 150 to one or more of the same or different types of processors 156[a plurality of processing cores operatively coupled to the parallel processor, the plurality of processing cores executing audio, speech, or image processing]….”).4
Regarding claim 12, Merrill in view of Kim teaches the system of claim 11, wherein the parallel processor is operatively coupled to receive at least one observation vector for a process executing on at least one of a plurality of processing cores and communicate an evaluation output to a respective at least one of the plurality of processing cores(Merrill, paras. 0064-0068, see also fig. 15, “[A] cloud-based neural network system may be composed of a heterogeneous combination of processors, GPUs and/or specialized hardware, which may include, but is not limited to, a plurality of FPGAs that may each contain a large number processing units… [f]or each user request, the dispatcher 153 may extract the data from the User API 148 and/or the Cache 154, assign the request to an appropriate neural network, and may load the neural network user request and the corresponding input data into a queue for the specific neural network within the queues 159[wherein the parallel processor is operatively coupled to receive at least one observation vector for a process]. Thereafter, when an appropriate configuration is available, data associated with each user request may be sent through the Network API 158 to an initiator 155, which may be tightly coupled 150 to one or more of the same or different types of processors 156[executing on at least one of a plurality of processing cores]… [u]pon completion of the execution of a user request on a one or more processors 156, the results may be sent back to the User API 148 via the associated initiator 155 through the Network API 158[and communicate an evaluation output to a respective at least one of the plurality of processing cores].”).
Referring to independent claim 29, it is rejected on the same basis as independent claim 9 since they are analogous claims.
Regarding claim 30, Merrill in view of Kim teaches the method of claim 29, wherein the parallel processor is a field programmable gate array (FPGA)(Kim, pg., 19, “To verify the proposed hardware architecture, we have performed experiments on an FPGA-based board which includes a Xilinx Field-Programmable Gate Array (Virtex 5 LX330) [is a field programmable gate array (FPGA)], 8 4MB SRAM memory devices, 1 GB DDR memory, and 1 GBit host Ethernet interface.”).5
Regarding claim 31, Merrill in view of Kim teaches the method of claim 29, wherein the parallel processor is a graphics processing unit (GPU)(Merrill, para. 0066, “The types of neural network processors 156 may include, but are not limited to, a reconfigurable interconnect NNP, a fixed-architecture NNP, a GPU[is a graphics processing unit (GPU)], standard multi-processors, and/or virtual machines.”).
Regarding claim 32, Merrill in view of Kim teaches the method of claim 29, further comprising: executing, by a plurality of processing cores operatively coupled to the parallel processor, audio, speech, or image processing(Kim, pgs., 17-19, “We used the following toy-sized problem for simulation and testing of the fRBM algorithm on the FPGA[: executing, by a plurality of processing cores operatively coupled to the parallel processor]... the input vector X for each case is a random set of binary pixels laid out in 2-d. The input Y for the same case is the same as X, but shifted vertically and/or horizontally by a random number of pixels with respect to X, with wraparound in both dimensions[image processing]”).6
Regarding claim 33, Merrill in view of Kim teaches the method of claim 3, wherein the parallel processor is operatively coupled to receive one observation vector for a process executing on one of the plurality of processing cores and communicate an evaluation output to a respective one of the plurality of processing cores(Merrill, para. 0038, “[A]t any given layer of the neural network, multiple IPUs 26 may process a single node, or multiple nodes may be processed by a single IPU 26.Reference is now made to FIG. 7, a diagram depicting an example of the operation of a multi-word NNP. The first column shows the input values (
I
1
through
I
n
) and two output cycles (
o
u
t
0
and
o
u
t
1
). The last column shows the clock cycle of the operation.”).
Regarding claim 35, Merrill in view of Kim teaches the method of claim 29, further comprising: coordinating a timing of communicating data between the storage storing the weight datasets and the parallel processor(Kim, pgs., 13-14, see also fig. 7, “As discussed in previous sections, the proposed architecture is comprised of a coarse grain pipeline consisting of 12 stages. Since matrix multiplication is the dominant operation in the fRBM ANN algorithm, we implement parallel multiplier structures capable of operating on all elements in a matrix row in parallel, thus generating one element of matrix result every time step. Thus, one iteration to process a whole batch of inputs requires
N
N
c
time steps for each of phases 1 to 10, as shown in Figure 7[coordinating a timing of communicating data between the storage storing the weight datasets and the parallel processor], where Nc is the number of cases in the batch and N is the number of inputs per case.”).7
Regarding claim 36, Merrill in view of Kim teaches the method of claim 29, wherein the weight dataset comprises a first layer weight dataset and a second layer weight dataset(Kim, pg., 12, “The RAM blocks for storing weight values are in turn divided into two categories, for connection weight values such as WX,WY,[ wherein the weight dataset comprises a first layer weight dataset] and WH[and a second layer weight dataset] and for bias weight values such as WYB and WHB.”).8
Regarding claim 37, Merrill teaches a method for reducing a memory bandwidth requirement in neural network processing comprising:
accumulating, in an input buffer of a parallel processor, [a plurality of feature vectors from a same stream of data, wherein the input buffer is sized for the plurality of feature vectors]( Merrill, para., 0036, see also figs. 5 and 6, “Reference is now made to FIG. 6, a diagram of an example of a multi-word input buffer 54, as shown in FIG. 5. Each word on the input bus 25 may be loaded into an input buffer or FiFo 62[accumulating, in an input buffer], and the resulting output 63 may be selected 61 from one or more words of the FiFo 62, and one or more words from another IPU's[of a parallel processor] output 45.”);9
and processing, by the parallel processor, [the plurality of feature vectors as a batch based on a weight dataset loaded once from a storage storing weight datasets for the neural network processing]( Merrill, para., 0036, see also figs. 5 and 6, “Reference is now made to FIG. 6, a diagram of an example of a multi-word input buffer 54, as shown in FIG. 5. Each word on the input bus 25 may be loaded into an input buffer or FiFo 62, and the resulting output 63 may be selected 61 from one or more words of the FiFo 62, and one or more words from another IPU's output 45[and processing, by the parallel processor].”).10
While Merrill does teach the parallel processor, Merrill does not teach: a plurality of feature vectors from a same stream of data, wherein the input buffer is sized for the plurality of feature vectors; the plurality of feature vectors as a batch based on a weight dataset loaded once from a storage storing weight datasets for the neural network processing.
However, Kim teaches:
a plurality of feature vectors from a same stream of data, wherein the input buffer is sized for the plurality of feature vectors (Kim, pgs., 8, see also figs., 3 and 4, As figs 3 and 4 detail as shown below:
PNG
media_image1.png
447
781
media_image1.png
Greyscale
During the Generate Phase a two-dimensional batch of input cases X and Y are buffered as shown by the blue square of fig. 3 and by the Buffer of Phase 1 of fig. 4[wherein the input buffer is sized for the plurality of feature vectors] & Kim, pgs., 19, “[T]he bit-streams are downloaded into the FPGA[a plurality of feature vectors from a same stream of data]....” );
the plurality of feature vectors as a batch based on a weight dataset loaded once from a storage storing weight datasets for the neural network processing (Kim, pgs., 4-12, see also fig. 4 “[W]e deal with the implementation of a conditional fRBM[Factored Restricted Boltzmann Machine]... [w]e will label each input pair...by a “presentation” (or “case”)... [and] [w]e will use
N
c
to denote the number of presentations (cases) in each batch[the plurality of feature vectors is evaluated as a batch]... [a]fter training is complete, the network may be run in execution-only mode[for the neural network processing], during which output activities h are computed as in phases 1 and 2, but no weight updates are performed[based on a weight dataset loaded once]... [t]he RAM blocks for storing weight values are in turn divided into two categories, for connection weight values such as WX,WY, and WH and for bias weight values such as WYB and WHB [from a storage storing weight datasets]. ”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Merrill with the teachings of Kim the motivation to do so would be to implement mini-batch training using a parallel processor such as a field programmable gate array (FPGA) for streaming data(Kim, pg., 2, “We present a design that exploits the use of “mini-batch” ANN training (common in software implementations) by using a fully pipelined parallel architecture that allows input data to be streamed while keeping the pipeline nearly full at all times. This design significantly increases performance and decreases intermediate result memory requirements, by comparison with alternative ANN architectures that either operate on a single input case at a time…or duplicate hardware to operate independently on multiple cases in parallel.”).
Regarding claim 38, Merrill in view of Kim teaches the method of claim 37, wherein the parallel processor is a field programmable gate array (FPGA)(Kim, pg., 19, “To verify the proposed hardware architecture, we have performed experiments on an FPGA-based board which includes a Xilinx Field-Programmable Gate Array (Virtex 5 LX330) [is a field programmable gate array (FPGA)], 8 4MB SRAM memory devices, 1 GB DDR memory, and 1 GBit host Ethernet interface.”).11
Regarding claim 39, Merrill in view of Kim teaches the method of claim 37, further comprising: executing, by a plurality of processing cores operatively coupled to the parallel processor, audio, speech, or image processing(Kim, pgs., 17-19, “We used the following toy-sized problem for simulation and testing of the fRBM algorithm on the FPGA[executing, by a plurality of processing cores operatively coupled to the parallel processor]... the input vector X for each case is a random set of binary pixels laid out in 2-d. The input Y for the same case is the same as X, but shifted vertically and/or horizontally by a random number of pixels with respect to X, with wraparound in both dimensions[image processing]”).12
Regarding claim 40, Merrill in view of Kim teaches the method of claim 39, wherein the parallel processor is operatively coupled to receive one observation vector for a process executing on one of the plurality of processing cores and communicate an evaluation output to a respective one of the plurality of processing cores(Merrill, para. 0038, “[A]t any given layer of the neural network, multiple IPUs 26 may process a single node, or multiple nodes may be processed by a single IPU 26.Reference is now made to FIG. 7, a diagram depicting an example of the operation of a multi-word NNP. The first column shows the input values (
I
1
through
I
n
) and two output cycles (
o
u
t
0
and
o
u
t
1
). The last column shows the clock cycle of the operation.”).
Regarding claim 41, Merrill in view of Kim teaches the method of claim 37, wherein the parallel processor is a graphics processing unit (GPU)(Merrill, para. 0066, “The types of neural network processors 156 may include, but are not limited to, a reconfigurable interconnect NNP, a fixed-architecture NNP, a GPU[is a graphics processing unit (GPU)], standard multi-processors, and/or virtual machines.”).
Regarding claim 43, Merrill in view of Kim teaches the method of claim 37, further comprising: coordinating a timing of communicating data between the storage storing the weight datasets and the parallel processor(Kim, pgs., 13-14, see also fig. 7, “As discussed in previous sections, the proposed architecture is comprised of a coarse grain pipeline consisting of 12 stages. Since matrix multiplication is the dominant operation in the fRBM ANN algorithm, we implement parallel multiplier structures capable of operating on all elements in a matrix row in parallel, thus generating one element of matrix result every time step. Thus, one iteration to process a whole batch of inputs requires
N
N
c
time steps for each of phases 1 to 10, as shown in Figure 7[coordinating a timing of communicating data between the storage storing the weight datasets and the parallel processor], where Nc is the number of cases in the batch and N is the number of inputs per case.”).13
Regarding claim 44, Merrill in view of Kim teaches the method of claim 37, wherein the weight dataset comprises a first layer weight dataset and a second layer weight dataset(Kim, pg., 12, “The RAM blocks for storing weight values are in turn divided into two categories, for connection weight values such as WX,WY,[ wherein the weight dataset comprises a first layer weight dataset] and WH[and a second layer weight dataset] and for bias weight values such as WYB and WHB.”).14
Claims 34 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Merrill et al. US 2016/0210550 Al (“Merrill”) in view of Kim, Lok-Won et al.,"A fully pipelined fpga architecture of a factored restricted boltzmann machine artificial neural network." ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7.1 (2014)(“Kim”) and in view of Li et al., Fpga acceleration of recurrent neural network based language model. In 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines 2015 May 2 ("Li").
Regarding claim 34, Merrill in view of Kim teaches the method of claim 29, but does not teach wherein the neural network evaluation is performed in a recurrent neural network (RNN).
However, Li teaches: wherein the neural network evaluation is performed in a recurrent neural network (RNN)(Li, pgs. 114-116, see also figs. 5, and 7, "We map the proposed parallel architecture of RNNLM into two types of computation engines (CEs): CE-H for the hidden layer and CE-O for the output layer. According to Figure 5, one CE-Hand multiple CE-O are required. The two types of CEs are customized for high efficiency, with the only difference in the design of activation function ... each CE is segmented into several identical processing elements (PEs). Since the majority of RNNLM execution is performed through these PEs, the proposed implementation can easily be migrated to a future device by instantiating more PEs [wherein the neural network evaluation is performed in a recurrent neural network (RNN)].").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Merrill in view of Kim with the teachings of Li the motivation to do so would be to use the reconfigurable nature of FPGA hardware not only to accelerate computational throughput but to also implement different types of neural network architectures based on different applications (Li, pgs., 111-112, "FPGA based accelerators have attracted great attentions for flexible reconfiguration capability and high energy efficiency. FPGA based platform ... used in this work, offers a large number of configurable logic elements and high external memory bandwidth ... [i]n this work, we propose an FPGA implementation framework for RNNLM training acceleration. A holistic approach is adopted which combines the computation efficiency enhancement at architectural level and the memory access load reduction in hardware implementation.").
Regarding claim 42, Merrill in view of Kim teaches the method of claim 37, but does not teach wherein the neural network processing is performed in a recurrent neural network (RNN).
However, Li teaches: wherein the neural network processing is performed in a recurrent neural network (RNN)(Li, pgs. 114-116, see also figs. 5, and 7, "We map the proposed parallel architecture of RNNLM into two types of computation engines (CEs): CE-H for the hidden layer and CE-O for the output layer. According to Figure 5, one CE-Hand multiple CE-O are required. The two types of CEs are customized for high efficiency, with the only difference in the design of activation function ... each CE is segmented into several identical processing elements (PEs). Since the majority of RNNLM execution is performed through these PEs, the proposed implementation can easily be migrated to a future device by instantiating more PEs [wherein the neural network processing is performed in a recurrent neural network (RNN)].").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Merrill in view of Kim with the teachings of Li the motivation to do so would be to use the reconfigurable nature of FPGA hardware not only to accelerate computational throughput but to also implement different types of neural network architectures based on different applications (Li, pgs., 111-112, "FPGA based accelerators have attracted great attentions for flexible reconfiguration capability and high energy efficiency. FPGA based platform ... used in this work, offers a large number of configurable logic elements and high external memory bandwidth ... [i]n this work, we propose an FPGA implementation framework for RNNLM training acceleration. A holistic approach is adopted which combines the computation efficiency enhancement at architectural level and the memory access load reduction in hardware implementation.").
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM C STANDKE whose telephone number is (571)270-1806. The examiner can normally be reached Gen. M-F 9-9PM EST.
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/Adam C Standke/
Primary Examiner
Art Unit 2129
1 Examiner Notes: The claim limitations that are not in bold and contained within square brackets (i.e., [ ]) are
claim limitations that are not taught by the prior art of Merrill.
2 Examiner Notes: The claim limitations that are not in bold and contained within square brackets (i.e., [ ]) are
claim limitations that are not taught by the prior art of Merrill.
3 According to the broadest reasonable interpretation (BRI), the use of alternative language amounts to the claim requiring one or more elements but not all.
4 According to the broadest reasonable interpretation (BRI), the use of alternative language amounts to the claim requiring one or more elements but not all.
5 It would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the teachings of Merrill with the above teachings of Kim for the same rationale stated at Claim 29.
6 According to the broadest reasonable interpretation (BRI), the use of alternative language amounts to the claim requiring one or more elements but not all.
7 It would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the teachings of Merrill with the above teachings of Kim for the same rationale stated at Claim 29.
8 It would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the teachings of Merrill with the above teachings of Kim for the same rationale stated at Claim 29.
9 Examiner Notes: The claim limitations that are not in bold and contained within square brackets (i.e., [ ]) are
claim limitations that are not taught by the prior art of Merrill.
10 Examiner Notes: The claim limitations that are not in bold and contained within square brackets (i.e., [ ]) are
claim limitations that are not taught by the prior art of Merrill.
11 It would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the teachings of Merrill with the above teachings of Kim for the same rationale stated at Claim 37.
12 According to the broadest reasonable interpretation (BRI), the use of alternative language amounts to the claim requiring one or more elements but not all.
13 It would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the teachings of Merrill with the above teachings of Kim for the same rationale stated at Claim 37
14 It would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the teachings of Merrill with the above teachings of Kim for the same rationale stated at Claim 37
Prosecution Insights