DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the RCE filed 10/31/2025.
Claims 1-4, 6, 7, 9-12, 15, 17-19, and 24-26 are pending in this application. Claims 1, 2, 4, 6, 9, 10, 12, 14, 17, and 18 have been amended. Claims 5, 8, 13, 16, and 20-23 have been cancelled.
Request Continuation for Examination
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed 10/07/2025 has been entered.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 6, 7, 9-12, 15, 17-19, and 24-26 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-24 of U.S Patent No. 10140157 in view of US 20090031318.
Although the conflicting claims are not identical, they are not patentably distinct from each other because claim 1 of the instant application and claims 1 and 5 of U.S. patent number 10140157 are both including the same features. The difference between the instant application and US 10140157 is the instant application recites “a priority associated with the group run queue has changed as a result of a change in a priority of the process”. US patent number US 20090031318 teaches a priority associated with the group run queue has changed as a result of a change in a priority of the process ([Fig.7 and [0052-0056]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify U.S. patent number 10140157 with US 20090031318 because it would have provided the enhanced capability for scheduling and processing of threads from multi-core compatible and legacy applications in a multi-core system.
As to remaining claims 2-4, 6, 7, 9-12, 14, 15, 17-19, and 24-26, they are also rejected under obvious type double patenting as stated in claim 1 above.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-3, 7, 9-11, 15, 17-19, and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Gopalan et al. (US 20090031318) in view of Brenner et al. (US 20030110204) and in further view of Chatterjee et al. (US 20060059487).
The Brenner reference was cited by Applicant in the IDS filed 11/19/2018.
It is noted that any citations to specific, pages, columns, paragraphs, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
As to claim 1:
Gopalan teaches a computer-implemented method ([0016]: a computer process (method)…executing a computer process), comprising:
receiving by a processor core of a data processing system, a runnable thread selected from a set of threads in a group run queue for a process that is executing concurrently with a plurality of processes, wherein a priority associated with the group run queue has changed as a result of a change in a priority of the process, and the group run queue is part of a global run queue and wherein the global run queue includes a plurality of group run queues each corresponding to one of a plurality of process priorities ([0024] FIG. 3 illustrates an example multi-core compatible application submitting its threads to the GRQ and per-processor queues (PPQs) of a multi-core system; [0033]: While the medium and low priority threads are placed in the GRQ, the place holder may change its position tip or down depending on a priority of other pending threads. For example, another high priority thread may arrive while the high priority thread of the multi-thread application is being processed. Thus, the medium priority thread of the multi-thread application may be shifted below the newly arriving high priority thread. Of course, an upward shift may also happen if the priorities are reversed; [0041] Schedulers for the processors of each device or the system may place the threads on the GRQ(s) and per-processor queues based on their affinity status as described above. Results of processed threads are then provided by the respective cores to the submitting operating system or application; [0052]: Process 700 begins with operation 702, where a thread is received from an application or the operating system; [0054]: At decision operation 710, a determination is made whether the thread is from a multi-thread legacy application. If the thread is from a multi-thread legacy application, a stub is placed in the processing queue at next operation 712, the thread with highest priority from the legacy application placed in place of the stub at following operation 714, and the stub position adjusted at subsequent optional operation 716 based on a priority of the legacy application thread and any pending threads in the queue); and
executing the runnable thread with the processor core of the data processing system (Fig.7: 722, execute operation on thread; [0056]: At operation 722 following operation 720, the thread is processed by the multi-core processor providing the results to the requesting application and/or operating system).
Gopalan, however, does not explicitly teach the following additional limitations:
Brenner teaches relocating, based on resource usage, the group run queue from a first global run entry of the global run queue having a first process priority to a second global run entry of the global run queue having a second process priority ([0033]: The global run queue of a node competes with the corresponding local run queues for CPUs to service its threads. Threads that are present in the global run queue and threads in the local run queues seek processing time from the CPUs and thus, compete on a priority basis for the CPUs' resources; [0083]: Starvation Load Balancing is directed to moving unbound threads which have not been dispatched within a predetermined period of time to a global run queue. In this way, undispatched threads from local run queues may be moved to the global run queue where there is a greater likelihood that they will be assigned to a local run queue for a CPU that may be able to dispatch them; [0086]: In addition, by moving threads that are not being dispatched to the global run queue, there is a greater likelihood that load balancing will achieve the desired effect. For example, if a local run queue has a large number of undispatched threads, load balancing will tend to cause dispatching threads to be placed in other local run queues).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Gopalan with Brenner because it would have provided the enhanced capability for performing initial load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced.
The combination of Gopalan and Brenner does not explicitly teach the threads are runnable threads.
Chatterjee teaches runnable threads (Abstract, [0026], and [0040-0041]: runnable threads).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to combine Chatterjee with Gopalan as modified Brenner because it would have provided the enhanced capability for scheduling computing threads for processing in a multithreaded computing system.
As to claim 2:
Gopalan teaches the global run queue is associated with a list of a plurality of group run queues, each of the group run queues is associated with one of the plurality of processes ([0032-0033], [0036], and Fig. 2-4).
As to claim 3:
Gopalan teaches each of the group run queues includes a list of a plurality of threads associated with a corresponding process, each of the threads being associated with one of a plurality of thread priorities associated with the corresponding process ([0034-0036], and [0054]).
As to claim 4:
Gopalan teaches monitoring processing resource usages amongst a set of processes being executed by the processor cores of the data processing system; and modifying the priority of group run queues based on processing resource usages of a corresponding set of processes, such that one of the set of processes does not utilize too many process resources that will starve another process (Abstract and [0052-0056]).
As to claim 7:
Gopalan teaches the processor cores is configured to execute one or more threads of a particular process within a predetermined time slot ([0021]).
As to claim 24:
Gopalan teaches the priority of the group run queue changed based on at least a resource usage of the process ([0052-0056]).
As to claims 9-11, 15, and 25:
Note the rejection of claims 1-3, 7, and 24, respectively. Claims 9-11, 15, and 25 are the same as claims 1-3, 7, and 24, except claims 9-11, 15, and 25 are computer-readable medium claims and claims 1-3, 7, and 24 are method claims.
As to claims 17-19 and 26:
Note the rejection of claims 1-3 and 24 above, respectively. Claims 17-19 and 26 are the same as claims 1-3 and 24, except claims 17-19 and 26 are system claims and claims 1-3 and 24 are method claims.
Allowable Subject Matter
5. Claims 4, 6, 12, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, subject to the nonstatutory obviousness-type double patenting rejection above.
Response to Arguments
6. Applicants' arguments filed 10/07/2025 have been considered but are moot in
view of the new ground(s) of rejection.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VAN H. NGUYEN whose telephone number is (571) 272-3765. The examiner can normally be reached on Monday- Friday from 9:00AM to 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEWIS BULLOCK, can be reached at telephone number (571) 272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VAN H NGUYEN/
Primary Examiner, Art Unit 2199