DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
The claim objections to claims 1, 8, and 17 are withdrawn in light of the amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims, the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Pierson (US 20230158491) (previously cited) in view of Zurich Instruments (“Principles of lock-in detection and the state of the art”) (newly cited) as evidenced by Smith (“In-Phase & Quadrature Sinusoidal Components”) (newly cited) and as evidenced by Shumway (“Time Series Analysis and Its Applications: With R Examples”) (newly cited).
Regarding claim 1, Pierson discloses:
a sensing device (claim 1) comprising:
a fluid chamber (claim 1 “fluid path” and “test well”) comprising a micro-well array (claim 1 “test well”; and paragraphs [0446] “six wells” and [0447] “filling each well with 25 µl”);
a well of the micro-well array (claim 1 “test well”) associated with a first electrode (claim 1 “excitation electrode”) and a second electrode (claim 1 “sensing electrode”), the electrodes positioned to provide an AC excitation signal (paragraphs [0317]-[0318]) through the well (claim 1);
a synchronous detector electrically coupled to the first electrode and the second electrode (paragraph [0259]); and
the synchronous detector adapted to transform a circuit response to the AC excitation signal into representations of a real component and an imaginary component of an impedance signal received from the first electrode and the second electrode (paragraph [0259]), wherein the synchronous detector (paragraph [0259] and [0303]) multiplies a measured signal (paragraph [0259] and [0333] “multipliers” with “an in-phase square wave”) with an in-phase component of a source frequency of the AC excitation signal (paragraphs [0259], [0333], and [0354] deriving “in-phase and quadrature components of the induced signal” from “an in-phase square wave”) and averages the results (paragraph [0333], “low-pass filter”) to obtain the real and imaginary components (paragraphs [0013] and [0332]-[0334], the real and imaginary components, see especially paragraph [0332] “j” the imaginary unit and paragraph [0334] “{Re}” the real component of impedance; as well as paragraph [0259] “The complex impedance signal 530 can be interpreted as a quadrature-modulated waveform (e.g., a combination of an in-phase waveform resulting from the resistance of the test fluid and an out-of-phase waveform resulting from the reactance of the test fluid)”; also, paragraph [0335] “impedance is computed explicitly, and the output of the synchronous detector is predicted”; also, paragraph [0353], “an impedance spectrum” and “sweep”) of the impedance (paragraphs [0013] and [0259]) at each measurement frequency (paragraphs [0077], [0264], [0297], [0316], and [0354]) and well (paragraphs [0005] and [0288]-[0289]).
The following evidence and explanation is related to Pierson:
Evidentiary reference Smith discloses that a quadrature component is an orthogonal component to the in-phase component meaning it is 90° out-of-phase:
Smith discloses: that every measured sinusoidal signal (such as that of the AC excitation signal) with two orthogonal phases can be expressed as the sum of a sine function (phase zero) and cosine function (phase π/2). If the sine part is called the “in-phase” component, the cosine part can be called the “phase-quadrature” component. In general, “phase-quadrature” means “90° out of phase”, i.e., a relative phase shift of ±π/2. Every sum of an in-phase and quadrature component can be expressed as a single sinusoid at some amplitude and phase (Smith, pg. 1, see Trigonometric Identity for a mathematical proof and Fig. 4.2 for visualization).
Additionally, evidentiary reference Shumway discloses how averaging occurs with a low-pass filter.
Shumway discloses:
The centered moving average smoothes the series because it retains the lower frequencies and tends to attenuate the higher frequencies. In general, differencing is an example of a high-pass filter because it retains or passes the higher frequencies, whereas the moving average is a low-pass filter because it passes the lower or slower frequencies.
(Shumway, pgs. 213-214 and Fig. 4.16)
Thus, Shumway discloses that a low pass filter is a component that takes the moving average of a signal.
Therefore, Pierson discloses wherein the synchronous detector multiplies a measured signal with an in-phase component of a source frequency of the AC excitation signal (paragraphs [0259], [0333], and [0354] deriving “in-phase and quadrature components of the induced signal” from “an in-phase square wave”) and averages the results (paragraph [0333], “low-pass filter”).
Furthermore, Pierson also mentions multiplication by “j”, the imaginary unit, describing that the current through the parasitic path is 90° out-of-phase with the excitation voltage; therefore, Pierson discloses two orthogonal phases (0° and 90° phase difference from each other) of a source frequency (Pierson, paragraph [0332]-[0333]).
Pierson does not disclose wherein the synchronous detector multiplies a measured signal with two orthogonal phases of a source frequency.
Zurich Instruments discloses wherein the synchronous detector (pg. 2, a lock-in amplifier; see Fig. 2A-2B), multiplies a measured signal with two orthogonal phases of a source frequency (pg. 2 under “Dual-phase demodulation”; and, Fig. 2B, caption “the input signal is multiplied by the reference signal and a 90° phase-shifted version of the reference signal”).
In the analogous art of lock-in amplifiers, it would have been obvious to one skilled in the art before the effective filing date to modify the synchronous detector of Pierson to multiply the detected signal with two orthogonal signals based upon a source signal in order to detect the in-phase and quadrature components of the detected signal of Zurich Instruments, to convert into the amplitude and phase of the detected signal (Zurich Instruments, pg. 2, under “Dual-phase demodulation”).
Regarding claim 2, Pierson discloses further comprising a driver circuit to provide the AC excitation signal to the micro-well array (paragraphs [0189], [0275], and [0367]-[0369]).
Regarding claim 3, Pierson discloses wherein the driver circuit comprises an input stage comprising a current generator (paragraphs [0222] or [0252] “current source”) generating the AC excitation signal as an alternating current (paragraphs [0189] and [0369] “power supply or voltage source … are configured to apply an AC signal”) to the first electrode (claim 1 “excitation electrode”).
Regarding claim 4, Pierson discloses wherein the driver circuit (paragraphs [0189], [0256], [0275], and [0367]-[0369]) comprises an output stage coupled to the first electrode (paragraph [0368]), the output stage providing an output representing a sensed voltage generated by the AC excitation signal (paragraphs [0368]-[0369]).
Regarding claim 10, Pierson discloses where the excitation comprises a combination of multiple AC excitation signal frequencies (paragraphs [0297] and [0316] “sweeping voltages and frequencies”), and the synchronous detector adapted to detect each of the multiple frequencies (paragraph [0316] and [0353] “enabling high-sensitivity biomolecule quantification through conductivity measurements”).
Regarding claim 11, Pierson discloses where the circuit response is generated by biological changes (paragraphs [0005] “amplification” and for biological samples [0106]-[0107], [0110], [0114]-[0117], [0120], [0123], and [0126]-[0134]) in the contents of the well (paragraph [0005]).
Regarding claim 12, Pierson discloses where the sensed biological change comprises changes in extension of single-stranded DNA to double-stranded DNA (paragraph [0420] “for amplification” of many different viral nucleic acids, including “DNA viruses, such as … single-stranded viruses” and paragraph [0004]-[0005] “amplification” and “PCR” in general, which entails extension of single-strands of nucleic acids’ complementary strands to replicate the nucleic acid strand).
Regarding claim 13, Pierson discloses wherein the synchronous detector (paragraph [0259] “extract … from the raw signal … and compute their amplitude and phase”) is adapted to transform the circuit response to the AC excitation signal (paragraphs [0317]-[0318] and [0259]) into an absolute value of the impedance signal (paragraph [0260]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson (US 20230158491) (previously cited) in view of Zurich Instruments (“Principles of lock-in detection and the state of the art”) (newly cited) as evidenced by Smith (“In-Phase & Quadrature Sinusoidal Components”) (newly cited) and as evidenced by Shumway (“Time Series Analysis and Its Applications: With R Examples”) (newly cited) as applied to claim 4, further in view of Merriman (US 20190094175) (previously cited).
Regarding claim 5, Pierson discloses further comprising: a low pass filter (paragraph [0259]) configured between (paragraph [0259] “multipliers and low pass filters … to extract the in-phase and out-of-phase components from the raw signal … and compute their amplitude and phase”) the output stage (paragraph [0368]) and the synchronous detector (paragraph [0259]), and a frequency of the AC excitation signal (paragraphs [0316]-[0317]).
Pierson does not disclose a bandpass filter having a center frequency equal to a frequency of the AC excitation signal.
Merriman discloses a bandpass filter (paragraphs [0122], [0153], and [0181] “bandpass filter”).
In the analogous art of biomolecular sensors, it would have been obvious to one skilled in the art before the effective filing date to modify the circuit of Pierson with the bandpass filter of Merriman in order to eliminate extraneous electronic noise from the circuit response (Merriman, paragraphs [0121]-[0122] and [0181]).
Regarding the phrase “a bandpass filter having a center frequency equal to a frequency of the AC excitation signal”, it would have been obvious to one skilled in the art before the effective filing date to modify the range of the bandpass filter to fit the range of AC excitation signals in order to block electronic noise in the signal. Additionally, the limitation is obvious as a matter of routine optimization, because the range of the bandpass filter is a result-effective variable. The motivation for optimizing this result-effective variable is to allow the circuit response signal to be sensed, while blocking electronic noise (Merriman, paragraphs [0121]-[0122] and [0181]). MPEP § 2144.05(II).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Pierson (US 20230158491) (previously cited) in view of Zurich Instruments (“Principles of lock-in detection and the state of the art”) (newly cited) as evidenced by Smith (“In-Phase & Quadrature Sinusoidal Components”) (newly cited) and as evidenced by Shumway (“Time Series Analysis and Its Applications: With R Examples”) (newly cited) as applied to claim 1, further in view of Shachar (US 20160238553) (previously cited) and evidentiary reference Fiore (“10.2 Integrators”) (previously cited).
Regarding claim 8, Pierson discloses an output of the synchronous detector (paragraph [0259] “extract … from the raw signal … and compute their amplitude and phase”).
Arguably, Pierson discloses further comprising a smoother connected to an output of the synchronous detector (paragraph [0259] “low pass filter” where a smoother / integrator can be a type of low pass filter).
Nevertheless, Shachar discloses a smoother (paragraph [0183], Figs. 30C and 31, element 916 “definite integration” and paragraph [0185] “smoothing”) connected to an output of a detector (Fig. 31, paragraph [0180], “interconnection between the sensor signal array output … into a universal analog multiplexer … forming the AU 300”).
In the analogous art of a carbon nanotube BioFET array, it would have been obvious to one skilled in the art before the effective filing date to modify the integrated circuits of Pierson with the smoother of Shachar in order to smooth signal variations from the electrical signal. For more information on how integrators do this function, see evidentiary reference Fiore (Fiore, pg. 2, under “10.2.1: Accuracy and Usefulness of Integration”).
Regarding claim 9, Pierson discloses the real component of the impedance output by the synchronous detector and the imaginary component of the impedance output by the synchronous detector (paragraph [0259] “raw sensed signal … can be parsed into its resistance and reactants components”).
Arguably, Pierson discloses wherein the smoother comprises: first smoothing logic configured to receive the real component of the impedance output by the synchronous detector; and second smoothing logic configured to receive the imaginary component of the impedance output by the synchronous detector (paragraph [0259]-[0260], multiple smoothing logic / integrators can be a type of “low pass filter”, which may be used with “a synchronous detector” in the parsing of the impedance signal into real and imaginary components).
Nevertheless, Shachar discloses wherein the smoother comprises: first smoothing logic (paragraph [0183], Figs. 30C and 31, element 916 “definite integration” and paragraph [0185] “smoothing”) configured to receive the real component of the impedance signal output (paragraph [0159] “The DFT algorithm returns a real (R) and imaginary (I) data-word at each output frequency … the magnitude of the impedance and relative phase of the impedance at each frequency point along the sweep is easily calculated by the arithmetical unit (AU)”); and receiving the imaginary component of the impedance output (paragraph [0159]).
In the analogous art of a carbon nanotube BioFET array, it would have been obvious to one skilled in the art before the effective filing date to modify the integrated circuits of modified Pierson with the smoother of Shachar in order to smooth signal variations from the electrical signal (Fiore, pg. 2). For more information on how integrators do this function, see evidentiary reference Fiore (Fiore, pg. 2, under “10.2.1: Accuracy and Usefulness of Integration”).
Additionally, regarding the phrase “second smoothing logic”, mere duplication of parts has no patentable significance unless a new and unexpected result is produced. MPEP § 2144.04(VI)(B). Also, it would have been obvious to one skilled in the art before the effective filing date to modify modified Pierson with a second smoothing logic if needed in order to smooth signal variations from the electrical signal. For more information on how integrators do this function, see evidentiary reference Fiore (Fiore, pg. 2, under “10.2.1: Accuracy and Usefulness of Integration”). Lastly, it would have been expected that both the real and imaginary components of impedance calculated by the arithmetical unit (AU) of Shachar would be capable of being used with an integrator, already in the AU of Shachar (as described above in the rejection to claim 8).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson (US 20230158491) (previously cited) in view of Zurich Instruments (“Principles of lock-in detection and the state of the art”) (newly cited) as evidenced by Smith (“In-Phase & Quadrature Sinusoidal Components”) (newly cited) and as evidenced by Shumway (“Time Series Analysis and Its Applications: With R Examples”) (newly cited) as applied to claim 13 above, further in view of Baru (US 2004/0164783) (previously cited).
Regarding claim 14, Pierson discloses wherein the absolute value of the impedance signal is determined using a full-wave rectifier (paragraph [0318]).
If it is deemed that Pierson does not disclose this limitation, Pierson at least discloses the absolute value of the impedance signal (paragraph [0260]).
Baru discloses a full-wave rectifier (paragraph [0004]).
In the analogous art of determination of pathogen levels via changes in electrical impedance, it would have been obvious to one skilled in the art before the effective filing date to modify the electrical signal of Pierson with the full-wave rectifier of Baru in order to obtain rectified bioelectric signals, for example for low voltage medical devices (paragraph [0001]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson (US 20230158491) (previously cited) in view of Zurich Instruments (“Principles of lock-in detection and the state of the art”) (newly cited) as evidenced by Smith (“In-Phase & Quadrature Sinusoidal Components”) (newly cited) and as evidenced by Shumway (“Time Series Analysis and Its Applications: With R Examples”) (newly cited), further in view of Baru (US 2004/0164783) (previously cited) as applied to claim 14 above and Shachar (US 20160238553) (previously cited) and evidentiary reference Fiore (“10.2 Integrators”) (previously cited).
Regarding claim 15, Pierson discloses further comprising a low pass filter coupled to an output of a rectified signal (paragraph [0318]).
Arguably, Pierson discloses further comprising a smoother (paragraph [0318] “low-pass filter” where a smoother / integrator can be a type of low-pass filter) coupled to an output of the full-wave rectifier (paragraph [0318]).
If it is deemed Pierson does not disclose a full-wave rectifier, Baru discloses a full-wave rectifier (paragraph [0004]).
In the analogous art of determination of pathogen levels via changes in electrical impedance, it would have been obvious to one skilled in the art before the effective filing date to modify the electrical signal of Pierson with the full-wave rectifier of Baru in order to obtain rectified bioelectric signals, for example for low voltage medical devices (paragraph [0001]).
If it is deemed Pierson does not disclose a smoother, Shachar discloses a smoother (paragraph [0183], Figs. 30C and 31, element 916 “definite integration” and paragraph [0185] “smoothing”) connected to an output of a detector (Fig. 31, paragraph [0180], “interconnection between the sensor signal array output … into a universal analog multiplexer … forming the AU 300”).
In the analogous art of a carbon nanotube BioFET array, it would have been obvious to one skilled in the art before the effective filing date to modify the integrated circuits of modified Pierson with the smoother of Shachar in order to smooth signal variations from the electrical signal. For more information on how integrators do this function, see evidentiary reference Fiore (Fiore, pg. 2, under “10.2.1: Accuracy and Usefulness of Integration”).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Pierson (US 20230158491) (previously cited) in view of Zurich Instruments (“Principles of lock-in detection and the state of the art”) (newly cited) as evidenced by Smith (“In-Phase & Quadrature Sinusoidal Components”) (newly cited) and as evidenced by Shumway (“Time Series Analysis and Its Applications: With R Examples”) (newly cited) as applied to claim 1, further in view of Shachar (US 20160238553) (previously cited).
Regarding claim 16, Pierson discloses the synchronous detector (paragraph [0259]).
Arguably, Pierson discloses wherein the synchronous detector includes an amplifier (paragraph [0259], “multipliers”)
Pierson does not disclose wherein the synchronous detector includes an inverter and switches.
Shachar discloses an amplifier (paragraph [0179] “non-inverting amplifier”), an inverter (paragraph [0179] “an inverting amplifier” has an inverter), and switches (paragraph [0186] “switches to start and modify the operations”).
In the analogous art of a carbon nanotube BioFET array, it would have been obvious to one skilled in the art before the effective filing date to modify the synchronous detector of Pierson with the components of Shachar in order to compute unit analog processes on the electrical signal before digitization (Shachar, Fig. 31A and paragraphs [0110] and [0186]).
Regarding claim 17, Pierson discloses the synchronous detector (paragraph [0259]).
Pierson does not disclose a clock to control the switches.
Shachar discloses a clock (Fig. 19 “clock” and paragraph [0159] “clock traffic”) that sends a signal to control functional blocks that can include switches (paragraph [0186]) of the general-purpose analog computational unit of an analog front end (paragraphs [0156]-[0159]).
In the analogous art of carbon nanotube BioFET array, it would have been obvious to one skilled in the art before the effective filing date to modify the switches of modified Pierson with the clock signal of Shachar in order to employ both digital and analog sections of the invention to work together so that expanded test frequency range and widened impedance measurement range can be achieved (Shachar, paragraph [0158]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson (US 20230158491) (previously cited) in view of Zurich Instruments (“Principles of lock-in detection and the state of the art”) (newly cited) as evidenced by Smith (“In-Phase & Quadrature Sinusoidal Components”) (newly cited) and as evidenced by Shumway (“Time Series Analysis and Its Applications: With R Examples”) (newly cited) further in view of Shachar (US 20160238553) (previously cited), as applied to claim 17, further in view of Baltz (US 7,791,028) (previously cited).
Regarding claim 19, Pierson discloses the AC excitation signal (paragraphs [0317]-[0318] and [0368]-[0369]).
Pierson does not disclose wherein the clock is synchronized with the AC excitation signal.
Baltz discloses that the clock is synchronized with the AC excitation signal (col. 6, lines 52-63).
In the analogous art of the measurement of electrical signals, it would have been obvious to one skilled in the art before the effective filing date to modify the sensing device of modified Pierson with the synchronous timing device of Baltz in order to measure signals, to digitally process the signals or data, the phase and amplitude based on measurements of the input and output of a system are determined (Baltz, abstract).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson (US 20230158491) (previously cited) in view of Zurich Instruments (“Principles of lock-in detection and the state of the art”) (newly cited) as evidenced by Smith (“In-Phase & Quadrature Sinusoidal Components”) (newly cited) and as evidenced by Shumway (“Time Series Analysis and Its Applications: With R Examples”) (newly cited) further in view of Shachar (US 20160238553) (previously cited), as applied to claim 17, further in view of Smolka (US 3,825,825) (previously cited) and evidentiary reference Fiore (“10.2 Integrators”) (previously cited).
Regarding claim 20, arguably, Pierson discloses a smoother (paragraph [0318] “low-pass filter” where a smoother / integrator can be a type of low-pass filter).
Pierson does not disclose wherein a first switch is to switch between connecting the amplifier to a first smoother and connecting the inverter to the first smoother to generate the real component of the impedance signal.
Modified Pierson teaches a switch (see rejection to claim 16), an amplifier (see rejection to claim 16), and an inverter (see rejection to claim 16).
Smolka discloses wherein a first switch (Fig. 4, element 82 “switch”, where the switch is controlled) is to switch between connecting the amplifier (Fig. 4, element 72 or 74 “logarithmic amplifier”) to a first output (Fig. 4, element 80 “Summer”) and connecting the inverter (Fig. 4, element 76 or 78 “inverting amplifier”) to the first output (Fig. 4, element 80 “Summer”) to generate the real component of the impedance signal (abstract, Fig. 4, the block diagram of the real part detector shown in Fig. 1, element 22 “real part detector”).
In the analogous art of measuring the real part of the complex impedance, it would have been obvious to one skilled in the art before the effective filing date to modify the switch of modified Pierson to be controlled to switch between an amplifier and an inverter in order to obtain the real component of the impedance. In context of Smolka, this would aid in impedance matching between a transmitter and an antenna (Smolka, col. 3, lines 10-20); in context of modified Pierson, it would yield the real impedance signal of the analyte in the microwell.
Notably, Smolka also discloses a similar process for computing both the real and imaginary component of impedance (Fig. 7).
Shachar discloses a first smoother (paragraph [0183], Figs. 30C and 31, element 916 “definite integration” and paragraph [0185] “smoothing”) connected to an output of a detector (Fig. 31, paragraph [0180], “interconnection between the sensor signal array output … into a universal analog multiplexer … forming the AU 300”).
In the analogous art of a carbon nanotube BioFET array, it would have been obvious to one skilled in the art before the effective filing date to modify the integrated circuits of modified Pierson with the smoother of Shachar in order to smooth signal variations from the electrical signal. For more information on how integrators do this function, see evidentiary reference Fiore (Fiore, pg. 2, under “10.2.1: Accuracy and Usefulness of Integration”).
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Pierson (US 20230158491) (previously cited) in view of Zurich Instruments (“Principles of lock-in detection and the state of the art”) (newly cited) as evidenced by Smith (“In-Phase & Quadrature Sinusoidal Components”) (newly cited) and as evidenced by Shumway (“Time Series Analysis and Its Applications: With R Examples”) (newly cited), as applied to claim 2, further in view of Palumbo (“Analysis of power supply noise attenuation in a PTAT current source”) (previously cited) and Bishop (“Understand Amplifiers”) (previously cited).
Regarding claim 21, Pierson discloses the driver circuit (paragraphs [0189], [0275], and [0367]-[0369]) and a power supply (paragraphs [0367]-[0369]).
Pierson does not disclose wherein the driver circuit comprises first, second, and third transistors, each coupled to a power supply.
Palumbo discloses the first and second transistors (Fig. 2, Q1 and Q2), each coupled to a power supply (Fig. 2. iin and iout).
In the analogous art of circuit design, it would have been obvious to one skilled in the art before the effective filing date to modify the circuit of Pierson with the Widlar current mirror depicted by Palumbo in order to use Q2’s drain to carry the load.
Bishop discloses the third transistor (Fig. 3.1, Q1), coupled to a power supply (Vdd).
In the analogous art of circuit design, it would have been obvious to one skilled in the art before the effective filing date to modify the circuit of modified Pierson with the transistor of Bishop, such that the input to the gate of Bishop is taken from Q2’s drain of Palumbo, incorporated into modified Pierson, and such that the input to the gate of Bishop is connected the first electrode of modified Pierson in order to amplify the output of the electrodes (and thereby the signal that is related to the load of the electrode) of modified Pierson.
Regarding claim 22, Pierson does not disclose wherein the first transistor includes a drain coupled to ground.
Palumbo discloses the first transistor (Fig. 2, Q1), includes a drain coupled to ground (Fig. 2.).
In the analogous art of circuit design, it would have been obvious to one skilled in the art before the effective filing date to modify the circuit of modified Pierson with the Widlar current mirror depicted by Palumbo in order to use Q2’s drain to carry the load.
Regarding claim 23, Pierson discloses the first electrode (claim 1 “excitation electrode”).
Pierson does not disclose wherein the second transistor includes a drain coupled to the first electrode and a gate of the third transistor.
Palumbo discloses the second transistor including a drain coupled to a load (Fig. 2, Q2).
In the analogous art of circuit design, it would have been obvious to one skilled in the art before the effective filing date to modify the circuit of modified Pierson with the Widlar current mirror depicted by Palumbo in order to use Q2’s drain to carry the load.
Bishop discloses a gate of the third transistor (Fig. 3.1, Q1).
In the analogous art of circuit design, it would have been obvious to one skilled in the art before the effective filing date to modify the circuit of modified Pierson with the transistor of Bishop, such that the input to the gate of Bishop is taken from Q2’s drain of Palumbo, incorporated into modified Pierson, and such that the input to the gate of Bishop is connected the first electrode of modified Pierson in order to amplify the output of the electrodes (and thereby the signal that is related to the load of the electrode) of modified Pierson.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Pierson (US 20230158491) (previously cited) in view of Zurich Instruments (“Principles of lock-in detection and the state of the art”) (newly cited) as evidenced by Smith (“In-Phase & Quadrature Sinusoidal Components”) (newly cited) and as evidenced by Shumway (“Time Series Analysis and Its Applications: With R Examples”) (newly cited) in view of Palumbo (“Analysis of power supply noise attenuation in a PTAT current source”) (previously cited) and Bishop (“Understand Amplifiers”) (previously cited), as applied to claim 21, further in view of Choi (US 2006/0138560) (previously cited).
Regarding claim 24, Pierson does not disclose wherein the first transistor is a p-channel MOSFET, the second transistor is a p-channel MOSFET, and the third transistor is an n-channel MOSFET.
Choi discloses:
wherein the first transistor is a p-channel MOSFET, the second transistor is a p-channel MOSFET (Fig. 1, elements M3 and M4 and paragraphs [0008]-[0009]).
In the analogous art of current mirror circuits, it would have been obvious to one skilled in the art before the effective filing date to modify two MOSFETS in a current mirror to be P-channel MOSFETS in order to create a conventional constant voltage generation circuit using conventional MOS transistors (Choi, paragraph [0005]).
Bishop discloses
the third transistor is an n-channel MOSFET (“n-channel enhancement type MOSFET, the source follower”)
In the analogous art of circuit design, it would have been obvious to one skilled in the art before the effective filing date to modify the third transistor of modified Pierson with the n-channel MOSFET of Bishop in order to amplify the output of the electrodes using a MOSFET source follower amplifier (and thereby the signal that is related to the load of the electrode) of modified Pierson.
Additional Prior Art References
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
Chodavarapu (US 20110115499) (previously cited) – This invention, cited in a previous Office Action, is a high-throughput integrated impedance spectrometer for biological applications; also, newly found Rairligh, cited below, was described in Chodavarapu’s prior art, cited in their specification.
Lee (US 20110024309) (newly cited) – This invention is a biochip for detecting biomolecules.
Pierson (US 20190232282) (newly cited) – This invention is related to Pierson, cited above.
Othman (US 6970738) (newly cited) – This invention is a complex impedance spectrometer using parallel demodulation and digital conversion, for use with the complex impedance spectrum of a tissue.
Aytur (US 20040033627) (newly cited) – This invention is a method and apparatus for detecting substances of interest, focusing on different biological molecules (see paragraphs [0122] and [0126]).
Stanford Research Systems (“About Lock-In Amplifiers”) (newly cited) – This non-patent literature describes lock-in amplifiers and phase sensitive detection.
Rairigh (“Analysis of On-Chip Impedance Spectroscopy Methodologies for Sensor Arrays”) (newly cited) – This non-patent literature describes on-chip impedance spectroscopy for sensor arrays.
Response to Arguments
Applicant’s arguments filed 07/08/2025 have been fully considered but they are not persuasive.
Regarding Applicant arguments and the amendments to the claims, a new secondary reference Zurich Instruments has been applied, and is included in the corresponding rejections as described above. Two evidentiary references are applied as well: Smith and Shumway. Additional Prior Art references have also been added to the record.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/N.G.E./Examiner, Art Unit 1799
/MICHAEL A MARCHESCHI/Supervisory Patent Examiner, Art Unit 1799