DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prosecution Reopened
In view of the Appeal Brief filed on 09/08/25, PROSECUTION IS HEREBY REOPENED. New grounds of rejections are set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/EVA Y MONTALVO/ Supervisory Patent Examiner, Art Unit 2818
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-16, 21-36 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Independent claims 1, 9, 21, and 29 filed on 11/06/24 recites limitation “the reduced thickness portion including top and bottom planar surfaces”, which is not supported by the original disclosure. Notably, the original disclosure failed to support the top and bottom surfaces being specifically planar (i.e., perfectly flat, 2D surface with no curvature and no thickness, extending in two directions, or flat or being leveled). The drawings do not remedy the deficiency.
Claims 2-8, 10-16, 22-28, 30-36 are rejected being dependent under rejected claims 1, 9, 21, and 29.
Claims 4,14, 24, and 34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite limitation “wherein the full thickness portion is between the reduced thickness portion and the leads or lead terminals”, which is indefinite. Is it not clear how the full thickness portion can be positioned between a reduced thickness portion of the pad and two leads/lead terminals as the leads/lead terminals are position on both side of the leadframe/package. For the sake of the compact prosecution, the limitation is interpreted as “wherein the full thickness portion is between the reduced thickness portion and one of the leads or lead terminals” in the instant Office Action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (figs. 1A and 1C) in view of Okumura et al. (U.S. 2017/0250124; hereinafter Okumura).
Regarding to claim 1, Applicant Admitted Prior Art (AAPA, figs. 1A and 1C) discloses a leadframe for a multichip semiconductor package, comprising:
a first die pad 182 (figs. 1A and 1C) and a second die pad 192 (figs. 1A and 1C) both vertically offset relative to leads or lead terminals 114 and 124 that are positioned on at least 2 sides beyond the first die pad 182 and the second die pad 192 (figs. 1A and 1C) (e.g. the structure of AAPA (figs. 1A and 1C) is similar to the structure of the present invention (figs. 1B and 1D).
AAPA does not disclose at least one of the first die pad and second die pad has a reduced thickness portion and a full thickness portion, the reduced thickness portion including top and bottom planar surfaces.
Okumura in the same field of art teaches a leadframe with die pad (131, Fig. 1B) vertically offsetting from the two leads (54) positioned on at least two sides beyond the die pad. The die pad has a reduced thickness portion (edge portion of 131) and a full thickness portion (central portion of 131), the reduced thickness portion including top and bottom planar surfaces (i.e., edge portion of 131 has a top and a bottom surface that appears to be planar).
AAPA and Okumura are in the same field of endeavor and teach similar devices, where both die pads serve the same function of supporting the chips/dies in the respective devices. A person having ordinary skill in the art at the time of invention would have readily recognized the equivalent substitution of the same element, by substituting both AAPR’s die pads 182 and 192 with two of Okumura’s die pad 131, and would obtain predictable results. Thus, the claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR).
Regarding to claim 21, Applicant Admitted Prior Art (AAPA, figs. 1A and 1C) discloses a method for making a multichip semiconductor package, comprising:
providing a first die pad 182 (figs. 1A and 1C) and a second die pad 192 (figs. 1A and 1C) both vertically offset relative to leads or lead terminals 114 and 124 that are positioned on at least 2 sides beyond the first die pad 182 and the second die pad 192 (figs. 1A and 1C) (e.g. the structure of AAPA (figs. 1A and 1C) is similar to the structure of the present invention (figs. 1B and 1D).
AAPA does not disclose at least one of the first die pad and second die pad has a reduced thickness portion and a full thickness portion, the reduced thickness portion including top and bottom planar surfaces.
Okumura in the same field of art teaches a method of making a semiconductor package with die pad (131, Fig. 1B) vertically offsetting from the two leads (54) positioned on at least two sides beyond the die pad. The die pad has a reduced thickness portion (edge portion of 131) and a full thickness portion (central portion of 131), the reduced thickness portion including top and bottom planar surfaces (i.e., edge portion of 131 has a top and a bottom surface that appears to be planar).
AAPA and Okumura are in the same field of endeavor and teach similar methods of making semiconductor packages, where both die pads serve the same function of supporting the chips/dies in the respective devices. A person having ordinary skill in the art at the time of invention would have readily recognized the equivalent substitution of the same element, by substituting both AAPR’s die pads 182 and 192 with two of Okumura’s die pad 131, and would obtain predictable results. Thus, the claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR).
Regarding claims 2 and 3, AAPA in view of Okumura teaches a leadframe/method of forming a semiconductor package wherein the reduced thickness portion (Okumura’s edge portion of 131) has a thickness that is 20% to 80 % of the full thickness portion (Okumura’s center portion of 131). Examiner notes that Okumura’s Fig. 9A shows the edge portion of 131 to be just a little less than 50% of the center portion so it is considered to be well within the claimed 20% to 80% range.
Regarding claims 3 and 23, AAPA in view of Okumura teaches a leadframe/method of forming a semiconductor package wherein both the first and second die pads have the reduced thickness portion. (AAPA Fig. 1A and Okumura Fig. 9A)
Regarding claims 4 and 24, AAPA in view of Okumura teaches a leadframe/method of forming a semiconductor package wherein the full thickness portion is between the reduced thickness portion and one of the leads or lead terminals (Fig. 9A of Okumura shows that the center portion of the 131 with full thickness is between the right edge portion of 131 with reduced thickness and the left lead 54).
Regarding claims 5 and 25, AAPA in view of Okumura teaches a leadframe/method of forming a semiconductor package wherein the reduced thickness portion is on a bottom side of the first die pad and the second die pad (Okumura Fig. 9A).
Regarding claim 6, the claimed process step “thinning in a portion of an inside portion of the leads or the lead terminals” is considered “product-by-process”. It has not been given any patentable weight since a “product-by-process” claim is directed to a product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product-by-process” claim, and not the patentability of the process, and that old or obvious product produced by a new method is not patentable as a product, whether claimed in “product-by-process” claim or not.
Note that applicant has the burden of proof in such case, as the above case law makes clear.
Regarding claim 26, AAPA in view of Okumura teaches a method of forming a semiconductor package further comprising thinning in a portion of an inside portion (Okumura 141/14/54 [0053-0054]) of the leads or the lead terminals (Fig. 6 and Fig. 9A). Examiner notes that leads 141/14 within the encapsulant are thinned as showed in Fig. 6, and leads 141/14 can be external input terminals like leads 54.
Regarding claims 7 and 27, AAPA in view of Okumura teaches a leadframe/method of forming a semiconductor package wherein the vertically offset comprises a downset (see AAPA Fig.1A and Okumura Fig, 9A).
Regarding claims 8 and 28, AAPA in view of Okumura teaches a leadframe/method of forming a semiconductor package that wherein the vertically offset comprises a vertically up offset (see AAPA Fig.1C).
Claims 9-16, 29-30, and 32-36 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA in view of Okumura and further in view of Dong et al. (U.S. 2009/0213914; hereinafter Dong, cited in previous action).
Regarding claim 9, AAPA (figs. 1A and 1C) discloses a leadframe for a multichip isolation device package, comprising:
a first die pad (182 figs. 1A and 1C) and a second die pad (192 figs. 1A and 1C) both vertically offset relative to leads or lead terminals (114) and (124) that are positioned on at least 2 sides beyond the first die pad and the second die pad.
AAPA does not disclose at least one of the first die pad and second die pad has a reduced thickness portion and a full thickness portion, the reduced thickness portion including top and bottom planar surfaces.
Okumura in the same field of art teaches a leadframe with die pad (131, Fig. 1B) vertically offsetting from the two leads (54) positioned on at least two sides beyond the die pad. The die pad has a reduced thickness portion (edge portion of 131) and a full thickness portion (central portion of 131), the reduced thickness portion including top and bottom planar surfaces (i.e., edge portion of 131 has a top and a bottom surface that appears to be planar).
AAPA and Okumura are in the same field of endeavor and teach similar devices, where both die pads serve the same function of supporting the chips/dies in the respective devices. A person having ordinary skill in the art at the time of invention would have readily recognized the equivalent substitution of the same element, by substituting both AAPR’s die pads 182 and 192 with two of Okumura’s die pads 131, and would obtain predictable results. Thus, the claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR).
The combined device of AAPA and Okumura teaches a first integrated circuit (IC) die (11) on the first die pad (131) which has a first bond pad (i.e., where wire 18 connects from, Fig. 9A) connected to a first of the leads or the lead terminals (54), the first IC die including functional circuitry configured for realizing a transmitter or a receiver (i.e., semiconductor chip 11 would include a functional circuitry that can configured for transmitting or receiving base on programing); a second IC die (11) on the second die pad (131) which has a second bond pad (i.e., where wire 18 connects from, Fig. 9A) connected to a second of the leads or the lead terminals (54), the second IC die including functional circuitry configured for realizing another of the transmitter and the receiver (i.e., semiconductor chip 11 would include a functional circuitry that can configured for transmitting or receiving base on programing).
AAPA and Okumura does not provide teaching for an isolation component in a signal path of the isolation device positioned on or between the first and the second IC die.
Dong discloses a device comprising: an isolation component (e.g. a capacitive isolator 1602 that may be integrated into two separate multi-functional dies (1604, 1606, fig. 15, ¶0083) in the combined device of AAPA and Okumura. The teaching would have resulted in an isolation component 1602 in a signal path of the isolation device on at least one of the first and second IC die (11) for capacitive isolation.
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of AAPA and Okumura by having the isolation component in the signal path of the isolation device on at least one of the first and second IC die, as taught by Dong, in order to provide the isolation circuit for the device.
Regarding claim 29, AAPA (figs. 1A and 1C) discloses a method of making a multichip isolation device package, comprising:
providing a first die pad (182 figs. 1A and 1C) and a second die pad (192 figs. 1A and 1C) both vertically offset relative to leads or lead terminals (114) and (124) that are positioned on at least 2 sides beyond the first die pad and the second die pad.
AAPA does not disclose at least one of the first die pad and second die pad has a reduced thickness portion and a full thickness portion, the reduced thickness portion including top and bottom planar surfaces.
Okumura in the same field of art teaches a leadframe with die pad (131, Fig. 1B) vertically offsetting from the two leads (54) positioned on at least two sides beyond the die pad. The die pad has a reduced thickness portion (edge portion of 131) and a full thickness portion (central portion of 131), the reduced thickness portion including top and bottom planar surfaces (i.e., edge portion of 131 has a top and a bottom surface that appears to be planar).
AAPA and Okumura are in the same field of endeavor and teach similar devices, where both die pads serve the same function of supporting the chips/dies in the respective devices. A person having ordinary skill in the art at the time of invention would have readily recognized the equivalent substitution of the same element, by substituting both AAPR’s die pads 182 and 192 with two of Okumura’s die pads 131, and would obtain predictable results. Thus, the claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR).
The combined device of AAPA and Okumura teaches placing a first integrated circuit (IC) die (11) on the first die pad (131) which has a first bond pad (i.e., where wire 18 connects from, Fig. 9A) connected to a first of the leads or the lead terminals (54), the first IC die including functional circuitry configured for realizing a transmitter or a receiver (i.e., semiconductor chip 11 would include a functional circuitry that can configured for transmitting or receiving base on programing); placing a second IC die (11) on the second die pad (131) which has a second bond pad (i.e., where wire 18 connects from, Fig. 9A) connected to a second of the leads or the lead terminals (54), the second IC die including functional circuitry configured for realizing another of the transmitter and the receiver (i.e., semiconductor chip 11 would include a functional circuitry that can configured for transmitting or receiving base on programing).
AAPA and Okumura does not provide teaching for placing an isolation component in a signal path of the isolation device positioned on or between the first and the second IC die.
Dong discloses a method comprising: placing an isolation component (e.g. a capacitive isolator 1602 that may be integrated into two separate multi-functional dies (1604, 1606, fig. 15, ¶0083) in the combined method of AAPA and Okumura. The teaching would have resulted in an isolation component 1602 in a signal path of the isolation device on at least one of the first and second IC die (11) for capacitive isolation.
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the method of AAPA and Okumura by having the isolation component in the signal path of the isolation device on at least one of the first and second IC die, as taught by Dong, in order to provide the isolation circuit for the device.
Regarding claims 10 and 30, AAPA, Okumura, and Dong teach a device/method wherein the isolation component comprises the capacitive isolator 1602 (Dong, fig. 15 and [0083]).
Regarding claim 11, AAPA, Okumura, and Dong teach a device/method wherein the isolation component comprises two capacitive isolators 1602 (Dong, fig. 15 and [0083]).
Regarding claims 12 and 32, AAPA, Okumura, and Dong teach a device/method wherein the reduced thickness portion (Okumura’s edge portion of 131) has a thickness that is 20% to 80 % of the full thickness portion (Okumura’s center portion of 131). Examiner notes that Okumura’s Fig. 9A shows the edge portion of 131 to be just a little less than 50% of the center portion so it is considered to be well within the claimed 20% to 80% range.
Regarding claims 13 and 33, AAPA, Okumura, and Dong teach a device/method wherein both the first and second die pads have the reduced thickness portion. (AAPA Fig. 1A and Okumura Fig. 9A).
Regarding claims 14 and 34, AAPA, Okumura, and Dong teach a device/method wherein the full thickness portion is between the reduced thickness portion and one of the leads or lead terminals (Fig. 9A of Okumura shows that the center portion of the 131 with full thickness is between the right edge portion of 131 with reduced thickness and the left lead 54).
Regarding claim 15, the claimed process step “thinning in a portion of an inside portion of the leads or the lead terminals” is considered “product-by-process”. It has not been given any patentable weight since a “product-by-process” claim is directed to a product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product-by-process” claim, and not the patentability of the process, and that old or obvious product produced by a new method is not patentable as a product, whether claimed in “product-by-process” claim or not.
Note that applicant has the burden of proof in such case, as the above case law makes clear.
Regarding claim 35, AAPA, Okumura, and Dong teaches a method of forming a semiconductor package further comprising thinning in a portion of an inside portion (Okumura 141/14/54 [0053-0054]) of the leads or the lead terminals (Fig. 6 and Fig. 9A). Examiner notes that leads 141/14 within the encapsulant are thinned as showed in Fig. 6, and leads 141/14 can be external input terminals like leads 54.
Regarding claims 16 and 36, AAPA, Okumura, and Dong teach a device/method wherein the vertically offset comprises a downset (AAPA fig. 1A, Okumura Fig. 9A).
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over AAPA, Okumura, and Dong and further in view of Coyne (U.S. 2017/0133841, cited in previous action).
As discussed in details above, Applicant Admitted Prior Art (figs. 1A and 1C), Okumura, in view of Dong substantially disclose all the limitations in claim 29 above. However, they do not providing teaching for the isolation component comprises the transformer isolation.
However, Coyne discloses a method comprising: wherein the isolation component comprises the transformer isolation (figs. 6-7, ¶0042, line 38+ and ¶0043).
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the method of AAPA, Okumura, and Dong by having the isolation component comprising the transformer isolation, as taught by Coyne, in order to provide a suitable isolation component and improve the electrical isolation property of the module.
Claims 1-8 and 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (figs. 1A and 1C) in view of Yu et al. (U.S. 2013/0241041; hereinafter Yu).
Regarding claims 1 and 21, Applicant Admitted Prior Art (figs. 1A and 1C) discloses a leadframe for a multichip semiconductor package, comprising:
a first die pad 182 (figs. 1A and 1C) and a second die pad 192 (figs. 1A and 1C) both vertically offset relative to leads or lead terminals 114 and 124 that are positioned on at least 2 sides beyond the first die pad 182 and the second die pad 192 (figs. 1A and 1C) (e.g. the structure of AAPA (figs. 1A and 1C) is similar to the structure of the present invention (figs. 1B and 1D); thus, the first die pad 182 and the second die pad 192 (figs. 1A and 1C) both vertically offset relative to leads or lead terminals 114 and 124 (figs. 1A and 1C).
Applicant Admitted Prior Art (figs. 1A and 1C) do not disclose at least one of the first die pad and second die pad has a reduced thickness portion.
However, Yu et al. discloses a device comprising: at least one of the first die pad (see labeled fig. 1K) and second die pad (see labeled fig. 1K) has a reduced thickness portion (see labeled fig. 1K) and a full thickness portion (see labeled fig. 1K), the reduced thickness portion including top and bottom planar surfaces (labeled fig. 1K; e.g. the reduced thickness portion including a portion of top planar surface).
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Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of AAPA (figs. 1A and 1C) by having the first and second die pads has a reduced thickness portion, the reduced thickness portion including top and bottom planar surfaces, as taught by Yu, in order to enhance the structural strength for the semiconductor package.
Regarding claims 2 and 22, Yu discloses that wherein the reduced thickness portion (fig. 1K) has a thickness that is 20% to 80 % of the full thickness portion (fig. 1K).
Regarding claims 3 and 23, Yu discloses that wherein both the first and second die pads (see labeled fig. 1K) have the reduced thickness portion (fig. 1K).
Regarding claims 4 and 24, Yu discloses that wherein the full thickness portion (see labeled fig. 1K) is between the reduced thickness portion and the leads or lead terminals (see labeled fig. 1K).
Regarding claims 5 and 25, Yu discloses the reduced thickness portion is on one side (e.g. a top side) of the first die pad (see labeled fig. 1K) and second die pad (see labeled fig. 1K). It would have been obvious to one of ordinary skill in the art at the time of the invention to form the reduced thickness portion is on a bottom side of the first die pad and the second die pad.
Regarding claims 6 and 26, Yu discloses that the device further comprising thinning in a portion of an inside portion (see labeled fig. 1K) of the leads or the lead terminals (fig. 1K).
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Regarding claims 7 and 27, AAPA (fig. 1A) discloses that wherein the vertically offset comprises a downset.
Regarding claims 8 and 28, AAPA (fig. 1C) discloses that wherein the vertically offset comprises a vertically up offset.
Claims 9-16, 29-30 and 32-36 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (figs. 1A and 1C) in view of Yu et al. (U.S. 2013/0241041; hereinafter Yu) and further in view of Dong et al. (U.S. 2009/0213914; hereinafter Dong).
Regarding claims 9 and 29, Applicant Admitted Prior Art (figs. 1A and 1C) discloses a leadframe for a multichip semiconductor package, comprising:
a first die pad 182 (figs. 1A and 1C) and a second die pad 192 (figs. 1A and 1C) both vertically offset relative to leads or lead terminals 114 and 124 that are positioned on at least 2 sides beyond the first die pad 182 and the second die pad 192 (figs. 1A and 1C) (e.g. the structure of AAPA (figs. 1A and 1C) is similar to the structure of the present invention (figs. 1B and 1D); thus, the first die pad 182 and the second die pad 192 (figs. 1A and 1C) both vertically offset relative to leads or lead terminals 114 and 124 (figs. 1A and 1C).
Applicant Admitted Prior Art (figs. 1A and 1C) do not disclose at least one of the first and second die pads has a reduced thickness portion and isolation component.
However, Yu et al. discloses a device comprising: the first die pad and second die pad (see labeled fig. 1K) has a reduced thickness portion (see labeled fig. 1K) and a full thickness portion (see labeled fig. 1K), the reduced thickness portion including top and bottom planar surfaces (labeled fig. 1K; e.g. the reduced thickness portion including a portion of top planar surface);
a first integrated circuit (IC) die (fig. 1K) on the first die pad (see labeled fig. 1K) which has a first bond pad (fig. 1K) connected to a first of the leads or the lead terminals (see labeled fig. 1K), the first IC die including functional circuitry configured for realizing a transmitter or a receiver (e.g. the wiring connections between the die and the leads for transmitting or receiving in fig. 1K);
a second IC die 120 on the second die pad (see labeled fig. 1K) which has a second bond pad (fig. 1K) connected to a second of the leads or the lead terminals (see labeled fig. 1K), the second IC die 120 including functional circuitry configured for realizing another of the transmitter and the receiver (e.g. the wiring connections between the die and the leads for transmitting or receiving in fig. 1K).
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of AAPA (figs. 1A and 1C) by having at least one of the first and second die pads has a reduced thickness portion, as taught by Yu, in order to enhance the structural strength for the semiconductor package.
Furthermore, Dong discloses a device comprising: an isolation component (e.g. a capacitive isolator 1602 (fig. 15, ¶0083)) in a signal path of the isolation device on at least one of the first and second IC die 1604 or 1606 (fig. 15) for capacitive isolation.
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of AAPA (figs. 1A and 1C) and Yu by having the isolation component in the signal path of the isolation device on at least one of the first and second IC die, as taught by Dong, in order to provide the isolation circuit for the device.
Regarding claims 10 and 30, Dong discloses that wherein the isolation component comprises the capacitive isolator 1602 (fig. 15).
Regarding claim 11, Dong discloses that wherein the isolation component comprises the capacitive isolator 1602 (fig. 15). It would have been obvious to one of ordinary skill in the art at the time of the invention was made to provide the isolation component comprises two capacitive isolators, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claims 12 and 32, Yu discloses that wherein the reduced thickness portion (fig. 1K) has a thickness that is 20% to 80 % of the full thickness portion (fig. 1K).
Regarding claims 13 and 33, Yu discloses that wherein both the first and second die pads (see labeled fig. 1K) have the reduced thickness portion (fig. 1K).
Regarding claims 14 and 34, Yu discloses that wherein the full thickness portion (see labeled fig. 1K) is between the reduced thickness portion (see labeled fig. 1K) and it would have been obvious to one of ordinary skill in the art at the time of the invention was made to provide the full thickness portion under the die pad.
Regarding claims 15 and 35, Yu discloses that the device further comprising thinning in a portion of an inside portion (see labeled fig. 1K) of the leads or the lead terminals (fig. 1K).
Regarding claims 16 and 36, AAPA (fig. 1A) discloses that wherein the vertically offset comprises a downset (fig. 1A).
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (figs. 1A and 1C) and Yu et al. (U.S. 2013/0241041; hereinafter Yu) in view of Dong et al. (U.S. 2009/0213914; hereinafter Dong) and further in view of Coyne (U.S. 2017/0133841).
As discussed in details above, Applicant Admitted Prior Art (figs. 1A and 1C) and Yu as modified by Dong substantially disclose all the limitations as claimed above except for the isolation component comprises the transformer isolation.
However, Coyne discloses a method comprising: wherein the isolation component comprises the transformer isolation (figs. 6-7, ¶0042, line 38+ and ¶0043).
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the method of AAPA (figs. 1A and 1C), Yu and Dong by having the isolation component comprising the transformer isolation, as taught by Coyne, in order to provide a suitable isolation component and improve the electrical isolation property of the module.
Response to Arguments
Applicant's arguments filed 09/08/2025 have been fully considered but they are not persuasive.
The Applicant argues that Applicant Admitted Prior Art (figs. 1A and 1C) and reference of Yu et al. do not disclose the currently amended limitation of the reduced thickness portion including top and bottom planar surfaces, as amended in currently amended independent claims 1, 9, 21 and 29.
This argument is respectfully traversed because the reference of Yu et al. discloses the currently amended limitation of the reduced thickness portion including top and bottom planar surfaces (labeled fig. 1K; e.g. the reduced thickness portion including a portion of top planar surface).
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media_image5.png
Greyscale
Therefore, the rejection is properly maintained. Dependent claims 2-8, 10-16, 22-28 and 30-36 fall with the independent claims 1, 9, 21 and 29, respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eva Yan Montalvo whose telephone number is (571)270-3829. The examiner can normally be reached M-TH 9AM-7PM ET.
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/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818
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