Prosecution Insights
Last updated: October 25, 2026
Application No. 16/486,967

Chip Card and Method for Fabricating a Chip Card

Non-Final OA §103
Filed
Aug 19, 2019
Priority
Mar 03, 2017 — FR 1751760 +1 more
Examiner
WALSH, DANIEL I
Art Unit
2876
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Linxens Holding
OA Round
6 (Non-Final)
64%
Grant Probability
Moderate
6-7
OA Rounds
0m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 64% of resolved cases
64%
Career Allowance Rate
520 granted / 807 resolved
-3.6% vs TC avg
Moderate +12% lift
Without
With
+12.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
41 currently pending
Career history
893
Total Applications
across all art units

Statute-Specific Performance

§101
12.3%
-27.7% vs TC avg
§103
56.3%
+16.3% vs TC avg
§102
9.7%
-30.3% vs TC avg
§112
15.9%
-24.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 807 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-2, 6-13, and 17-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosquet et al. (FR 3025634) in view of Finn (US 20130140370, hereinafter Finn ‘370) and Finn (US 20080283615). Re claim 1, Bosquet et al. teaches: Providing at least one intermediate sheet (is silent to the top and bottom) comprising at least one conductive circuit formed as an internal wiring forming an antenna on said intermediate sheet (antenna 24 embedded in the body 14 of the card 10), Providing at least one second conductive circuit comprising at least two bonding pads (is silent to etching of a conductive material laminated on a flexible substrate, each one of said bonding pads comprising a first and second electrically connected portion, the second portion of each of the pads comprising a solder drop) as the microprocessor 16 has pads on the front for interfacing with a contact reader and is shown with bonding pads on the rear for contacting the antenna and other modules as is known in the art. Laminating at least one top sheet, bottom sheet, intermediate sheet, and said at least one second conductive circuit together, to form a card body made of plastic material (“The card 10 comprises a body 14 plastic, for example made of PVC, PET or polycarbonate”, and “First, a step of assembling plastic layers is carried out. An internal layer of the body 14 comprises a substrate on which is mounted a battery 32 and interconnection tracks 36 connected on the one hand to the battery 32. The layers are assembled together by high temperature and pressure lamination. Then, the method consists in machining the cavity 38 in the assembly obtained to form the body 14 of the card. According to another method, the body and the cavity are directly formed by molding. The cavity is adapted to receive the display which has a screen. At least one interconnection track opens into the cavity 38 to electrically connect the display to the battery. Then the display 12 is placed in the cavity and electrically connected to the battery. The display is mounted so that the screen is oriented towards the opening of the cavity 38. The module 20 is then positioned flush with the first face of the body 14 and assembled by applying a heating of minimum 150 ° C. and a pressure of at least two bars on the said substrate 22 the first module 20 being positioned flush with the first body face 14. Then, the module is printed so as to produce a pattern delimiting a window 26 for visual access to the right of the screen 28 of the display positioned in the cavity 38. For this purpose, printing is carried out after step d 'inserting, on the external face of the module 20 which makes it possible to personalize the module and to connect it to the card to which it is attached. Printing can also be carried out in a standard manner before the module insertion step, on one or on both sides of the module substrate.” Producing a first cavity in the thickness of the card body for a first module to be placed in (first cavity and second cavity for modules 19 and 20), Producing at least one second cavity in the thickness of the car body to place at least one second module comprising an electronic component (first and second cavity for modules 19 and 20, either 19 and 20 being electronic), Connecting said at least one conductive circuit to said at least one second conductive circuit (the antenna is connected to the microprocessor / chip which is interpreted as forming the second conductive circuit) Connecting at least one of said first module and said second module to said at least one second conductive circuit (the second module is the chip which forms the second conductive circuit and the second and first circuits are interconnected as part of the card structure) Bosquets is silent to: One top sheet and one bottom sheet, but Bosquets teaches a printing layer 44 (top) and that there are several layers to form the card, thus obviating a top and bottom layer as is routine and conventional in the art. etching of a conductive material laminated on a flexible substrate, each one of said bonding pads comprising a first and second electrically connected portion, the second portion of each of the pads comprising a solder drop, but the Examiner notes that the top of a contact chip module is well known and conventional in the art to have the rear (internal facing) bonding pads formed in such a manner to be connected to internal circuitry, and thus such limitations are routine and conventional and would have been obvious to one of ordinary skill in the art to use conventional techniques for chip module mounting. In analogous art, Finn ‘370 teaches that bonding pads on both top and underside of a chip module are taught which are etched on both sides to form the contact pads, wherein copper clad is interpreted as a lamination/ lamination is an obvious type of copper cladding technique selected from known means to clad/ coat. Nonetheless, Finn teaches a card with a plurality layers (multiple layer inlay 200 has top bottom and intermediate sheets), wherein the chip module 242 terminals 248 for contact to the antenna using a hot bond tool (paragraph [0132]+, wherein the choice of solder is an obvious expedient as one of a plurality of types of electrical interconnection materials one of ordinary skill in the art would have at their disposal to choose from (paragraph [0140]+ teaches solder). At least one top sheet, one bottom sheet, and one intermediate sheet comprising at least one conductive circuit are provided (plastic body (made of PVC/ PET/ Polycarbonate lamination) followed by cavity 38 delimited by body 14 made by a milling cutter 15 for example). A conductive circuit is provided via antenna 24 embedded in the card body, which is the recited internal wiring that is forming an antenna on said intermediate sheet. As discussed above the sheets are laminated together. A first cavity has been taught above re cavity 38. The first module connects to the circuit (page 7, line 3-5 and FIG. 2+ wherein the module connects to the antenna), at least one second cavity produced in the thickness of the card body to place at least one second module comprising an electronic component to connect the second module to a conductive circuit (second module 20 is in second cavity 38). As the second module is connected to the battery 32 it is interpreted as being connected to a conductive circuit. The first conductive circuit formed as an internal wiring on the intermediate sheet. The second conductive circuit recited as comprising at least two bonding pads of a conductive material laminate on a flexible substrate is suggested by the lines 36 (used to connect the modules 19 and 20 together or to the battery). The bonding pads connect the module to the lines 36 at 40/42. The bonding pads are formed on an inner layer of the laminate structure and as such are conductive material laminated on the flexible substrate. Re the limitation that the first conductive circuit is formed as an internal wiring on the intermediate layer, the Examiner has interpreted that Finn also teaches such limitations via 36 as the tracks are on an internal layer and can be connected to the display and battery. Alternatively, antenna 24 formed on plastic body 14 can read on the first conductive circuit. Re the limitations that a second conductive circuit with at least two bonding pads laminated thereon each comprising a first and second interconnected portion wherein the second portion comprises a solder drop, the second conductive circuit can be interpreted as the display/battery and tracks 36. Two bonding pads are taught at plates 42 which as a result of machining are exposed (paragraph [0036]+). This is interpreted as first and second electorally interconnected portions as the exposed portions of the plates are interested as one of the first/ second portions, and the opposing side of the plates which connect to circuitry are interpreted as the other of the first/ second portion. Solder drops are interpreted as spot welds 40. Even further, to clarify, Bosque teaches “The layers are assembled together by lamination at high temperature and pressure. Next, the process consists of machining the cavity 38 in the resulting assembly to form the card body 14. According to another method, the body and the cavity are directly formed by molding. The cavity is adapted to receive the display which presents a screen. At least one interconnection track opens into cavity 38 to electrically connect the display to the battery.” The inner layer is taught as being a plurality of plastic layers laminated together. A bonding pad is exposed by machining, which is interpreted as etching a conductive material as claimed. Therefore, the Examiner maintains that as the layers are laminated prior to milling the cavity (wherein the milling/machining of the cavity is what exposes the copper plates) this is interpreted to read on the limitation of the lamination including the bonding pads which are laminated as part of the card body prior to milling/ machining and thus are laminated on a flexible substrate as one of the intermediate or separate substrate. Re the limitations of laminating to form a card body is taught (paragraph [0051]+ and as discussed above wherein the body is laminated prior to machining/ milling). Re the limitation of connecting the modules, the Examiner note the modules are connected in cavities in that they are part of the working card. Re the limitations of producing a first and second cavity, cavity 38 is a first cavity for holding a display. Claim 6 of Bosquet et al. teaches first and second cavities for first and second modules but is silent to explicitly reciting the chip. Though silent to another cavity to hold the chip the Examiner notes that such limitations are known and conventional in the art and obvious in light of the FIG. 1+ of Bosquet et al. Finn also teaches such limitations (paragraph [0098]+) connecting the module in the cavity and to the wire ends of the antennas. Prior to the effective filing date it would have been obvious to combine the teachings for milling to achieve depth for connections, thus using known techniques for known results. Re claim 2, the second conductive circuit is a connection unit on the intermediate sheet to connect a module to a conductive circuit, such as a chip to the first conductive circuit/ antenna. Re claim 6, solder has been discussed above, re claim 1. Re claims 7-8, as discussed above, the first and second portions are located on one side as they are used to connect to the internal wiring within a cavity. Re claim 9, Finn teaches the contacts on opposite sides of the circuit/ module/ chip (FIG. 2C and Finn ‘370 with CP and BP on opposite sides of the module/ circuit, as well, for connectivity. Re claim 10, the Examiner has interpreted that the connection is made in a cutout, such as the cavities as discussed above. Re claim 11, laminating prior to insertion has been discussed above, and is an obvious expedient so as to not expose the chip and modules to heat to reduce damage. Re claim 12, the limitations have been discussed above, wherein it is known to mill/ form cavities before insertion, in order to have a cavity to insert. Re claim 13, as discussed above, the prior art teaches laminating before component insertion, as laminating can “seriously damage the component” and thus would have been obvious for protecting against damage to place after cutouts/ cavity formation. As discussed above, milling/ machining is performed after lamination which reads on producing the cutout. Lamination has been discussed above wherein several thin layers are laminated to form a plastic body. Re claim 17, the limitations have been discussed above re claim 1. Re claim 18, the prior art teaches such limitations via the contacts for contact reading and the module 20. Re claims 19-20, though a display 12/20 is taught by the prior art, Bosquet et al. teaches that it can be a fingerprint sensor and is not limited to a display and any other type of electronic component can be applied, including a . Accordingly, it would have been obvious to connect to a microcontroller for biometric for controlling the additional function of a fingerprint sensor or other electronic device, such as a BLE/ WIFI, etc. as recited, for such expected results associated with trying different known electronic elements. Re claim 21, Bosquet et al. silent to explicitly reciting two bonding pads on opposite faces of a dielectric substrate interconnected through the substrate. The Examiner notes that as Bosquet et al. teaches modules inserted into cavities it would have been obvious, as known in the art, for there to be opposing pads for connectivity outside the card and internally, on opposite faces of a carrier/ inlay/ dielectric substrate. Nonetheless, Finn et al. teaches such limitations (FIG. 2C+ which teaches a module with opposing pads/ terminals 250 and 248 on opposite sides of the carrier/ inlay 242. It would have been obvious for 242 to be dielectric for the desired properties in IC module applications, such as low conductivity. Re claim 22, the Examiner notes that the card has a laminated structure and therefore bonding pads are formed on a same substrate as the wiring, such as the card being laminated is in itself a flexible substrate of indistinguishable layers. Alternatively, the Examiner notes that the limitation “on” can be interpreted as below or above and therefore at least two bonding pads formed “on the same substrate as the wiring is read on by the pads being above, below, or directly above/below the substrate, and therefore reads on the claim limitations. The pads can be interpreted as terminals/ pads on an outside of the card or internal, and still read on the limitations. Further, the pads are on the same surface interpreted as when they are exposed by milling. Claims 13-16 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosquet et al./ Finn/ Finn ‘370 , as discussed above, in view of Snell et al. (US 20190102662). Re claims 13-16, the limitations are drawn to cutouts being formed at different times relative to laminating and module placement, which is not explicitly taught by Bosquet et al. Snell et al. generally teaches (paragraph [0040]+) that removing material can be performed before or after lamination, that cavities can be cut before lamination of the card, etc. Therefore it would have been obvious to combine the teachings in order to accommodate different modules and their subsequent placement, taking into account damage, sizing, convenience, and manufacturing techniques available. Re claim 21, Bosquet et al./ Finn ‘370/ Finn is silent to explicitly reciting two bonding pads on opposite faces of a dielectric substrate interconnected through the substrate (the dielectric not being the module substrate. The Examiner notes that as Bosquet et al. teaches modules inserted into cavities it would have been obvious, as known in the art, for there to be opposing pads for connectivity outside the card and internally, on opposite faces of a carrier/ inlay/ dielectric substrate. FIG.4 of Snell shows pads 20 and FIG. 6 shows the opposite side (exposed side) of pads. Thus the pads are on opposite sides of the carrier body. It would have been obvious to combine for the body to be dielectric for desired properties for the module. Claim 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosquet et al./ Finn/ Finn ‘370, as discussed above, in view of Zhang et al. (US 9449912). Bosquet et al/ Finn/ Finn ‘370 is silent to explicitly reciting two bonding pads on opposite faces of a dielectric substrate interconnected through the substrate (not the chip module). The Examiner notes that as Bosquet et al. teaches modules inserted into cavities it would have been obvious, as known in the art, for there to be opposing pads for connectivity outside the card and internally, on opposite faces of a carrier/ inlay/ dielectric substrate. Zhang et al. teaches such limitations via dielectric 120 with pads 136 and 116+ on opposite sides of the dielectric and interconnected through the dielectric. Prior to the effective filing date it would have been obvious to combine the teachings for well-known conventional support and pad/ terminal connectivity. Claims 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosquet et al./ Finn ‘370/ Finn , as discussed above, in view of Inamoto (US 6250555). Bosquet et al./ Finn is silent to explicitly reciting two bonding pads on opposite faces of a dielectric substrate interconnected through the substrate (not the module). The Examiner notes that as Bosquet et al. teaches modules inserted into cavities it would have been obvious, as known in the art, for there to be opposing pads for connectivity outside the card and internally, on opposite faces of a carrier/ inlay/ dielectric substrate. Nonetheless, Inamoto teaches (col 6, line 63+) that an IC module is mounted in a recess, fabricated by forming an electrode pattern (external terminal, which is analogous to one of the bonding pads on opposite face) that there is an IC chip electrode formed on a glass epoxy (dielectric) substrate, and the face of the terminal is electrically conducted with the circuit pattern through a through hole, and the chip is mounted on the substrate and then sealed). Prior to the effective filing date it would have been obvious to combine the teachings for conventional use of a dielectric for chip mounting/ fabricating an IC card, as known and conventional in the art. Re claim 22, as there are layers, the bonding pads are formed on a same flexible substrate, because the card is a stacked structure of layers, and therefore bonding pads which are attached to a layer or layers are therefore formed on the substrate. The broad language reciting “formed on” can read on any sides of a multilayer structure or any sides of a substrate absent more precise recitations. Allowable Subject Matter Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach at least the second conductive circuit with two bonding pads is used for connecting the internal wiring to the first module (re claim 3), for connecting the internal wiring to the second module (claim 4) and for connecting the internal wiring to first and second modules as per claim 5.. Response to Arguments Applicant's arguments filed have been fully considered but they are not persuasive in light rejections above. The Examiner has cited new art above. Additional Remarks The Examiner notes that Lee (US 2015008106) teaches forming a cavity after lamination (abstract), Suwald US 20170116505) teaches lamination then filing of milled openings (paragraph [0043]+), and Eymard (US 20190026621) teaches after lamination, the cavity is milled to put a module and expose lands of the antenna each equipped with respective solder pads (paragraph [0045]+). The Examiner notes that Kim Yong-Jun et al. (US 20120273577) alternatively could be applied above for two conductive circuits (inlay and bonding pads) separately formed. As the inner layer is part of a laminated structure, the layer and elements thereon area interpreted as laminated in the structure. Additionally, re claim 14, the Examiner seeks clarification how lamination is after cutouts when claim 1 recites lamination prior to cut outs. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL I WALSH whose telephone number is (571)272-2409. The examiner can normally be reached on 7-9pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steve Paik can be reached on 5712722404. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL I WALSH/Primary Examiner, Art Unit 2887
Read full office action

Prosecution Timeline

Show 13 earlier events
Jan 07, 2024
Response after Non-Final Action
Oct 23, 2025
Non-Final Rejection mailed — §103
Jan 09, 2026
Interview Requested
Jan 20, 2026
Examiner Interview Summary
Jan 20, 2026
Applicant Interview (Telephonic)
Jan 22, 2026
Response Filed
Jul 30, 2026
Final Rejection mailed — §103
Sep 25, 2026
Response after Non-Final Action

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Prosecution Projections

6-7
Expected OA Rounds
64%
Grant Probability
77%
With Interview (+12.4%)
3y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 807 resolved cases by this examiner. Grant probability derived from career allowance rate.

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