Prosecution Insights
Last updated: April 19, 2026
Application No. 16/486,967

Chip Card and Method for Fabricating a Chip Card

Non-Final OA §103
Filed
Aug 19, 2019
Examiner
WALSH, DANIEL I
Art Unit
2876
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Linxens Holding
OA Round
5 (Non-Final)
65%
Grant Probability
Moderate
5-6
OA Rounds
3y 0m
To Grant
76%
With Interview

Examiner Intelligence

Grants 65% of resolved cases
65%
Career Allow Rate
510 granted / 787 resolved
-3.2% vs TC avg
Moderate +11% lift
Without
With
+11.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
74 currently pending
Career history
861
Total Applications
across all art units

Statute-Specific Performance

§101
13.0%
-27.0% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 787 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-13, and 17-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosquet et al. (FR 3025634) in view of Finn (US 20080283615). Re claim 1, Bosquet et al. teaches: At least one top sheet, one bottom sheet, and one intermediate sheet comprising at least one conductive circuit are provided (plastic body (made of PVC/ PET/ Polycarbonate lamination) followed by cavity 38 delimited by body 14 made by a milling cutter 15 for example). A conductive circuit is provided via antenna 24 embedded in the card body. As discussed above the sheets are laminated together. A first cavity has been taught above re cavity 38. The first module connects to the circuit (page 7, line 3-5 and FIG. 2+ wherein the module connects to the antenna), at least one second cavity produced in the thickness of the card body to place at least one second module comprising an electronic component to connect the second module to a conductive circuit (second module 20 is in second cavity 38). As the second module is connected to the battery 32 it is interpreted as being connected to a conductive circuit. The first conductive circuit formed as an internal wiring on the intermediate sheet. The second conductive circuit recited as comprising at least two bonding pads of a conductive material laminate on a flexible substrate is suggested by the lines 36 (used to connect the modules 19 and 20 together or to the battery). The bonding pads connect the module to the lines 36 at 40/42. The bonding pads are formed on an inner layer of the laminate structure and as such are conductive material laminated on the flexible substrate. Re the limitation that the first conductive circuit is formed as an internal wiring on the intermediate layer, the Examiner has interpreted that 36 teaches such limitations as the tracks are on an internal layer and can be connected to the display and battery. Alternatively, antenna 24 formed on plastic body 14 can read on the first conductive circuit. Re the limitations that a second conductive circuit with at least two bonding pads laminated thereon each comprising a first and second interconnected portion wherein the second portion comprises a solder drop, the second conductive circuit can be interpreted as the display/battery and tracks 36. Two bonding pads are taught at plates 42 which as a result of machining are exposed (paragraph [0036]+). This is interpreted as first and second electorally interconnected portions as the exposed portions of the plates are interested as one of the first/ second portions, and the opposing side of the plates which connect to circuitry are interpreted as the other of the first/ second portion. Solder drops are interpreted as spot welds 40. Even further, to clarify, Bosque teaches “The layers are assembled together by lamination at high temperature and pressure. Next, the process consists of machining the cavity 38 in the resulting assembly to form the card body 14. According to another method, the body and the cavity are directly formed by molding. The cavity is adapted to receive the display which presents a screen. At least one interconnection track opens into cavity 38 to electrically connect the display to the battery.” The inner layer is taught as being a plurality of plastic layers laminated together. A bonding pad is exposed by machining, which is interpreted as etching a conductive material as claimed. Therefore, the Examiner maintains that as the layers are laminated prior to milling the cavity (wherein the milling/machining of the cavity is what exposes the copper plates) this is interpreted to read on the limitation of the lamination including the bonding pads which are laminated as part of the card body prior to milling/ machining and thus are laminated on a flexible substrate as one of the intermediate or separate substrate. Re the limitations of laminating to form a card body is taught (paragraph [0051]+ and as discussed above wherein the body is laminated prior to machining/ milling). Re the limitation of connecting the modules, the Examiner note the modules are connected in cavities in that they are part of the working card. Re the limitations of producing a first and second cavity, cavity 38 is a first cavity for holding a display. Claim 6 of Bosquet et al. teaches first and second cavities for first and second modules but is silent to explicitly reciting the chip. Though silent to another cavity to hold the chip the Examiner notes that such limitations are known and conventional in the art and obvious in light of the FIG. 1+ of Bosquet et al. Nonetheless, Finn teaches such limitations (paragraph [0098]+) connecting the module in the cavity and to the wire ends of the antennas. Prior to the effective filing date it would have been obvious to combine the teachings for milling to achieve depth for connections, thus using known techniques for known results. Re the newly added limitations that the bonding pads are made by etching a conductive material laminated on a flexible substrate that is one of the intermediate sheet or a separate substrate, as discussed above, the Examiner notes that Bosquet et al. teaches that each end of the wire (tracks 36) is connected to a copper plate 42 added to the inner layer and that machining makes it possible to open these plates 42 into the bottom of the cavity 38. Copper plates 42 are fixed on elements and a weld point 40 (solder point) is formed between the plates. Therefore, the Examiner has interpreted that the inner layer comprises a plurality of layers (plastics) laminated together to form a substrate. The tracks 36 are taught as being made in an inner layer such as by additive methods of adding conductive material to an inner layer such as embedded copper wires or silk-screening. Each end of the wire is connected to a copper plate 42 that is added to the inner layer. Since machining (interpreted as etching) opens these layers, this is intpereted as etching conductive material as it pertains to the claimed pads. The claims do not recite what type of conductive (heat, light, electricity, etc.) the material is or even a level of conductance (high/ low) and thus the machining of the inner layer to reveal the pads is interpreted as etching a conductive material as recited in the claims. The claims do not recite the machining is of the backside of an IC module/inlay comprising the IC module, for example, on either side of the encapsulated processor chip within the cavity. Each of the bonding pads (plates) have a solder point thereon. As “portions” has not been defined, each pad can be interpreted as having first and second electrically connected portions via first and second areas of the pad. A solder drop has been discussed above via the solder/ weld point, which is intepted as the second portion. The Examiner has intpereted that the sheets and circuits are laminated together to form a plastic card body with two cavities therein for the 2 modules (display 12 and microprocessor 16 for example). The display and microprocessor are connecting the first and second cavity to the second conductive circuit, wherein the first conductive circuit is claimed as being formed as an internal wiring, and thus tracks 36 are interpreted as the first conductive circuit. The second conductive circuit recited by providing the bonding pads, and the second conductive circuit can be interpreted as including the first and second modules in their respective cavities, which are also connected to 36. Re claim 2, the other conductive circuit with the bonding pads is interpreted as a connection unit added to the internal wiring inlay to connect a module to a conductive circuit (FIG. 1B+), and as the two circuits have been discussed above. Re claim 3, FIG. 1B+ shows such limitations, and the two circuits have been discussed above. Re claim 4, FIG. 1B+ shows such limitations as the bonding pads connect the second module to the battery and also to the first/ second module, using 36, as the two circuits have been discussed above. Re claim 5, the Examiner notes that bonding pads are known and conventional in the art, as taught above, for connecting modules to wires/ antennas for example. The two modules have been discussed above. The connection of the first and second modules to internal wiring is discussed above, wherein the wiring can be interpreted as the tracks 36 or the antenna as discussed above. Re claim 6, welding points 40 can be solder connected as taught by the art. Re claim 7, FIG. 1B+ shows portions of wirings attached to the bonding pads. The bonding pads are attached on one side to the module and another side to the tracks/ wiring. Re claim 8, the Examiner notes that the first and second portions are interpreted as on one side of a separate substrate such as a different substrate than the inner layer, or alternatively, as the wires connected to plates/ studs are in the inner layer and exposed by the milling/ machining, they are interpreted as on a top side for example of the inner/ intermediate sheet. Re claim 9, FIG. 1B+ teaches the first and second portions on opposite sides of the circuit, such as when they are from opposing pads. Re claim 10, the wires are disclosed as being embedded or screen printed, which is interpreted as cut outs in the inlay. Re claim 11, laminating prior to insertion has been discussed above. Re claim 12, the limitations have been discussed above, wherein it is known to mill/ form cavities before insertion, in order to have a cavity to insert. Re claim 13, as discussed above, the prior art teaches laminating before component insertion, as laminating can “seriously damage the component” and thus would have been obvious for protecting against damage to place after cutouts/ cavity formation. As discussed above, milling/ machining is performed after lamination which reads on producing the cutout. Lamination has been discussed above wherein several thin layers are laminated to form a plastic body. Re claim 17, the limitations have been discussed above re claim 1. Re claim 18, FIG. 1B+ shows the flush contacts and the second module 20 is the display powered by the battery. Re claims 19-20, though a display 12/20 is taught by the prior art, Bosquet et al. teaches that it can be a fingerprint sensor and is not limited to a display and any other type of electronic component can be applied, including a . Accordingly, it would have been obvious to connect to a microcontroller for biometric for controlling the additional function of a fingerprint sensor or other electronic device, such as a BLE/ WIFI, etc. as recited, for such expected results associated with trying different known electronic elements. Re claim 21, Bosquet et al. silent to explicitly reciting two bonding pads on opposite faces of a dielectric substrate interconnected through the substrate. The Examiner notes that as Bosquet et al. teaches modules inserted into cavities it would have been obvious, as known in the art, for there to be opposing pads for connectivity outside the card and internally, on opposite faces of a carrier/ inlay/ dielectric substrate. Nonetheless, Finn et al. teaches such limitations (FIG. 2C+ which teaches a module with opposing pads/ terminals 250 and 248 on opposite sides of the carrier/ inlay 242. It would have been obvious for 242 to be dielectric for the desired properties in IC module applications, such as low conductivity. Re claim 22, the Examiner notes that the card has a laminated structure and therefore bonding pads are formed on a same substrate as the wiring, such as the card being laminated is in itself a flexible substrate of indistinguishable layers. Alternatively, the Examiner notes that the limitation “on” can be interpreted as below or above and therefore at least two bonding pads formed “on the same substrate as the wiring is read on by the pads being above, below, or directly above/below the substrate, and therefore reads on the claim limitations. The pads can be interpreted as terminals/ pads on an outside of the card or internal, and still read on the limitations. Further, the pads are on the same surface interpreted as when they are exposed by milling. Claims 13-16 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosquet et al./ Finn , as discussed above, in view of Snell et al. (US 20190102662). Re claims 13-16, the limitations are drawn to cutouts being formed at different times relative to laminating and module placement, which is not explicitly taught by Bosquet et al. Snell et al. generally teaches (paragraph [0040]+) that removing material can be performed before or after lamination, that cavities can be cut before lamination of the card, etc. Therefore it would have been obvious to combine the teachings in order to accommodate different modules and their subsequent placement, taking into account damage, sizing, convenience, and manufacturing techniques available. Re claim 21, Bosquet et al./ Finn is silent to explicitly reciting two boding pads on opposite faces of a dielectric substrate interconnected through the substrate (the dielectric not being the module substrate. The Examiner notes that as Bosquet et al. teaches modules inserted into cavities it would have been obvious, as known in the art, for there to be opposing pads for connectivity outside the card and internally, on opposite faces of a carrier/ inlay/ dielectric substrate. FIG.4 of Snell shows pads 20 and FIG. 6 shows the opposite side (exposed side) of pads. Thus the pads are on opposite sides of the carrier body. It would have been obvious to combine for the body to be dielectric for desired properties for the module. Claim 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosquet et al./ Finn, as discussed above, in view of Zhang et al. (US 9449912). Bosquet et al/ Finn is silent to explicitly reciting two bonding pads on opposite faces of a dielectric substrate interconnected through the substrate (not the chip module). The Examiner notes that as Bosquet et al. teaches modules inserted into cavities it would have been obvious, as known in the art, for there to be opposing pads for connectivity outside the card and internally, on opposite faces of a carrier/ inlay/ dielectric substrate. Zhang et al. teaches such limitations via dielectric 120 with pads 136 and 116+ on opposite sides of the dielectric and interconnected through the dielectric. Prior to the effective filing date it would have been obvious to combine the teachings for well-known conventional support and pad/ terminal connectivity. Claims 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosquet et al./ Finn, as discussed above, in view of Inamoto (US 6250555). Bosquet et al./ Finn is silent to explicitly reciting two bonding pads on opposite faces of a dielectric substrate interconnected through the substrate (not the module). The Examiner notes that as Bosquet et al. teaches modules inserted into cavities it would have been obvious, as known in the art, for there to be opposing pads for connectivity outside the card and internally, on opposite faces of a carrier/ inlay/ dielectric substrate. Nonetheless, Inamoto teaches (col 6, line 63+) that an IC module is mounted in a recess, fabricated by forming an electrode pattern (external terminal, which is analogous to one of the bonding pads on opposite face) that there is an IC chip electrode formed on a glass epoxy (dielectric) substrate, and the face of the terminal is electrically conducted with the circuit pattern through a through hole, and the chip is mounted on the substrate and then sealed). Prior to the effective filing date it would have been obvious to combine the teachings for conventional use of a dielectric for chip mounting/ fabricating an IC card, as known and conventional in the art. Re claim 22, as there are layers, the bonding pads are formed on a same flexible substrate, because the card is a stacked structure of layers, and therefore bonding pads which are attached to a layer or layers are therefore formed on the substrate. The broad language reciting “formed on” can read on any sides of a multilayer structure or any sides of a substrate absent more precise recitations. Response to Arguments Applicant's arguments filed have been fully considered but they are not persuasive in light rejections above. In response to the Applicants argument that the connection pads are not attached to the inner layer (laminated) the Examiner notes that as the wires and pads/ plates are attached to an inner layer that is then laminated, the pads are interpreted as laminated, as they subsequently accessed through machining/ milling, which is interpreted to read on the etching as newly claimed. Etching of a conductive material does not specify what type of conductive material, and thus the etching of the inner layers (plastic laminate) to expose the pads are interpreted to read on such claimed limitations. Additional Remarks The Examiner notes that Lee (US 2015008106) teaches forming a cavity after lamination (abstract), Suwald US 20170116505) teaches lamination then filing of milled openings (paragraph [0043]+), and Eymard (US 20190026621) teaches after lamination, the cavity is milled to put a module and expose lands of the antenna each equipped with respective solder pads (paragraph [0045]+). The Examiner notes that Kim Yong-Jun et al. (US 20120273577) alternatively could be applied above for two conductive circuits (inlay and bonding pads) separately formed. As the inner layer is part of a laminated structure, the layer and elements thereon area interpreted as laminated in the structure. Additionally, re claim 14, the Examiner seeks clarification how lamination is after cutouts when claim 1 recites lamination prior to cut outs. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL I WALSH whose telephone number is (571)272-2409. The examiner can normally be reached on 7-9pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steve Paik can be reached on 5712722404. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL I WALSH/Primary Examiner, Art Unit 2887
Read full office action

Prosecution Timeline

Aug 19, 2019
Application Filed
Mar 12, 2021
Non-Final Rejection — §103
Jun 14, 2021
Response Filed
Jul 01, 2021
Final Rejection — §103
Sep 17, 2021
Response after Non-Final Action
Oct 04, 2021
Request for Continued Examination
Oct 06, 2021
Response after Non-Final Action
Mar 24, 2023
Non-Final Rejection — §103
Jun 28, 2023
Response Filed
Sep 11, 2023
Final Rejection — §103
Dec 14, 2023
Response after Non-Final Action
Dec 22, 2023
Response after Non-Final Action
Jan 04, 2024
Request for Continued Examination
Jan 07, 2024
Response after Non-Final Action
Oct 20, 2025
Non-Final Rejection — §103
Jan 09, 2026
Interview Requested
Jan 20, 2026
Examiner Interview Summary
Jan 20, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
65%
Grant Probability
76%
With Interview (+11.4%)
3y 0m
Median Time to Grant
High
PTA Risk
Based on 787 resolved cases by this examiner. Grant probability derived from career allow rate.

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