DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/05/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 43 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 43 recites the limitation "each pixilated semiconductor chip" in the second last line of the claim. It is unclear whether it refers to “a plurality of pixelated semiconductor chips” recited in the 7th and 6th last lines of the claim. It is recommended to replace the limitation with “each of the pixelated semiconductor chips.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 43 is/are rejected under 35 U.S.C. 102(a)(1)/a(2) as being anticipated by Akimoto et al. (US 2014/0191258 A1).
Regarding claim 43, Akimoto et al. teach a method for manufacturing an optoelectronic semiconductor device (semiconductor light emitting device; [0002]), the method comprising: A) providing a semiconductor layer sequence (11/12; Fig. 10A, see also Fig. 1, [0024, 0153]), the semiconductor layer sequence (11/12) having a radiation side (the top side of 11/12 in Fig. 10A, i.e. 15a in Fig. 1, [0023-0024]) with a plurality of illumination areas (the top side of 11/12 of chips 3s, [0022-0024]); B) applying a photostructurable first photo layer (43 before exposure; Fig. 10A, [0154-156]) on the radiation side (the top side of 11/12; see Fig. 10A); C) photostructuring the first photo layer (exposure and removing part of 43; Fig. 10A, [0154-156]) into a structured first photo layer (patterned 43 in Fig. 10A; [0154-156]) so that the structured first photo layer (patterned 43) comprises first holes (openings in 43 in Fig. 10A above 3bs; [0154]) and remaining regions (patterned 43 in Fig. 10A; [0154-0156]), wherein first illumination areas (the top side of 11/12 of 3bs; [0154-0156]) of the semiconductor layer sequence (11/12) are accessible in the first holes (openings in 43; see Fig. 10A); D) applying a first converter material (32; Fig. 10B, [0159]) to the structured first photo layer (patterned 43) so that the first converter material (32) is disposed on a surface of the remaining regions (a top surface of the patterned 43) facing away from the semiconductor layer sequence (11/12) and partially or completely fills the first holes (opening in 43 in Fig. 10B) thereby forming first converter elements (32s; [0128]) in the first holes (opening in 43 in Fig. 10C) and so that the first converter elements (32s) cover the associated first illumination areas (the top side of 11/12 of 3bs), the surface of the remaining regions (a top surface of the patterned 43) having a normal vector oriented parallel to a stacking direction (the vertical direction) of the semiconductor layer sequence (11/12); E) removing the structured first photo layer (removing patterned 43; Fig. 10D, [0159]); F) applying a second converter material (33; Fig. 11A, [0161]) to the radiation side (the top side of 11/12) at least in regions of second illumination areas (regions of the top side of 11/12 of 3cs; [0064]) forming second converter elements (33s in the wafer; Fig. 11B, [0161, 0021]), the second illumination areas (the top side of 11/12 of 3cs) being different from the first illumination areas (the top side of 11/12 of 3bs), wherein step F) (Fig. 11A) is carried out after steps A) to E) (Figs. 10A-10D), wherein the first converter elements (32s) directly adjoin the second converter elements (33s in Fig. 11B; see Fig. 11B) in a lateral direction (the horizontal direction), wherein the first converter elements (32s) are uniquely assigned to each of the first illumination areas (the top side of 11/12 of 3bs), and wherein the second converter elements (33s in Fig. 11B) are uniquely assigned to each of the second illumination areas (the top side of 11/12 of 3cs); and after steps E) and F) (i.e. after Fig. 11B), separating the semiconductor layer sequence (11/12; [0164]) into a plurality of pixelated semiconductor chips (a plurality of units each including one central chip 3a and two peripheral chips 3b and 3c; Fig. 11D, [0164]), wherein each of the semiconductor chip (each of the units including one central chip 3a and two peripheral chips 3b and 3c) comprises a part of the semiconductor layer sequence (a part of 11/12; Fig. 11D), an active layer (the active layer 12a of the chip 3a; Fig. 11D, also see Fig. 1) and a part of the radiation side (the top side of 11/12 in Fig. 11D; also see Fig. 1) including first (the top side of 11/12 of one of the 3bs) and second illumination areas (the top side of 11/12 of one of the 3cs), wherein the active layer of each pixilated semiconductor chip (the active layer 12a of the chip 3a of each of the units including one central chip 3a and two peripheral chips 3b and 3c; Fig. 11D, also see Fig. 1) is formed contiguously (see Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 19, 20, 22, 26, 29 and 40-42 is/are rejected under 35 U.S.C. 102(a)(1)/a(2) as being anticipated by Akimoto et al. (US 2014/0191258 A1) in view of Göötz (US 2020/0051963 A1).
Regarding claim 19, Akimoto et al. teach a method for manufacturing an optoelectronic semiconductor device (semiconductor light emitting device, fourth embodiment; Figs. 5A-6C and 10A-11D, [0152-0154]), the method comprising: A) providing one semiconductor layer sequence (11/12 in Fig. 10A, see also Fig. 1, [0024, 0153]), the semiconductor layer sequence (11/12) having a radiation side (the top side of 11/12 in Fig. 10A, i.e. 15a in Fig. 1, [0023-0024]) with a plurality of illumination areas (areas of the top side of 11/12 in Fig. 10A corresponding to areas of the top side of 11/12 of chips 3s in Fig. 1, [0022-0024]); B) applying a photostructurable first photo layer (43 before exposure; Fig. 10A, [0154-156]) on the radiation side of the semiconductor layer sequence (the top side of 11/12; see Fig. 10A); C) photostructuring the first photo layer (exposure and removing part of 43; Fig. 10A, [0154-156]) into a structured first photo layer (patterned 43 in Fig. 10A; [0154-156]) so that the structured first photo layer (patterned 43) comprises first holes (openings in 43 in Fig. 10A above 3bs; [0154]) and remaining regions (patterned 43 in Fig. 10A; [0154-0156]), wherein first illumination areas of the semiconductor layer sequence (the top side of 11/12 of 3bs; [0154-0156]) are accessible via the first holes (openings in 43; see Fig. 10A); D) applying a first converter material (32; Fig. 10B, [0159]) to the structured first photo layer (patterned 43) so that the first converter material (32) is disposed on a surface of the remaining regions (a top surface of the patterned 43) facing away from the semiconductor layer sequence (11/12) and partially or completely fills the first holes (opening in 43 in Fig. 10B) thereby forming first converter elements (32s; [0128]) in the first holes (opening in 43 in Fig. 10C) and so that the first converter elements (32s) cover the associated first illumination areas (the top side of 11/12 of 3bs), the surface of the remaining regions (a top surface of the patterned 43) having a normal vector oriented parallel to a stacking direction (the vertical direction) of the semiconductor layer sequence (11/12); E) removing the structured first photo layer (removing patterned 43; Fig. 10D, [0159]); and F) applying a second converter material (33; Fig. 11A, [0161]) to the radiation side (the top side of 11/12) at least in regions of second illumination areas (regions of the top side of 11/12 of 3cs; [0064]) forming second converter elements (33s in the wafer; Fig. 11B, [0161, 0021]), the second illumination areas (the top side of 11/12 of 3cs) being different from the first illumination areas (the top side of 11/12 of 3bs), wherein step F) (Fig. 11A) is carried out after steps A) to E) (Figs. 10A-10D), wherein the first converter elements (32s) directly adjoin the second converter elements (33s in Fig. 11B; see Fig. 11B) in a lateral direction (the horizontal direction), wherein the first converter elements (32s) are uniquely assigned to each of the first illumination areas (the top side of 11/12 of 3bs), and wherein the second converter elements (33s in Fig. 11B) are uniquely assigned to each of the second illumination areas (the top side of 11/12 of 3cs).
Akimoto et al. do not teach one semiconductor layer sequence (11/12 in Fig. 10A) is one contiguous semiconductor layer sequence, and the semiconductor layer sequence is the contiguous semiconductor layer sequence.
In the same field of endeavor of semiconductor manufacturing, Göötz teaches one semiconductor layer sequence (5; Fig. 2A, [0068]) is one contiguous semiconductor layer sequence (see Fig. 2A), and the semiconductor layer sequence (5; Figs. 2B-2H, [0068]) is the contiguous semiconductor layer sequence (see Figs. 2B-2H).
Akimoto et al. teach all the claimed elements except that Akimoto et al. is using a layer with a top flat surface (the bottom layer extending from the top surface of 11/18 to the bottom surface of 23/25; Fig. 1, [0024, 0030, 0037, 0031]) containing a discontiguous semiconductor layer sequence (11/12; Fig. 10A, see also Fig. 1, [0024, 0153]) for providing primary radiation to the converter elements ([0052]) rather than a layer with a top flat surface containing a contiguous semiconductor layer.
In the same field of endeavor of semiconductor manufacturing, Göötz teaches a layer with a top flat surface (the layer on the top of the carrier layer 4; see Fig. 2A) containing a contiguous semiconductor layer (5; Figs. 2A-2H) for providing primary radiation to the converter elements ([0068]).
One of ordinary skill in the art would have recognized that a layer with a top flat surface containing a discontiguous semiconductor layer sequence and a layer with a top flat surface containing a contiguous semiconductor layer are known equivalents for providing primary radiation to the converter elements within the semiconductor art.
It would have been obvious to one of ordinary skill in the art at the time of invention was made to substitute one know element (a layer with a top flat surface containing a discontiguous semiconductor layer sequence) for another known equivalent element (a layer with a top flat surface containing a contiguous semiconductor layer) resulting in the predictable result of providing primary radiation to the converter elements (KSR rationales B).
Regarding claim 20, Akimoto et al. teach the method according to claim 19, wherein the first converter elements are (32s) in direct contact with the second converter material (33; Fig. 11B) after steps A) to F) (Fig. 5C to Fig. 11A).
Regarding claim 22, Akimoto et al. teach the method according to claim 19, further comprising removing the first converter material (32) from regions (regions of 32 above 3a and 3c; Fig. 10B, [0159]) laterally adjacent to the first holes (opening in 43 in Fig. 10A) before or during step E) (before step E of Fig. 10D).
Regarding claim 26, Akimoto et al. teach wherein applying the second converter material (33) comprises: applying a photostructurable second photo layer (44 before pattering, same process as 43; Fig. 10E, [0160, 0154-0156]) to the radiation side (the top side of 11/12); photostructuring the second photo layer (pattering 44 similar to pattering 43; Fig. 10E, [0160, 0154-0156]) into a structured second photo layer (patterned 44; Fig. 10E, [0160, 0154-0156]) such that second holes (opening above 3c in Fig. 10E) are created in the regions of the second illumination areas (regions of the top side of 11/12 of 3cs); and applying the second converter material (33) to the structured second photo layer (patterned 44 in Fig. 11A; [0161]), wherein the second converter material (33) partially or completely fills the second holes (opening above 3c in Fig. 10E; see Fig. 11A), thereby forming the second converter elements (33s in Fig. 11B) in the second holes (opening above 3c in Fig. 10E), the second converter elements (33s in Fig. 11B) covering the associated second illumination areas (the top side of 11/12 of 3cs), and wherein the second converter elements (33s) directly adjoin the first converter elements (32s; Fig. 11B).
Regarding claim 29, Akimoto et al. teach the method according to claim 19, wherein the radiation side (the top side of 11/12) further comprises third illumination areas (the top side of 11/12 of 3as), and wherein the third illumination areas (the top side of 11/12 of 3as) are kept free from the first converter material (32) and the second converter material (33; see Fig. 11C).
Regarding claim 40, Akimoto et al. teach the method according to claim 19, wherein the second converter material (33) is applied to the plurality of illumination areas (the areas of the top surfaces of 11/12) thereby covering the first illumination areas (the top side of 11/12 of 3bs) which are already covered with the first converter elements (32s; see Fig. 11A).
Regarding claim 41, Akimoto et al. teach the method according to claim 19, wherein a surface of the structured first photo layer (an upper surface of the patterned 43 in Fig. 10A) is oriented parallel to the radiation side (a surface of the radiation side, i.e., a surface of the top side of 11/12; see Fig. 10A).
Regarding claim 42, Akimoto et al. teach the method according to claim 19, wherein a surface of the structured first photo layer (an upper surface of the patterned 43 in Fig. 10A) is oriented parallel to a main plane of extension of the optoelectronic semiconductor device (the horizontal plane of the top side of 11/12; see Fig. 10A).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akimoto et al. and Göötz as applied to claim 19 above, and further in view of Madigan (US 2014/0197385).
Regarding claim 21, Akimoto et al. teach the method according to claim 19, wherein the first photo layer (43).
Akimoto et al. do not teach the first photo layer comprises a photostructurable silicone.
In the same field of endeavor of semiconductor manufacturing, Madigan teaches the first photo layer (104 of photoresist; [0051]) comprises a photostructurable silicone (photosensitive silicon; [0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Akimoto et al. and Madigan, and to have the first photo layer comprises a photostructurable silicone as taught by Madigan ([0051]), because Akimoto et al. teach the photo layer (43; [0081]) to be a photoresist layer ([0081]), but is silent about the actual material of the photoresist layer, while Madigan teaches that the photosensitive silicone is one of the common materials of the photoresist materials ([0051]).
Response to Arguments
Applicant’s amendments, filed 02/05/2026, overcome the rejections to claim 43 under 35 U.S.C. 112. The rejections to claim 43 under 35 U.S.C. 112 have been withdrawn.
Applicant's arguments with respect to claim 19 and 43 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 3/18/2026
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