Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The previous 112(b) rejection is withdrawn in view of the amendment.
Claim Rejections - 35 USC § 101
The previous 101 rejection is withdrawn in view of the amendment.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 4-8, 11-13, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Douzane US 8,447,438 in view of Coleman US 2013/0254491 and Sudo JP H07152652A.
[CLM 1]
Douzane US 8,447,438 teaches:
A computing system, comprising:
A main memory controller;
DPRAM Controller 530 [Fig. 5]
A plurality of sensors;
Sensors comprising sensing elements for a power train [C2, L8-33].
A sensor hub to execute program code for the sensors;
Host CPU to process raw data [C4, L1-21], acting as controller for controlling programmable interconnections matrix 110 to connect sensing elements with control elements of a power train [C2, L8-33]; [Figs. 1, 5].
An embedded memory coupled to the sensor hub, the sensor hub to execute the program code out of the embedded memory;
DPRAMs embedded with PIM and coupled with the host [Fig. 5].
non volatile storage to store the program code, the program code comprising instructions that when executed by the sensor hub cause the sensor hub to perform a method, comprising:
Programmable I/O bank 250 may further carry programming for portions of the control unit [Fig. 5]. Configuration information for sensors and controls may be stored in non-volatile memory [C2, L8-33][Claim 6].
Where Douzane is silent, Coleman US 2013/0254491 teaches:
A plurality of general purpose processing cores;
Multi-core processor [0017].
Douzane discloses a generic host CPU and Coleman discloses a multi-core processor. A multi-core processor is a specific CPU. Both the host CPU of Douzane and Coleman’s multi-core processor are for performing data processing for sensors (processors for processing data from peripheral devices, such as sensors [Coleman, 0003; 0017; Fig. 3]). Hence, the elements are substitutable elements because both are disclosed for performing the same function – processing data for sensors. Further, the results of the substitution would have been predictable because the elements are for performing the same function, and further because both processors were used in a real-time data processing context (automotive context of Douzane being a real-time data processing context).
Accordingly, it would have been obvious to the skilled artisan before the effective filing date of the claimed invention to substitute the generic host CPU of Douzane for the multi-core processor of Coleman, and the results of the substitution would have been predictable.
Where Coleman and Douzane are silent, Sudo JP H07152652A teaches a memory management method for a processor, comprising:
swapping out a higher priority page comprising higher priority code and/or data of the program code out of the embedded memory after the higher priority page has remained idle in the embedded memory for a first period of time; and,
swapping out a lower priority page comprising lower priority code and/or data of the program code out of the embedded memory after the lower priority page has remained idle in the embedded memory for a second period of time that is shorter than the first period of time.
Swapping out a page of a first priority after a first period of time equal to the fixed time required for the replacement pointer to reach the position of the clear pointer at the beginning of the first time period [P6].
Swapping out a page of a second priority after a second period of time equal to the fixed time required for the replacement pointer to reach the position of the clear pointer at the beginning of the second time period [P6]. The distance and time before a clean page is permitted to be evicted are shorter than the distance and time before a dirty page is permitted to be evicted [0014].
Sudo discloses assigning a priority to each page based on attributes of the contents of the page [0014][P4-5]. For example, clean pages are assigned a high replacement priority and dirty pages are assigned a low replacement priority. The priority may also be based on whether the page is read-only (code) or if the page may be written (data or stack) [P2], or an indication of an access frequency [P7].
The priority of a page is associated with the distance between the replacement pointer and the clear pointer, where the distance corresponds to a length of time the page must remain idle before it can be swapped out [0012; 0014; P6-7]. When the clear pointer encounters a page, it clears the reference bit. When the replacement pointer encounters a page, if the reference bit of that page is clear, the page is evicted. If the page is accessed after the clear pointer clears the bit but before the replacement pointer reaches the page, the reference bit will be set when the replacement pointer reaches the page, and the replacement is blocked.
Hence, each page is associated with a “predetermined time” during which the page must remain idle (not referred to, accessed, or used) in order to be eligible to be swapped out. If the page does get accessed during the time period where the replacement pointer approaches the page, the reference bit is set and the replacement pointer is unable to evict the page.
Accordingly, Sudo discloses a page swapping mechanism where pages are allowed to be swapped out after different assigned periods of time based on a processing time associated with the page.
Regarding Sudo’s use of the word “priority”:
Sudo assigns each pages a priority based on the processing required to replace them [0006].
If the cost is high, Sudo discourages swapping by assigning a low swapping priority to the page. If the cost is low, Sudo assigns a high swapping priority to the page. Hence, Sudo describes the system from the perspective where the priority is associated with replacement.
Priority may alternatively be defined based on the content of the page. A page with dirty data (page not rewritten) may be described as high priority and a page with clean data (page has been rewritten) may be described as low priority [0006-0009]. For the same reasons, the high priority page is given low swapping priority and the low priority page is given high swapping priority, based on the time required for replacement processing.
For purposes of examination, the latter definition of priority is applied.
Hence, Douzane and Coleman disclosed a system and context comprising a processor and memory for providing, processing and employing sensor data, and Sudo disclosed a memory management method for a processor and memory to improve memory efficiency.
The cited prior art of record taught each and every feature claimed. The skilled artisan could have been combined these known elements according to known methods, e.g. by using the processor of Coleman as the processor of Douzane, and using the processor and memory controller to execute the memory management method of Sudo in order to more efficiently control the contents of the memory, thus reducing the time required to perform page replacement in the memory and while still permitting limited replacement of pages with high replacement processing time [0006-0011; 0036]].
The results of the combination would have been predictable because each element is used in the same manner as disclosed to form a computing system for controlling a drivetrain based on a plurality of sensors, in which the data pages in the memory are managed based on a processing time required for replacement.
Accordingly, it would have been obvious to the skilled artisan before the effective filing date of the claimed invention to combine the system of Douzane with the processor of Coleman and the memory management method of Sudo, and the results of the combination would have been predictable.
[CLM 8][CLM 21][CLM 22]
Claims 8, 21 and 22 recite similar subject matter and are rejected on similar grounds.
[CLM 4]
4. (Currently Amended) The computing system of claim 1 wherein the first time period is greater than one second and the second time period is less than one second.
The combination teaches claim 1. While Sudo does not specify a time period associated with each of the time periods, the specific time period to assign to each priority level would have been a matter of design choice.
Accordingly, it would have been an obvious design choice to the skilled artisan before the effective filing date of the claimed invention to set the first time period to be greater than a second and the second time period to less than a second.
[CLM 11]
Claim 11 recites similar subject matter as claim 4 and is rejected on similar grounds.
[CLM 5]
5. (Original) The computing system of claim 1 wherein the method further comprises:
swapping out a medium priority page comprising medium priority code and/or data of the program code out of the embedded memory after the medium priority page has remained idle in the embedded memory for a third period of time that is less than the first time period but greater than the second time period.
The combination teaches claim 1, wherein the priority levels may include more than two priority levels (hence, there being intermediate priority levels) [Sudo, P4-5]. Each priority level may be associated with a different distance set between the associated clear pointer and replacement pointer, and therefore a different period of time the page is permitted to be idle before becoming eligible to be swapped out.
[CLM 12]
Claim 12 recites similar subject matter as claim 5 and is rejected on similar grounds.
[CLM 6]
6. (Currently Amended) The computing system of claim 1 wherein the program code comprises multiple pages each assigned to one of a plurality of different priority levels, each priority level assigned a different amount of time it is that pages of that priority level are permitted to be idle in the embedded memory before being eligible to be evicted from the embedded memory.
The combination teaches claim 1, wherein the program code comprises multiple pages each assigned to one of a plurality of different priority levels, each priority level assigned a different amount of time it is that pages of that priority level are permitted to be idle in the embedded memory before being eligible to be evicted from the embedded memory (pages may be of a plurality of different priority levels [Sudo, P4-5], and each level is associated with a clear pointer set a different distance from the replacement pointer [P5], the distance corresponding to a time before the page can be evicted).
[CLM 13]
Claim 13 recites similar subject matter as claim 6 and is rejected on similar grounds.
7. (Original) The computing system of claim 1 wherein the sensors includes any of:
a thermometer;
an accelerator;
a transducer.
The combination teaches claim 1, wherein the sensors includes any of a thermometer; an accelerator; a transducer (power train actuators/sensors to convert between mechanical and electrical signals comprise transducers [C2, L8-33]).
[CLM 23]
23. (Original) The semiconductor chip of claim 22 wherein the sensor is integrated within a peripheral control hub.
The combination teaches claim 22, wherein the sensor is integrated within a peripheral control hub (sensors 120 integrated with actuators in peripheral control hub [Douzane, Fig. 1]; element 120 comprises sensors and actuators which are peripheral to PIM 110 and host 260 and includes actuators which are considered control elements).
[CLM 24]
24. (Original) The semiconductor chip of claim 23 wherein the higher and lower pages are to be swapped out to a memory that is coupled to a memory controller that is embedded on the semiconductor chip.
The combination teaches claim 23, wherein the higher and lower pages are to be swapped out to a memory (swapped out to memory [Coleman, Fig. 1]) that is coupled to a memory controller that is embedded on the semiconductor chip (processor device 1 may be implemented as a system on a chip (SoC) comprising the cache controller [Coleman, 0017; Fig. 1]).
Claim(s) 2-3 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination as applied to claim 1 above, in further view of Ronstrom US 2001/0013087.
[CLM 2]
2. (Original) The computing system of claim 1 wherein the higher priority page does not contain lower priority code and/or data of the program code.
The combination teaches claim 1. Where the combination is silent, Ronstrom teaches:
wherein the higher priority page does not contain lower priority code and/or data of the program code (storing hot data and cold data in separate pages [0024][Figs. 2-4]).
Ronstrom teaches a principle for constructing memory pages for higher memory efficiency. Ronstrom describes a problem where pages containing data with different access frequencies are loaded or kept in the page cache [0014]. These pages can contain both hot data and cold data, which contributes to inefficient use of the memory [0019-0020].
Ronstrom discloses, based on the data access frequency of data objects, storing objects together with objects of similar access frequency [0022-0024][FIg. 4]. By storing hot data into hot pages and cold data into cold pages, hot data pages can be kept in a cache while cold data pages can be evicted. Separating hot and cold data into different pages in this manner improves memory management by reducing the space wasted in cache for storing cold data.
Accordingly, it would have been obvious to the skilled artisan before the effective filing date of the claimed invention to separate hot and cold data into different pages, thus avoiding storing lower priority code and/or data together with hot data in hot pages, as taught by Ronstrom in the memory system of the combination in order to improve the efficiency of the memory.
[CLM 9]
Claim 9 recites similar subject matter as claim 2 and is rejected on similar grounds.
[CLM 3]
3. (Original) The computing system of claim 1 wherein the lower priority page does not contain higher priority code and/or data of the program code.
The combination teaches claim 1, wherein the lower priority page does not contain higher priority code and/or data of the program code (storing hot data and cold data in separate pages [Ronstrom, 0024][Figs. 2-4]).
For similar reasons as discussed in claim 2, Ronstrom teaches avoiding storing hot data together with cold data in cold pages.
Ronstrom teaches a principle for constructing memory pages for higher memory efficiency. Ronstrom describes a problem where pages containing data with different access frequencies are loaded or kept in the page cache [0014]. These pages can contain both hot data and cold data, which contributes to inefficient use of the memory [0019-0020].
Ronstrom discloses, based on the data access frequency of data objects, storing objects together with objects of similar access frequency [0022-0024][FIg. 4]. By storing hot data into hot pages and cold data into cold pages, hot data pages can be kept in a cache while cold data pages can be evicted. Separating hot and cold data into different pages in this manner improves memory management by reducing the space wasted in cache for storing cold data.
Accordingly, it would have been obvious to the skilled artisan before the effective filing date of the claimed invention to separate hot and cold data into different pages, thus avoiding storing higher priority code and/or data together with cold data in cold pages, as taught by Ronstrom in the memory system of the combination in order to improve the efficiency of the memory.
[CLM 10]
Claim 10 recites similar subject matter as claim 3 and is rejected on similar grounds.
Response to Arguments
Applicant's arguments filed 06/24/2025 have been fully considered but they are not persuasive.
With respect to Applicant’s argument that “Applicant respectfully asserts that no person of ordinary skill in the art (POSITA) in view of what was known at the time of the invention and in light of the specification of the current application would consider a host CPU to be a sensor hub as recited in claim 1” (see pg. 22 of Applicant’s communication), the Examiner respectfully disagrees. The Examiner notes that the term “sensor hub” is not specifically defined in the current claim language. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
With respect to Applicant’s argument that “Applicant further notes Sudo does not disclose the use of embedded memory and under Sudo the pages of memory are swapped between RAM (which could be reasonably construed as main memory) and the secondary storage device. Additionally, any program code and/or instructions would be executed on the CPU of Sudo, which clearly does not fall within any reasonable interpretation of the scope of a sensor hub as claimed.” (see pg. 26 of Applicant’s communication), the Examiner respectfully disagrees. The Examiner notes that the term “embedded memory” is not specifically defined in the current claim language. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Additionally, the Examiner directs Applicant to the response above regarding the claimed “sensor hub”.
With respect to Applicant’s argument that “First, as argued above, the combination of Douzane, Coleman, and Sudo does not teach each and every feature (all limitations) claimed.” (see pg. 30 of Applicant’s communication), the Examiner respectfully disagrees and refers Applicant to the responses above.
With respect to Applicant’s argument that “First, Sudo does not execute program code out of embedded memory.” (see pg. 31 of Applicant’s communication), the Examiner respectfully disagrees. The Examiner notes that the term “embedded memory” is not specifically defined in the current claim language. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
With respect to Applicant’s argument that “Second, the pages that Sudo swaps are agnostic to any program code and/or data of the program code for sensors.” (see pg. 31 of Applicant’s communication), the Examiner respectfully disagrees. The Examiner notes that the terms “program code and/or data of the program code for sensors” are not specifically defined in the current claim language. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
With respect to Applicant’s argument that “The Examiner’s interpretation of “priority” is also incorrect and not consistent with what is disclosed in the present application (would not be as construed by a POSITA in light of the specification).” (see pg. 31 of Applicant’s communication), the Examiner respectfully disagrees. The Examiner notes that the term “priority” is not specifically defined in the current claim language. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
With respect to Applicant’s argument that “The Examiner has also failed to identify how Douzane, Coleman, and Sudo would be combined to obtain the invention of claim 1.” (see pg. 33 of Applicant’s communication), the Examiner respectfully disagrees. The Examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the results of the combination would have been predictable because each element is used in the same manner as disclosed to form a computing system for controlling a drivetrain based on a plurality of sensors, in which the data pages in the memory are managed based on a processing time required for replacement. The Examiner notes that it is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant (see MPEP 2144 IV) Additionally, the Examiner directs Applicant to the response above regarding the claimed “sensor hub”.
With respect to Applicant’s arguments regarding the dependent claims, the arguments rely on the allegation that the independent claims are patentable and therefore for the same reasons the dependent claims are patentable. However, as addressed above, the independent claims are not patentable, thus, Applicant’s arguments with respect to the dependent claims are not persuasive.
Additionally, in response to Applicant's argument that Ronstrom is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, Ronstrom is in in the field of the inventor’s endeavor, that being data storage systems.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Arpan P. Savla whose telephone number is (571)272-1077. The examiner can normally be reached M-F, 10AM-6PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached at 571-272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137