DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114 was filed in this application after a decision by the Patent Trial and Appeal Board, but before the filing of a Notice of Appeal to the Court of Appeals for the Federal Circuit or the commencement of a civil action. Since this application is eligible for continued examination under 37 CFR 1.114 and the fee set forth in 37 CFR 1.17(e) has been timely paid, the appeal has been withdrawn pursuant to 37 CFR 1.114 and prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant’s submission filed on 01/20/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goodfellow et al., US-PGPUB 2002/0144163 (hereinafter Goodfellow)
Regarding Claims 1 and 11. Goodfellow discloses a device (Abstract; Fig. 1; Paragraph [0022]) comprising:
an input configured to receive a feedback signal from a power stage circuit, an output configured to provide a control signal for controlling the power stage circuit (Paragraph [0029], input/output in a suitable feedback loop);
a digital compensator coupled between the input and the output, and configured to form a loop with the power stage circuit when the power stage circuit is coupled to the input and the output (Fig. 6, compensator block 630);
and a processor (Paragraph [0029], controller may include a digital signal processor) configured to:
provide a first injection signal having a first non-zero frequency to a first node of the loop (Fig. 6; Paragraph [0071], signal generator injecting or providing a sinusoidal waveform toward either “+” or Gain/Phase Detector 635. Note the claim does not recite that the first and second non-zero frequency are same or different);
receive a sampled signal at a second node of the loop (Fig. 6, receiving from the Power ICs; Paragraph [0023]);
provide a second injecting signal have a second non-zero frequency to a third node of the loop, the third node different the first node (Fig. 6; Paragraph [0071], signal generator injecting or providing a sinusoidal waveform toward either “+” or Gain/Phase Detector 635 that are different), and
determine a transfer function of the loop based on the first injection signal, the second injection signal and the sampled signal (Paragraph [0071]-[0072]; transfer function; Paragraph [0065]; Note: The limitation “based on” is a broad term as it implies that any recited limitations proceeding “based on" can even simply be connected conceptually in the broadest sense without actually being directly used to achieve the given objective)
Regarding Claim 2. Goodfellow discloses a simplified diagram depicting the blocks inside the Controller (Fig. 6), which includes the compensator block 630. Although the diagram shows the first node position (the adder indicated as “+”) is outside the digital compensator, it would have been obvious to have the position of the first node inside the digital compensator as well, as long as the output from the compensation is added with the injected signal generated signal.
Regarding Claim 3. Goodfellow discloses the first node is outside the digital compensator (Fig. 6)
Regarding Claim 4. Goodfellow discloses the second node is inside the digital compensator (Fig. 7)
Regarding Claim 5. Goodfellow discloses the second node is outside the digital compensator (Fig. 6)
Regarding Claim 6. Goodfellow discloses a digital signal processor (DSP) implementing the digital compensator and the processor (Paragraph [0029], controller may include a digital signal processor)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7, 9, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Goodfellow et al., US-PGPUB 2002/0144163 in view of Chapuis, US-PGPUB 2004/0156219 (hereinafter Chapuis)
Regarding Claims 7 and 12. Goodfellow discloses the DSP includes:
a digital adder configured to generate a digital error signal based on the digital feedback signal and a reference signal (Fig. 6, adder indicated by “+” or addition at Gain/Phase, Paragraph [0071])
the digital compensator configured to generate a digital control signal based on the digital error signal (Fig. 6, Compensator Block 630); and
a pulse width modulator (PWM) coupled to the output for providing the control signal based on the digital control signal (Fig. 6, PWM generator 650)
Goodfellow further discloses receiving digital information (Fig. 4, Voltage and Current A/D; Paragraph [0029], receives digital information in a suitable feedback loop)
Goodfellow does not disclose a DSP with an analog-to-digital converter (ADC) coupled to the input for converting the feedback signal to a digital feedback signal
Chapuis discloses a digital signal processor with an analog-to-digital converter (ADC) coupled to the input for converting the feedback signal to a digital feedback signal (Paragraph [0021])
At the time of the invention filed, it would have been obvious to use the teaching of Chapuis in Goodfellow and have a DSP with an analog-to-digital converter (ADC) coupled to the input for converting the feedback signal to a digital feedback signal with simplified circuitry (instead of having multiple ADCs throughout the system)
Regarding Claims 9 and 14. Goodfellow discloses the DSP includes a second digital adder configured to add the second injection signal to the digital control signal before the PWM provide the control signal (Fig. 6, adder indicated by “+” before PWM)
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Goodfellow et al., US-PGPUB 2002/0144163 in view of Nadimpalli et al., US Pat No. 7,535,204 (hereinafter Nadimpalli)
Regarding Claim 16. Goodfellow discloses a system (Abstract; Fig. 1; Paragraph [0022]) comprising:
a power stage circuit having an output terminal configured to provide an output voltage, and an input configured to receive a control signal for regulating the output voltage (Paragraph [0029], input/output in a suitable feedback loop);
a digital signal processor (DSP) (Paragraph [0029], controller may include a digital signal processor) having a first terminal coupled to the input terminal for providing the control signal to the power stage circuit, a second terminal coupled to the output terminal for receiving a feedback signal representative of the output voltage of the power stage circuit, the DSP forming a loop with the power stage circuit (Fig. 6), and configured to:
provide a first injection signal having a first non-zero frequency to a first node of the loop (Fig. 6; Paragraph [0071], signal generator injecting or providing a sinusoidal waveform toward either “+” or Gain/Phase Detector 635. Note the claim does not recite that the first and second non-zero frequency are same or different);
receiving a sampled signal at a second node of the loop (Fig. 6, receiving from the Power ICs; Paragraph [0023]);
provide a second injecting signal have a second non-zero frequency to a third node of the loop (Fig. 6; Paragraph [0071], signal generator injecting or providing a sinusoidal waveform toward either “+” or Gain/Phase Detector 635), and
determine a transfer function of the loop based on the first injection signal, the second injection signal and the sampled signal (Paragraph [0071]-[0072]; transfer function; Paragraph [0065]; Note: The limitation “based on” is a broad term as it implies that any recited limitations proceeding “based on" can even simply be connected conceptually in the broadest sense without actually being directly used to achieve the given objective)
Goodfellow discloses a switching power converter (Paragraph [0005]), but does not explicitly disclose a telecommunications system, a power stage circuit having an output terminal configured to provide an output voltage to the telecommunications system, and an input terminal configured to receive a control signal for regulating the output voltage
Nadimpalli discloses a switching power converter used in a telecommunications system, which includes a power stage circuit having an output terminal configured to provide an output voltage to the telecommunications system, and an input terminal configured to receive a control signal for regulating the output voltage (Abstract, Col. 1, lines 1-67; Col. 2, lines 1-29; Figs. 1-3; 6-9)
At the time of the invention filed, it would have been obvious to a person of ordinary skill in the art to combine the teaching of Nadimpalli and Goodfellow and use in a telecommunications system, which includes a power stage circuit having an output terminal configured to provide an output voltage to the telecommunications system, and an input terminal configured to receive a control signal for regulating the output voltage, so as to regulate power supply.
Regarding Claim 19. Goodfellow discloses the DSP includes a second digital adder configured to add the second injection signal to the digital control signal before the PWM provide the control signal (Fig. 6, “adder indicated by “+” before PWM)
7. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Goodfellow et al., US-PGPUB 2002/0144163 in view of Nadimpalli et al., US Pat No. 7,535,204 as applied to Claim 16 and further in view of Chapuis, US-PGPUB 2004/0156219.
Regarding Claim 17. Goodfellow discloses the DSP includes:
a digital adder configured to generate a digital error signal based on the digital feedback signal and a reference signal (Fig. 6, adder indicated by “+” or addition at Gain/Phase, Paragraph [0071])
the digital compensator configured to generate a digital control signal based on the digital error signal (Fig. 6, Compensator Block 630); and
a pulse width modulator (PWM) coupled to the output for providing the control signal based on the digital control signal (Fig. 6, PWM generator 650)
Goodfellow further discloses receiving digital information (Fig. 4, Voltage and Current A/D; Paragraph [0029], receives digital information in a suitable feedback loop)
Goodfellow does not disclose a DSP with an analog-to-digital converter (ADC) coupled to the input for converting the feedback signal to a digital feedback signal
Chapuis discloses a digital signal processor with an analog-to-digital converter (ADC) coupled to the input for converting the feedback signal to a digital feedback signal (Paragraph [0021])
At the time of the invention filed, it would have been obvious to use the teaching of Chapuis in the modified Goodfellow and have a DSP with an analog-to-digital converter (ADC) coupled to the input for converting the feedback signal to a digital feedback signal with simplified circuitry (instead of having multiple ADCs throughout the system)
8. Claims 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Goodfellow et al., US-PGPUB 2002/0144163 in view of Colby et al., US-PGPUB 2005/0057950 (hereinafter Colby)
Regarding Claims 10 and 15. Goodfellow discloses the injection signal includes a sinusoidal signal for power regulation (Paragraph [0071]-[0072])
Goodfellow does not disclose injecting a digitized sinusoidal signal.
Colby discloses power regulation, which includes injecting a digitized sinusoidal signal (Paragraph [0033])
Injection of sinusoidal signal for power regulation is known, which includes injection of digitized sinusoidal signal. As such, at the time of the invention filed, it would have been obvious to a person of ordinary skill in the art to use the teaching of Colby in Goodfellow and inject a digitized sinusoidal signal, so as to efficiently regulate power supply.
9. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Goodfellow et al., US-PGPUB 2002/0144163 in view of Nadimpalli et al., US Pat No. 7,535,204 as applied to Claim 16 and further in view of Colby et al., US-PGPUB 2005/0057950
Regarding Claim 20. Goodfellow discloses the injection signal includes a sinusoidal signal for power regulation (Paragraph [0071]-[0072])
The modified Goodfellow does not disclose injecting a digitized sinusoidal signal.
Colby discloses power regulation, which includes injecting a digitized sinusoidal signal (Paragraph [0033])
Injection of sinusoidal signal for power regulation is known, which includes injection of digitized sinusoidal signal. As such, at the time of the invention filed, it would have been obvious to a person of ordinary skill in the art to use the teaching of Colby in the modified Goodfellow and inject a digitized sinusoidal signal, so as to efficiently regulate power supply.
Allowable Subject Matter
Claims 8, 13 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (1, 11, 16) and (7, 12, 17), as explained before in the previous Office Action dated 06/08/2022.
Response to Arguments
Applicant's arguments filed 01/20/2026 have been fully considered but they are not persuasive based on the updated rejection as shown above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HYUN D PARK whose telephone number is (571)270-7922. The examiner can normally be reached 11-4.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arleen Vazquez can be reached at 571-272-2619. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN D PARK/Primary Examiner, Art Unit 2857