DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 24th, 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-5, 7-9, 11-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 15 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pre-Grant Patent 2018/0349762 (Lee et al; Lee).
Regarding claim 15:
Lee teaches:
1. A neural circuit, comprising: a neural array, comprising a plurality of semiconductor components,
(Lee, ¶0029)
“Referring to FIGS. 1A and 1B, a synapse array 100a of a neuromorphic device in accordance with an embodiment of the present disclosure may include a plurality of input neurons 10, a plurality of output neurons 20, a plurality of gating controllers 40, and a plurality of synapses 30a.”
2. wherein each of the semiconductor components stores a weighting value,
(Lee, ¶0035)
“That is, the synapse 30a of the synapse array 100a in accordance with an embodiment of the present disclosure can have various contributions to synapse weight through a plurality of separate individual ferroelectric films Ff1 to Ffn, and can also output the total synapse weights (e.g., current) that is averaged over, or summed through, the common floating gate electrode (Gf) [i.e. wherein each of the semiconductor components stores a weighting value,].”
3. and the semiconductor components are divided into a plurality of neural sub-groups,
(Lee, ¶0045, Fig. 2B)
“The synapse is transistors T1 to Tn may include ferroelectric field effect transistors. Drain electrodes D1 to Dn of synapse transistors T1 to Tn may be electrically connected to a common input neuron 10 and source electrodes S1 to Sn may be electrically connected to a common output neuron 20 [i.e. and the semiconductor components are divided into a plurality of neural sub-groups,].”
4. wherein each of the neural sub-groups is configured to receive a plurality of input signals and generate an output current,
(Lee, ¶0030)
“Each of the synapses 30a may include a transistor having a common floating gate electrode Gf, a plurality of individual ferroelectric films Ff1 to Ffn, and a plurality of control gate electrodes Gc1 to Gcn [i.e. wherein each of the neural sub-groups].”
(Lee, ¶0033, Fig. 1B)
“Referring again to FIG. 1B, the plurality of gating controllers 40 may be electrically connected to the plurality of control gate electrodes Gc1 to Gcn of synapse 30a through a plurality of gating control lines 41, respectively. [i.e. is configured to receive a plurality of input signals].”
(Lee, ¶0032)
“A voltage or current may be supplied from the synapse 30a to the output neuron 20. Thus, the output neuron 20 may receive and output the synaptic weight of the synapse 30a. In another embodiment of the present disclosure, the output neuron 20 may provide a voltage or current to the synapse 30a [i.e. and generate an output current
5. and a computing result is calculated based on the output current,
(Lee, ¶0035)
“The common floating gate electrode Gf may adjust a channel of the synapse 30a by averaging, or totaling, the polarization voltages Vp of the ferroelectric films Ff1 to Ffn [i.e. and a computing result is calculated based on the output current,].”
6. wherein the semiconductor components in the neural array comprises a first semiconductor component and a second semiconductor component,
(Lee, ¶0045)
“Referring to FIG. 2B, a synapse 30b may include a plurality of synapse transistors [i.e. wherein the semiconductor components in the neural array comprises] T1 to Tn connected in parallel [i.e. a first semiconductor component and a second semiconductor component,].”
7. a structure difference exists between the first semiconductor component and the second semiconductor component, and the structure difference comprises at least one of difference of gate width-to-length ratio, difference of connection of diffusion layer, difference of thickness of connected metal layer and difference of configuration of parallel-connected sub-semiconductor elements.
(Lee, ¶0045)
“Referring to FIG. 2B, a synapse 30b may include a plurality of synapse transistors T1 to Tn connected in parallel [i.e. a structure difference exists between the first semiconductor component and the second semiconductor component… difference of configuration of parallel-connected sub-semiconductor elements].”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 8-9, 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over in view of US Pre-Grant Patent 2018/0349762 (Lee et al; Lee) in view of US Pre-Grant Patent 2020/0394502 (Chen et al; Chen).
Regarding claim 1:
Lee teaches:
1. A neural circuit, comprising: a via plug;
(Lee, ¶0036, Figs. 1A, 1C)
FIG. 1C is a layout schematically illustrating the synapse array of the neuromorphic device shown in FIG. 1A. Referring to FIG. 1C, the synapse array 100a of the neuromorphic device in accordance with an embodiment of the present disclosure may include a plurality of active regions Act, a plurality of gate lines GL1 to GLn, a plurality of input neuron via plugs 10V, a plurality of output neuron via plugs 20V, and a plurality of gating via plugs 40V.
2. and a neural array, comprising a plurality of semiconductor components, wherein each of the semiconductor components stores a weighting value,
(Lee, ¶0045, Fig. 2B)
“Gate electrodes G1 to Gn of the synapse transistors T1 to Tn may include ferroelectric films Ff1 to Ffn, respectively. Accordingly, the synapse transistors T1 to Tn may independently have various levels of synapse weights according to the polarization voltages of the ferroelectric films Ff1 to Ffn, respectively [i.e. and a neural array, comprising a plurality of semiconductor components, wherein each of the semiconductor components stores a weighting value,].”
3. and the semiconductor components are divided into a plurality of neural sub-groups,
(Lee, ¶0045, Fig. 2B)
“The synapse is transistors T1 to Tn may include ferroelectric field effect transistors. Drain electrodes D1 to Dn of synapse transistors T1 to Tn may be electrically connected to a common input neuron 10 and source electrodes S1 to Sn may be electrically connected to a common output neuron 20 [i.e. and the semiconductor components are divided into a plurality of neural sub-groups,].”
4. wherein each of the neural sub-groups is configured to receive a plurality of input signals;
(Lee, ¶0030)
“Each of the synapses 30a may include a transistor having a common floating gate electrode Gf, a plurality of individual ferroelectric films Ff1 to Ffn, and a plurality of control gate electrodes Gc1 to Gcn [i.e. wherein each of the neural sub-groups].”
(Lee, ¶0033, Fig. 1B)
“Referring again to FIG. 1B, the plurality of gating controllers 40 may be electrically connected to the plurality of control gate electrodes Gc1 to Gcn of synapse 30a through a plurality of gating control lines 41, respectively. [i.e. is configured to receive a plurality of input signals].”
5. and generate an output current at an output terminal among a plurality of output terminals,
(Lee, ¶0032)
“A voltage or current may be supplied from the synapse 30a to the output neuron 20. Thus, the output neuron 20 may receive and output the synaptic weight of the synapse 30a. In another embodiment of the present disclosure, the output neuron 20 may provide a voltage or current to the synapse 30a [i.e. and generate an output current at an output terminal].”
6. and a computing result is calculated based on the output current,
(Lee, ¶0035)
“The common floating gate electrode Gf may adjust a channel of the synapse 30a by averaging, or totaling, the polarization voltages Vp of the ferroelectric films Ff1 to Ffn [i.e. and a computing result is calculated based on the output current,].”
7. wherein the semiconductor components in the neural array comprises a first semiconductor component and a second semiconductor component,
(Lee, ¶0045)
“Referring to FIG. 2B, a synapse 30b may include a plurality of synapse transistors [i.e. wherein the semiconductor components in the neural array comprises] T1 to Tn connected in parallel [i.e. a first semiconductor component and a second semiconductor component,].”
Chen teaches:
1. only a subset of the semiconductor components comprising the first semiconductor component in the neural array is connected to a first output terminal among the output terminals through the via plug,
(Chen, ¶0040, Fig. 8)
The output conductor portion EB1 [i.e. the first semiconductor component in the neural array] may be electrically connected to the conductor element KB1 [i.e. is connected to a first output terminal] and the conductor element KB2 [i.e. among the output terminals] through the contact vias 626 [i.e. only a subset of the semiconductor components comprising…through the via plug,].
Examiner notes that Fig. 8 separately routes the other KB elements elsewhere or leaves them disconnected. Hence, only a subset of components are connected.
2. and the first semiconductor component is configured to reflect, through the via plug, a weighting value provided by the first semiconductor component into the computing result,
(Chen, ¶0040)
“Then, the weighted signal may be transferred from the signal output terminals Sout of the parallel resistor to the second neural circuit NB1 through an another conductor circuits (which may comprise the output conductor portion EB1 [i.e. and the first semiconductor component is configured to reflect,], the contact vias 626 electrically connected with the output conductor portion EB1 [i.e. through the via plug, a weighting value provided by the first semiconductor component into the computing result],”
3. at least one of the semiconductor components comprising the second semiconductor component in the neural array is not connected to any output terminal among the output terminals through any via plug, such that the computing result is not influenced by the second semiconductor component due to lack of said any via plug,
(Chen, ¶0040)
“The output conductor portion EB3 is not electrically connected to the contact via 626, and may be electrically insulated from the conductor element KB5 and the conductor element KB6 by an insulating layer (not shown) formed on the conductor elements [i.e. at least one of the semiconductor components comprising the second semiconductor component in the neural array is not connected to any output terminal among the output terminals through any via plug,]”
(Chen, ¶0043)
“The unit resistor R5 and the unit resistor R6 are floating since they are not electrically connected to the output conductor portion EB3. Therefore, the weighted signal of the synapse weight W.sub.1,3 is not resulted through the unit resistor R5 and the unit resistor R6 [i.e. such that the computing result is not influenced by the second semiconductor component due to lack of said any via plug,].”
4. and the first semiconductor component connected to the via plug and the second semiconductor component not connected to said any via plug are arranged as array in the neural array.
(Chen, ¶0044)
“The synapse weights may be arranged as a plane array or a 3D array [i.e. and the first semiconductor component connected to the via plug and the second semiconductor component not connected to said any via plug are arranged as array in the neural array].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee’s neuromorphic synapse array to selectively provide output-side via connections to only a subset of the semiconductor components, as taught by Chen, in order to selectively include or exclude the weighting contributions of individual components and thereby obtain a desired synaptic weighting value, since Chen expressly teaches varying the arrangement of the contact vias “for obtaining synapse weights having expected weight values (Chen, ¶0043).”
Regarding claim 3:
The combination of Lee and Chen teaches the circuit of claim 1.
Lee teaches:
1. wherein each of the semiconductor components has a first terminal, a second terminal, and a control terminal, the first terminal is coupled to the output terminal, the second terminal is coupled to a first reference voltage, and the control terminal receives one of the input signals.
(Lee, ¶0031)
“That is, the input neuron 10 [i.e. a second terminal,] may provide a voltage or current to the synapse 30a. In another embodiment of the is present disclosure, the input neuron 10 may provide a pulse-shaped electrical signal to the synapse 30a [i.e. the second terminal is coupled to a first reference voltage,].”
(Lee, ¶0033)
“Referring again to FIG. 1B, the plurality of gating controllers 40 [i.e. a control terminal] may be electrically connected to the plurality of control gate electrodes Gc1 to Gcn of synapse 30a through a plurality of gating control lines 41, respectively [i.e. and the control terminal receives one of the input signals].”
(Lee, ¶0045)
“Referring to FIG. 2B, a synapse 30b may include a plurality of synapse transistors T1 to Tn connected in parallel [i.e. wherein each of the semiconductor components has a first terminal,]. The synapse is transistors T1 to Tn may include ferroelectric field effect transistors. Drain electrodes D1 to Dn of synapse transistors T1 to Tn may be electrically connected to a common input neuron 10 and source electrodes S1 to Sn may be electrically connected to a common output neuron 20 [i.e. the first terminal is coupled to the output terminal].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee with Chen. The motivation is the same as claim 1.
Regarding claim 5:
The combination of Lee and Chen teaches the circuit of claim 1.
Lee teaches:
1. wherein each of the semiconductor components has a first terminal, a second terminal, and a control terminal, the first terminal receives one of the input signals, the second terminal is coupled to the output terminal, and the control terminal receives a weighting adjustment signal.
(Lee, ¶0031)
“That is, the input neuron 10 may provide a voltage or current to the synapse 30a [i.e. wherein each of the semiconductor components has a first terminal,]. In another embodiment of the is present disclosure, the input neuron 10 may provide a pulse-shaped electrical signal to the synapse 30a [i.e. the first terminal receives one of the input signals].”
(Lee, ¶0045)
“Drain electrodes D1 to Dn of synapse transistors T1 to Tn may be electrically connected to a common input neuron 10 and source electrodes S1 to Sn [i.e. a second terminal,] may be electrically connected to a common output neuron 20 [i.e. the second terminal is coupled to the output terminal,].”
(Lee, ¶0045)
“Each of the gate electrodes G1 to Gn of the synapse transistors T1 to Tn may be electrically connected to different gating controllers 40, respectively [i.e. and a control terminal,]. That is, the synapse transistors T1 to Tn may have independent and separate turn-on states and turn-off states [i.e. and the control terminal receives a weighting adjustment signal].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee with Chen. The motivation is the same as claim 1.
Regarding claim 8:
The combination of Lee and Chen teaches the circuit of claim 1.
Lee teaches:
1. wherein the first semiconductor component comprises a first terminal, and the via plug is connected onto the first terminal.
(Lee, ¶0040)
“The input is neuron line 11 and the output neuron line 21 [i.e. wherein the first semiconductor component comprises a first terminal] may be disposed on the interlayer insulating layer 50 and electrically connected to the input neuron via plug 10V and the output neuron via plug 20V, respectively [i.e. and the via plug is connected onto the first terminal].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee with Chen. The motivation is the same as claim 1.
Regarding claim 9:
The combination of Lee and Chen teaches the circuit of claim 1.
Lee teaches:
1. wherein the first semiconductor component comprises a control terminal, and the via plug is connected onto the control terminal.
(Lee, ¶0037)
“The plurality of gating via plugs 40V may be disposed on end portions of the plurality of gate lines GL1 to GLn…[i.e. wherein the first semiconductor component comprises a control terminal]. In an example, the plurality of gate lines GL1 to GLn may correspond to the plurality of control gate electrodes Gc1 to Gcn or the plurality of gating control lines 41 shown in FIGS. 1A or 1B [i.e. and the via plug is connected onto the control terminal].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee with Chen. The motivation is the same as claim 1.
Regarding claim 11:
The combination of Lee and Chen teaches the circuit of claim 1.
Chen teaches:
1. wherein the output terminal has at least one metal layer, and the weighting value of each of the semiconductor components in the neural sub-groups is adjusted through the at least one metal layer.
(Chen, ¶0046)
“In an embodiment, the weight value of the synapse weight may be defined according to an amount of active transistor of the synapse weight…The first conductive layer M1D (first conductive layer M1D′) may be extended along the direction D3, and disposed on the first conductive element C1D (first conductive element C1D′) and the inter-layer dielectric (not shown). In an embodiment, the first conductive element C1D (first conductive element C1D′) and the first conductive layer M1D (first conductive layer M1D′) may be electrically connected between the source/drain 732D (source/drain 732D′) of the active transistor and the second neural circuit NBj[i.e. and the weighting value of each of the semiconductor components in the neural sub-groups is adjusted].”
“In an embodiment, the first conductive layers M1S, the first conductive layers M1D and the first conductive layers M1D′ may be a first metal layer [i.e. wherein the output terminal has at least one metal layer,].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee with Chen. The motivation is the same as claim 1.
Regarding claim 12:
The combination of Lee and Chen teaches the circuit of claim 1.
Lee teaches:
1. wherein each of the semiconductor components comprises at least one parallel-connected sub-semiconductor element, and the weighting value of each of the semiconductor components is adjusted through a number of the at least one parallel-connected sub-semiconductor element.
(Lee, ¶0045, Fig. 2B)
“Referring to FIG. 2B, a synapse 30b may include a plurality of synapse transistors T1 to Tn connected in parallel [i.e. wherein each of the semiconductor components comprises at least one parallel-connected sub-semiconductor element].”
“That is, the synapse transistors T1 to Tn may have independent and separate turn-on states and turn-off states. Therefore, a sum of the synapse weights of the synapse 30b may be determined in accordance with the turn-on states and the turn-off states of the synapse transistors T1 to Tn [i.e. and the weighting value of each of the semiconductor components is adjusted through a number of the at least one parallel-connected sub-semiconductor element].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee with Chen. The motivation is the same as claim 1.
Regarding claim 13:
The combination of Lee and Chen teaches the circuit of claim 1.
Chen teaches:
1. wherein the first terminal of the first semiconductor component is a drain terminal of the first semiconductor component.
(Chen, ¶0045, Fig. 9)
“In an embodiment, the source/drain 732S is a source, and the source/drain 732D and source/drain 732D′ are drains [i.e. wherein the first terminal of the first semiconductor component is a drain terminal].”
(Chen, ¶0046, Fig. 9)
“The other transistors of the synapse weight W.sub.1,1 are regarded as dummy transistors since the source/drains 732D and the source/drains 732D′ of the other transistors are floating and no signal is transferred to second neural circuit NBj from the source/drain 732D and the source/drains 732D′ of the other transistors [i.e. of the first semiconductor component.].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee with Chen. The motivation is the same as claim 1.
Regarding claim 14:
The combination of Lee and Chen teaches the circuit of claim 1.
Lee teaches:
1. wherein the control terminal of the first semiconductor component is a gate terminal of the first semiconductor component.
(Lee, ¶0037, Fig. 1C)
“In an example, the plurality of gate lines GL1 to GLn may correspond to the plurality of control gate electrodes Gc1 to Gcn [i.e. wherein the control terminal of the first semiconductor component is a gate terminal of the first semiconductor component].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee with Chen. The motivation is the same as claim 1.
Claims 2, 4, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over in view of US Pre-Grant Patent 2018/0349762 (Lee et al; Lee) in view of US Pre-Grant Patent 2020/0394502 (Chen et al; Chen), further in view of US Patent 5,336,937 (Sridhar et al; Sridhar).
Regarding claim 2:
Neither Lee nor Chen teaches:
1. wherein the weighting value of each of the semiconductor components corresponds to at least one of a gate width-to-length ratio and a threshold voltage of each of the semiconductor components.
Sridhar teaches:
1. wherein the weighting value of each of the semiconductor components corresponds to at least one of a gate width-to-length ratio and a threshold voltage of each of the semiconductor components.
(Sridhar, col. 4:51-54; 4:56-59)
“Each MOSFET has an associated weight value corresponding to a stored charge in its floating-gate, which causes a shift in its threshold voltage [i.e. wherein the weighting value of each of the semiconductor components corresponds to at least one of a gate width-to-length ratio]…Weight value may be repeatedly adjusted by changing the amount of this stored charge and thereby the threshold voltage shift of the MOSFET [i.e. and a threshold voltage of each of the semiconductor components].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee and Chen with Sridhar. It would have been obvious to one of ordinary skill in the art to modify Lee/Chen’s weighted semiconductor components such that their weighting values correspond to threshold voltages, as taught by Sridhar, in order to provide electrically programmable synaptic weights capable of repeated adjustment through stored charge and corresponding threshold-voltage shift, since Sridhar expressly teaches that “Weight value may be repeatedly adjusted by changing the amount of this stored charge and thereby the threshold voltage shift of the MOSFET (Sridhar, 4:56-59).”
Regarding claim 4:
Neither Lee nor Chen teaches:
1. wherein each of the semiconductor components has a first terminal, a second terminal, and a control terminal, the first terminal is coupled to the output terminal, the second terminal receives a weighting adjustment signal, and the control terminal receives one of the input signals.
Sridhar teaches:
1. wherein each of the semiconductor components has a first terminal, a second terminal, and a control terminal, the first terminal is coupled to the output terminal, the second terminal receives a weighting adjustment signal, and the control terminal receives one of the input signals.
(Sridhar, col. 4: 51-54)
“Each MOSFET has an associated weight value corresponding to a stored charge in its floating-gate [i.e. a control terminal,], which causes a shift in its threshold voltage [i.e. and the control terminal receives one of the input signals.].”
(Sridhar, col. 4: 62-67)
“The synaptic circuit consists of the gates of the MOSFETs connected to a single voltage input line, and the drains of the MOSFETs connected to a single output line [i.e. the first terminal is coupled to the output terminal]. In a first embodiment the source electrode of the P-type MOSFET is set to a positive voltage level, while the source electrode of the N-type MOSFET is set to ground [i.e. wherein each of the semiconductor components has a first terminal, a second terminal,].”
(Sridhar, col. 13: 9-13)
“The adjustment of V.sub.s from greater than or less than 0, in this case 5 V and -5 V, determines the quadrant of synaptic operation, while the weights of the MOSFETs can be adjusted to obtain the desired characteristic function [i.e. the second terminal receives a weighting adjustment signal,].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee and Chen with Sridhar. The motivation is the same as claim 2.
Regarding claim 7:
1. wherein each of the semiconductor components has a first terminal, a second terminal, and a control terminal, the first terminal receives a weighting adjustment signal, the second terminal is coupled to the output terminal, and the control terminal receives one of the input signals.
(Sridhar, col. 4: 51-54)
“Each MOSFET has an associated weight value corresponding to a stored charge in its floating-gate [i.e. a control terminal,], which causes a shift in its threshold voltage [i.e. and the control terminal receives one of the input signals.].”
(Sridhar, col. 4: 62-67)
“The synaptic circuit consists of the gates of the MOSFETs connected to a single voltage input line, and the drains of the MOSFETs connected to a single output line [i.e. the second terminal is coupled to the output terminal]. In a first embodiment the source electrode of the P-type MOSFET is set to a positive voltage level, while the source electrode of the N-type MOSFET is set to ground [i.e. wherein each of the semiconductor components has a first terminal, a second terminal,].”
(Sridhar, col. 13: 9-13)
“The adjustment of V.sub.s from greater than or less than 0, in this case 5 V and -5 V, determines the quadrant of synaptic operation, while the weights of the MOSFETs can be adjusted to obtain the desired characteristic function [i.e. the first terminal receives a weighting adjustment signal,].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee and Chen with Sridhar. The motivation is the same as claim 2.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over in view of US Pre-Grant Patent 2018/0349762 (Lee et al; Lee) in view of US Patent 5,336,937 (Sridhar et al; Sridhar).
Regarding claim 16:
Lee teaches the circuit of claim 15.
Lee teaches:
1. wherein the structure difference existed between the first semiconductor component and the second semiconductor component [causes a difference of weighting values provided by the first semiconductor component and the second semiconductor component, respectively].
(Lee, ¶0045)
“Referring to FIG. 2B, a synapse 30b may include a plurality of synapse transistors T1 to Tn connected in parallel [i.e. wherein the structure difference existed between the first semiconductor component and the second semiconductor component].”
1. [wherein the structure difference existed between the first semiconductor component and the second semiconductor component] causes a difference of weighting values provided by the first semiconductor component and the second semiconductor component, respectively.
(Sridhar, col. 13: 9-13)
“The adjustment of V.sub.s from greater than or less than 0, in this case 5 V and -5 V, determines the quadrant of synaptic operation, while the weights of the MOSFETs can be adjusted to obtain the desired characteristic function [i.e. causes a difference of weighting values provided by the first semiconductor component and the second semiconductor component, respectively].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated modify Lee with Sridhar. It would have been obvious to one of ordinary skill in the art to modify Lee’s weighted semiconductor components such that their weighting values correspond to threshold voltages, as taught by Sridhar, in order to provide electrically programmable synaptic weights capable of repeated adjustment through stored charge and corresponding threshold-voltage shift, since Sridhar expressly teaches that “Weight value may be repeatedly adjusted by changing the amount of this stored charge and thereby the threshold voltage shift of the MOSFET (Sridhar, 4:56-59).”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL JUSTIN BREENE whose telephone number is (571)272-6320. Examiner
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Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael J Huntley can be reached on 303-297-4307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786 9199 (IN USA OR CANADA) or 571-272-1000.
/P.J.B./ Examiner, Art Unit 2129
/MICHAEL J HUNTLEY/Supervisory Patent Examiner, Art Unit 2129
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