DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed September 11th, 2025 have been fully considered but they are not persuasive.
Applicant argues the Office mapping does not disclose the claimed mixed-connectivity array (via-connected first semiconductor components) and non-via-connected second semiconductor components arranged in the neural array) (Remarks, pgs. 7-8). The rejection applies Kurokawa for teaching a neural array comprising a plurality of semiconductor components/programmable logic elements that store weighting values and that are configured to receive a plurality of input signals and generate an output current at an output terminal, with a computing result calculated based on the output current (see, e.g., Kurokawa passages cited in the rejection, including col. 35:57–67; col. 35:50–53; col. 36:1–5; col. 30:57–61). The rejection applies Bae for teaching a via plug/TSV formed to pass through a semiconductor substrate and used as an interconnect structure (see, e.g., Bae col. 1:65–67; col. 2:1–2) and for connecting a semiconductor component to the via plug such that the semiconductor component’s state/weight is reflected “through the via plug” into a result (see, e.g., Bae col. 2:41–46 as cited). Under the combination, a first semiconductor component in Kurokawa’s neural array is connected to an output terminal through a via plug as taught by Bae, while at least one other semiconductor component in the same array constitutes the claimed second semiconductor component that is not connected to any output terminal through any via plug. Therefore, the mixed-connectivity structure is taught by the applied references.
Applicant further argues the cited references fail to teach that “the computing result is not influenced by the second semiconductor component due to lack of said any via plug (Remarks, pg. 7-8).” Kurokawa teaches that the computing result is calculated based on an output current at an output terminal (see, e.g., Kurokawa col. 35:50–53; col. 36:1–5 as cited). A semiconductor component that is not connected to any output terminal through any via plug does not contribute to the output-terminal current through that via-plug path and thus does not influence the computing result calculated from that output current through the via plug, as recited.
Applicant argues Kurokawa does not disclose that only a subset of elements are connected through TSV/via plug while remaining elements are deliberately not connected through TSV/via plug (Remarks, pg. 9). However, the claim does not require an express disclosure that “only a subset” is connected, nor does it require an express disclosure of intent (e.g., “deliberately”). The claim requires the structural/electrical condition that (i) a first semiconductor component is connected to a first output terminal among a plurality of output terminals through the via plug, and (ii) a second semiconductor component is not connected to any output terminal among the output terminals through any via plug. The rejection identifies a neural array including a plurality of components (Kurokawa), and then applies Bae’s via plug/TSV to provide the claimed via-plug connection path for the first semiconductor component. At least one other semiconductor component in the same array that lacks such a via-plug connection to an output terminal meets the recited “second semiconductor component … not connected … through any via plug” limitation.
Applicant argues a TSV cannot reasonably be replaced by, nor interpreted as, a switch as described in Kurokawa. The rejection does not rely on treating a TSV as a switch. The rejection cites Kurokawa’s switch SW/programming circuitry to evidence array connectivity/selection architecture (see, e.g., the Kurokawa switch discussion cited in the rejection), and separately applies Bae for the via plug/TSV structure meeting the claimed “via plug” limitation and the “connected … through the via plug” relationship. Accordingly, Applicant’s TSV-versus-switch argument does not rebut the applied combination.
Applicant argues there is no motivation to combine and that the Office relies on hindsight; and applicant further argues the proposed modification undermines array regularity/uniformity and complicates connectivity control. The rejection expressly provides a rationale for combining Kurokawa with Bae: a person of ordinary skill in the art would have been motivated to modify Kurokawa with Bae to improve the system so as to determine the presence or absence of short-circuiting of the semiconductor substrate located in the vicinity of the TSV (see Bae col. 2:2–5 as cited in the rejection). Applicant’s generalized assertions regarding “uniformity,” “regularity,” and “complication” are conclusory and do not identify a teaching away in the applied references, nor do they show the proposed combination would change Kurokawa’s principle of operation or render the system inoperable. Therefore, the rejection is maintained.
Applicant asserts that neither Kurokawa nor Cruz-Albrecht, alone or in combination, discloses or suggests “a structure difference” between a first semiconductor component and a second semiconductor component, and further that the Office has not shown that the recited “structure difference comprises at least one of … difference of connection of via plug …” (and the other enumerated alternatives).
This argument is not persuasive because Cruz-Albrecht expressly discloses a memristor array including a plurality of memristors arranged with nanowires, and further discloses row vias and column vias that interface the nanowires to row/column circuitry—i.e., some array components are connected to vias while other array components (e.g., the memristor devices at nanowire intersections) are not themselves connected to vias. Specifically, Cruz-Albrecht teaches that the symbolic diagram of the memristor array (FIG. 5A) “shows 128 memristors … with nanowires … arranged in 16 rows and 8 columns,” and that “there are 16 row vias 62 and 8 column vias 63 to interface the nanowires … to a row circuit … and a column circuit … respectively.” (Cruz-Albrecht, ¶0046; FIG. 5A). This disclosure supports the limitation that a structure difference exists between a first semiconductor component and a second semiconductor component and that the structure difference comprises at least one of the enumerated alternatives, including a “difference of connection of via plug.” (Cruz-Albrecht, ¶0046; FIG. 5A). Accordingly, Cruz-Albrecht teaches the claimed “structure difference” (at least via-connection difference) as recited in claim 15. (Cruz-Albrecht, ¶0046; FIG. 5A).
Applicant’s contention that Cruz-Albrecht shows only a standard array and therefore cannot evidence a “structure difference” between semiconductor components is not persuasive. The claim’s “structure difference” expressly includes a “difference of connection of via plug,” and Cruz-Albrecht explicitly discloses row vias and column vias interfacing array wiring (nanowires) to circuitry, which necessarily distinguishes via-connected array components from non-via-connected array components within the same neural array. (Cruz-Albrecht, ¶0046; FIG. 5A).
Applicant’s assertions of no motivation and hindsight are not persuasive. The rejection sets forth that a person of ordinary skill in the art would have been motivated to modify Kurokawa with Cruz-Albrecht to improve Kurokawa with improved neural circuits and synapses with spiking timing dependent plasticity. (Cruz-Albrecht, ¶0011). This is an articulated rationale grounded in the applied reference.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-9, 11-12, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent 10,650,766 (Kurokawa et al; Kurokawa) in view of US Patent 9,318,393 (Bae).
Regarding claim 1:
Kurokawa teaches:
A neural circuit, comprising: and a neural array, comprising a plurality of semiconductor components, wherein each of the semiconductor components stores a weighting value and the semiconductor components are divided into a plurality of neural sub-groups,
(Kurokawa, col. 34:37-44)
“As the switch SW illustrated in FIG. 25B, a transistor, a diode, or a switch formed using a MEMS (microelectromechanical system) technology, such as a digital micromirror device (DMD), can be used, for example [i.e. a neural array, comprising a plurality of semiconductor components,]. Alternatively, the switch SW may be a logic circuit in which transistors are combined. In the case where one transistor is used as the switch SW, an OS transistor characterized by extremely low off-state current is preferably used [i.e. A neural circuit, comprising:].”
(Kurokawa, col. 35: 57-67)
“The plurality of signals input to the first terminals of the programmable logic elements PLE[1] to PLE[m] are subjected to arithmetic processing by the product-sum operation circuit and the activation function circuit of each programmable logic element [i.e. wherein each of the semiconductor components stores a weighting value]
wherein each of the neural sub-groups is configured to receive a plurality of input signals and generate an output current at an output terminal among a plurality of output terminals, and a computing result is calculated based on the output current,
(Kurokawa, col. 35:50-53)
“Signals input from the input layer to the first intermediate layer [i.e. and the semiconductor components are divided into a plurality of neural sub-groups] correspond to signals input from the input terminals PDL[1] to PDL[l]. A signal input from the input terminal PDL[i] is transmitted to each of the wirings Q[1] to Q[m] through the wiring L[i] [i.e. wherein each of the neural sub-groups is configured to receive a plurality of input signals and generate an output current].
(Kurokawa, col. 30: 57-67; col. 31: 1-2, Fig. 23)
“Note that FIG. 23 illustrates only the input terminal PDL[1], the input terminal PDL[2], the input terminal PDL[l], the output terminal PDR[1], the output terminal PDR[2], the output terminal PDR[n] [i.e. generate an output current at an output terminal among a plurality of output terminals,], the programmable logic element PLE[1], the programmable logic element PLE[2], the programmable logic element PLE[m], the wiring L[1], the wiring L[2], the wiring L[l], the wiring P[1], the wiring P[2], the wiring P[m], the wiring R[1], the wiring R[2], the wiring R[m], the wiring Q[1], the wiring Q[2], the wiring Q[m], the programmable switches PSW1 to PSW3, and later-described switch circuits SWC in the NN circuit 100, and the other circuits, elements, wirings, and reference numerals thereof are not shown .”
(Kurokawa, col. 36:1-5)
“The output result of the activation function operation is retained by the retention circuit KC illustrated in FIGS. 24A and 24B. Note that the data retention by the retention circuit KC is performed when the potential of the clock signal CLK changes from a low-level potential to a high-level potential [i.e. and a computing result is calculated based on the output current,]l.”
wherein the semiconductor components in the neural array comprises a first semiconductor component and a second semiconductor component,
(Kurokawa, col. 30: 57-61)
“Note that FIG. 23 illustrates only the input terminal PDL[1], the input terminal PDL[2], the input terminal PDL[l], the output terminal PDR[1], the output terminal PDR[2], the output terminal PDR[n], the programmable logic element PLE[1] [i.e. wherein the semiconductor components in the neural array comprises a first semiconductor component and a second semiconductor component,]…”
the second semiconductor component in the neural array is not connected to any via plug, any output terminal among the output terminals through any via plug, such that the computing result is not influenced by the second semiconductor component due to lack of said any via plug, and the first semiconductor component connected to the via plug and the second semiconductor component not connected to said any via plug are arranged as array in the neural array.
(Kurokawa, col. 30: 57-67; col. 31: 1-2, Fig. 23)
“Note that FIG. 23 illustrates only the input terminal PDL[1], the input terminal PDL[2], the input terminal PDL[l], the output terminal PDR[1], the output terminal PDR[2], the output terminal PDR[n], the programmable logic element PLE[1], the programmable logic element PLE[2], the programmable logic element PLE[m], the wiring L[1], the wiring L[2], the wiring L[l], the wiring P[1], the wiring P[2], the wiring P[m], the wiring R[1], the wiring R[2], the wiring R[m], the wiring Q[1], the wiring Q[2], the wiring Q[m], the programmable switches PSW1 to PSW3, and later-described switch circuits SWC in the NN circuit 100, and the other circuits, elements, wirings, and reference numerals thereof are not shown .”
Bae teaches:
a via plug;
(Bae, col. 1:65-67; col. 2: 1-2).
“In accordance with another aspect of the embodiment, a semiconductor device includes: a logic unit formed over a semiconductor substrate so as to perform a memory operation; a through silicon via (TSV) [i.e. a via plug] formed to pass through the semiconductor substrate;”
the first semiconductor component in the neural array is connected to a first output terminal among the output terminals through the via plug, and the first semiconductor component is configured to reflect, through the via plug, a weighting value provided by the first semiconductor component into the computing result,
(Bae, col. 2: 41-46)
“When a voltage lower than the power supply voltage is applied to the first metal contact, copper (Cu) ions migrated from the TSV are collected at a lower part of the first metal contact [i.e. the first semiconductor component in the neural array is connected to the via plug is connected to a first output terminal among the output terminals] such that a bridge is formed between the first metal contact and the first connection structure or between the first metal contact and the second connection structure [i.e. and the first semiconductor component is configured to reflect, through the via plug, a weighting value provided by the first semiconductor component into the computing result,].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated to modify Kurokawa with Bae. The motivation is to improve the system “so as to determine the presence or absence of short-circuiting of the semiconductor substrate located in the vicinity of the TSV (Bae, col. 2:2-5).”
Regarding claim 2:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein the weighting value of each of the semiconductor components corresponds to at least one of a gate width-to-length ratio and a threshold voltage of each of the semiconductor components.
(Kurokawa, col. 75: 36-42)
“The conductor 404 can function as a top gate, and the conductor 310 can function as a back gate [i.e. wherein the weighting value of each of the semiconductor components corresponds to at least one of a gate width-to-length ratio]. The potential of the back gate can be the same as the potential of the top gate, the ground potential, or given potential. By changing the potential of the back gate independently of the potential of the top gate, the threshold voltage of the transistor can be changed [i.e. and a threshold voltage of each of the semiconductor components].”
Examiner notes that back gates and top gates will have a width-to-length ratio, being physical objects.
Regarding claim 3:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein each of the semiconductor components has a first terminal, a second terminal, and a control terminal, the first terminal is coupled to the output terminal, the second terminal is coupled to a first reference voltage, and the control terminal receives one of the input signals.
(Kurokawa, col. 41:21-30)
“In the column output circuit OUT[j], a first terminal of the transistor Tr1 [i.e. wherein each of the semiconductor components has a first terminal] is electrically connected to the wiring OL[j], a second terminal [i.e. a second terminal ] of the transistor Tr1 is electrically connected to the wiring VSSL, and a gate of the transistor Tr1 [i.e. and the control terminal receives one of the input signals] is electrically connected to a first terminal of the capacitor C1 [i.e. the first terminal is coupled to the output terminal,]. A first terminal of a transistor Tr2 is electrically connected to the wiring OL[j], a second terminal of the transistor Tr2 is electrically connected to the first terminal of the capacitor C1, and a gate of the transistor Tr2 is electrically connected to the wiring OSP.”
Examiner notes that a gate is analogous to the term control terminal.
One of ordinary skill in the art, at the time the invention was filed , would have been motivated to modify Kurokawa with Bae. The motivation is the same as claim 1.
Regarding claim 4:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein each of the semiconductor components has a first terminal, a second terminal, and a control terminal, the first terminal is coupled to the output terminal, the second terminal receives a weighting adjustment signal, and the control terminal receives one of the input signals.
(Kurokawa, col. 35:44-49)
“In addition, configuration data for the programmable logic elements PLE[1] to PLE[m] are set so that a weight coefficient for each neuron of the g-th intermediate layer with respect to an output signal of a neuron of the (g−1)-th intermediate layer is set in each of the programmable logic elements PLE[1] to PLE[m] [i.e. the second terminal receives a weighting adjustment signal].”
(Kurokawa, col. 36:26-36)
“The results are output from the second terminals of the programmable logic elements PLE[1] to PLE[m] when the potential of the clock signal CLK for the retention circuit KC changes from the high-level potential to the low-level potential. The result output from the second terminal of the programmable logic element PLE[j] is transmitted to each of the wirings Q[1] to Q[m] through the wiring P[j]. The signal transmitted to the wiring Q[j] is input to the first terminal of the programmable logic element PLE[j] [i.e. the first terminal is coupled to the output terminal,].”
One of ordinary skill in the art, at the time the invention was filed , would have been motivated to modify Kurokawa with Bae. The motivation is the same as claim 1.
Regarding claim 5:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein each of the semiconductor components has a first terminal, a second terminal, and a control terminal, the first terminal receives one of the input signals, the second terminal is coupled to the output terminal, and the control terminal receives a weighting adjustment signal.
(Kurokawa, col. 31:49-60)
“The input terminal In[h] (here, h is an integer greater than or equal to 1 and less than or equal to s) is electrically connected to an input terminal of the multiplier circuit MLT[h], and an output terminal of the multiplier circuit MLT[h] is electrically connected to an input terminal of the adder circuit AD. An output terminal of the adder circuit AD is electrically connected to an input terminal of the activation function circuit FC. An output terminal of the activation function circuit FC is electrically connected to a terminal TA1 [i.e. wherein each of the semiconductor components has a first terminal] of the retention circuit KC. A terminal TA2 of the retention circuit KC is electrically connected to the output terminal OUT [i.e. the second terminal is coupled to the output terminal,].”
(Kurokawa, col. 31:60-65)
“The multiplier circuit MLT[h] performs multiplication using data retained in the configuration memory CMW[h] (such data is hereinafter referred to as a weight coefficient) as a multiplier and an input signal input to the input terminal In[h] as a multiplicand [i.e. receives a weighting adjustment signal].”
One of ordinary skill in the art, at the time the invention was filed , would have been motivated to modify Kurokawa with Bae. The motivation is the same as claim 1.
Regarding claim 7:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein each of the semiconductor components has a first terminal, a second terminal, and a control terminal, the first terminal receives a weighting adjustment signal, the second terminal is coupled to the output terminal, and the control terminal receives one of the input signals.
(Kurokawa, col. 32:10-16)
“The retention circuit KC has a function of obtaining an operation result output from the activation function circuit FC through the terminal TA1 [i.e. wherein each of the semiconductor components has a first terminal, a second terminal, and a control terminal], and temporarily retaining the operation result [i.e. the first terminal receives a weighting adjustment signal] and a function of outputting the temporarily retained operation result to the terminal TA2 [i.e. the second terminal is coupled to the output terminal,]. In addition, the retention circuit KC can switch the above-described two functions in accordance with a clock signal CLK input through a terminal CKT [i.e. and the control terminal receives one of the input signals].”
One of ordinary skill in the art, at the time the invention was filed , would have been motivated to modify Kurokawa with Bae. The motivation is the same as claim 1.
Regarding claim 8:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein each of the first semiconductor components comprises a first terminal, and the weighting value of each of the semiconductor components is adjusted [through a via plug connected onto the first terminal].
(Kurokawa, col. 40: 58-64)
“The offset circuit 711 [i.e. wherein each of the semiconductor components comprises a first terminal,] is electrically connected to a wiring VDDL and a wiring VSSL for supplying power supply voltages. Specifically, each of the column output circuits OUT[1] to OUT[n] is electrically connected to the wiring VDDL and the wiring VSSL, and the reference column output circuit Cref is electrically connected to the wiring VDDL [i.e. and the weighting value of each of the semiconductor components is adjusted].”
Examiner notes that the weighting value is referred to in one example as adjusting the voltage in the specification.
Bae teaches:
1. [wherein each of the first semiconductor components comprises a first terminal, and the weighting value of each of the semiconductor components is adjusted] through a via plug connected onto the first terminal.
(Bae, col. 2: 41-46)
“When a voltage lower than the power supply voltage is applied to the first metal contact, copper (Cu) ions migrated from the TSV are collected at a lower part of the first metal contact, such that a bridge is formed between the first metal contact and the first connection structure or between the first metal contact and the second connection structure.”
One of ordinary skill in the art, at the time the invention was filed , would have been motivated to modify Kurokawa with Bae. The motivation is the same as claim 1.
Regarding claim 9:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein each of the first semiconductor components comprises a control terminal, [and the via plug is connected onto the control terminal].
(Kurokawa, col. 40: 58-64)
“The offset circuit 711 [i.e. wherein each of the semiconductor components comprises a control terminal,] is electrically connected to a wiring VDDL and a wiring VSSL for supplying power supply voltages. Specifically, each of the column output circuits OUT[1] to OUT[n] is electrically connected to the wiring VDDL and the wiring VSSL, and the reference column output circuit Cref is electrically connected to the wiring VDDL.”
Bae teaches:
1. [wherein each of the first semiconductor components comprises a control terminal,] and the via plug is connected onto the control terminal.
(Bae, col. 2: 41-46)
“When a voltage lower than the power supply voltage is applied to the first metal contact, copper (Cu) ions migrated from the TSV are collected at a lower part of the first metal contact, such that a bridge is formed between the first metal contact and the first connection structure or between the first metal contact and the second connection structure.”
One of ordinary skill in the art, at the time the invention was filed , would have been motivated to modify Kurokawa with Bae. The motivation is the same as claim 1.
Examiner notes that the difference between the first terminal and the control terminal for the purposes of generating voltage appears to be negligible
Regarding claim 11:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein the output terminal has at least one metal layer, and the weighting value of each of the semiconductor components in the neural sub- groups is adjusted through the at least one metal layer.
(Kurokawa, col. 75: 5-9)
“In the following description, the metal oxide 406a and the metal oxide 406b are collectively referred to as the metal oxide 406 in some cases. Although the metal oxide 406a and the metal oxide 406b are stacked in the transistor 200, the structure of the present invention is not limited to this structure [i.e. wherein the output terminal has at least one metal layer].”
(Kurokawa, col. 78: 7-13)
“Here, the conduction band minimum gradually changes in the metal oxides 406a and 406b [i.e. and the weighting value of each of the semiconductor components in the neural sub- groups]. In other words, the conduction band minimum continuously changes or is continuously connected. To obtain such an energy level, the density of defect states in a mixed layer formed at an interface between the metal oxides 406a and 406b is preferably made low [i.e. is adjusted through the at least one metal layer].”
One of ordinary skill in the art, at the time the invention was filed , would have been motivated to modify Kurokawa with Bae. The motivation is the same as claim 1.
Regarding claim 12:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein each of the semiconductor components comprises at least one parallel-connected sub-semiconductor element, and the weighting value of each of the semiconductor components is adjusted through a number of the at least one parallel- connected sub-semiconductor element.
(Kurokawa, col. 61:20-30)
“In that case, a filter value of a weight filter is stored as the first analog data in each of the memory cells AM, and image data is supplied as the second analog data to each of the wirings RW, whereby the product-sum operation of the convolutional operation in a CNN can be performed. In the case where a plurality of weight filters are used for the convolutional operation, filter values of the filters are stored in the memory cells AM in the respective columns [i.e. and the weighting value of each of the semiconductor components is adjusted through a number of the at least one parallel- connected sub-semiconductor element]. Accordingly, a plurality of filter operations can be performed in parallel, and feature extraction can be performed at high speed [i.e. wherein each of the semiconductor components comprises at least one parallel-connected sub-semiconductor element,].”
One of ordinary skill in the art, at the time the invention was filed , would have been motivated to modify Kurokawa with Bae. The motivation is the same as claim 1.
Regarding claim 13:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein the first terminal of the first semiconductor component is a drain terminal of the first semiconductor component.
(Kurokawa, col. 96: 43-49)
“In this specification, a transistor is an element having at least three terminals of a gate, a drain, and a source. The transistor includes a channel formation region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode) and current can flow between the source and the drain through the channel formation region.”
One of ordinary skill in the art, at the time the invention was filed , would have been motivated to modify Kurokawa with Bae. The motivation is the same as claim 1.
Regarding claim 14:
Kurokawa and Bae teach the system of claim 1.
Kurokawa teaches:
1. wherein the control terminal of the first semiconductor component is a gate terminal of the first semiconductor component.
(Kurokawa, col. 96: 43-49)
“In this specification, a transistor is an element having at least three terminals of a gate, a drain, and a source. The transistor includes a channel formation region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode) and current can flow between the source and the drain through the channel formation region.”
One of ordinary skill in the art, at the time the invention was filed , would have been motivated to modify Kurokawa with Bae. The motivation is the same as claim 1.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent 10,650,766 (Kurokawa et al; Kurokawa), further in view of US Pre-Grant Patent 2016/0364643 (Cruz-Albrecht et al; Cruz-Albrecht).
Regarding claim 15:
Kurokawa teaches:
1. A neural circuit, comprising: a neural array, comprising a plurality of semiconductor components, wherein each of the semiconductor components stores a weighting value, and the semiconductor components are divided into a plurality of neural sub-groups,
(Kurokawa, col. 34:37-44)
“As the switch SW illustrated in FIG. 25B, a transistor, a diode, or a switch formed using a MEMS (microelectromechanical system) technology, such as a digital micromirror device (DMD), can be used, for example [i.e. A neural circuit, comprising: a neural array, comprising a plurality of semiconductor components,]. Alternatively, the switch SW may be a logic circuit in which transistors are combined. In the case where one transistor is used as the switch SW, an OS transistor characterized by extremely low off-state current is preferably used [i.e. A neural circuit, comprising:].”
(Kurokawa, col. 35: 57-67)
“The plurality of signals input to the first terminals of the programmable logic elements PLE[1] to PLE[m] are subjected to arithmetic processing by the product-sum operation circuit and the activation function circuit of each programmable logic element [i.e. wherein each of the semiconductor components stores a weighting value]
2. and the semiconductor components are divided into a plurality of neural sub-groups, wherein each of the neural sub-groups is configured to receive a plurality of input signals and generate an output current, and a computing result is calculated based on the output current
(Kurokawa, col. 35:50-53)
“Signals input from the input layer to the first intermediate layer [i.e. and the semiconductor components are divided into a plurality of neural sub-groups] correspond to signals input from the input terminals PDL[1] to PDL[l]. A signal input from the input terminal PDL[i] is transmitted to each of the wirings Q[1] to Q[m] through the wiring L[i] [i.e. wherein each of the neural sub-groups is configured to receive a plurality of input signals and generate an output current].
(Kurokawa, col. 36:1-5)
“The output result of the activation function operation is retained by the retention circuit KC illustrated in FIGS. 24A and 24B. Note that the data retention by the retention circuit KC is performed when the potential of the clock signal CLK changes from a low-level potential to a high-level potential [i.e. and a computing result is calculated based on the output current,].”
3. wherein the semiconductor components in the neural array comprises a first semiconductor component and a second semiconductor component,
(Kurokawa, col. 30: 57-61)
“Note that FIG. 23 illustrates only the input terminal PDL[1], the input terminal PDL[2], the input terminal PDL[l], the output terminal PDR[1], the output terminal PDR[2], the output terminal PDR[n], the programmable logic element PLE[1] [i.e. comprises a first semiconductor component and a second semiconductor component,,]…”
Kurokawa does not explicitly teach:
1. a structure difference exists between the first semiconductor component and the second semiconductor component,
2. and the structure difference comprises at least one of difference of gate width-to-length ratio, difference of connection of diffusion layer, difference of thickness of connected metal layer and difference of configuration of parallel-connected sub-semiconductor elements.
Cruz-Albrecht teaches:
1. a structure difference exists between the first semiconductor component and the second semiconductor component,
(Cruz-Albrecht, ¶0046, Fig. 5A)
“The memristor array 34 of each node 12 interfaces to circuitry, which may be CMOS, to select a memristor 35 for a read or write operation. A symbolic diagram of the memristor array 34 is shown in FIG. 5A, and shows 128 memristors 35 with nanowires 60 and 61 arranged in 16 rows and 8 columns, respectively. In this embodiment there are 16 row vias 62 and 8 column vias 63 to interface the nanowires 60 and 61 to a row circuit 64 and a column circuit 66, respectively [i.e. a structure difference exists between the first semiconductor component and the second semiconductor component,].”
2. and the structure difference comprises at least one of difference of gate width-to-length ratio, difference of connection of via plug, difference of connection of diffusion layer, difference of thickness of connected mental layer and difference of configuration of parallel-connected sub-semiconductor elements.
(Cruz-Albrecht, ¶0046, Fig. 5A)
“The memristor array 34 of each node 12 interfaces to circuitry, which may be CMOS, to select a memristor 35 for a read or write operation. A symbolic diagram of the memristor array 34 is shown in FIG. 5A, and shows 128 memristors 35 with nanowires 60 and 61 arranged in 16 rows and 8 columns, respectively. In this embodiment there are 16 row vias 62 and 8 column vias 63 to interface the nanowires 60 and 61 to a row circuit 64 and a column circuit 66, respectively [i.e. and the structure difference comprises at least one of… difference of connection of via plug].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated to modify Kurokawa with Cruz-Albrecht. The motivation is to improve Kurokawa with “improved neural circuits and synapses with spiking timing dependent plasticity (Cruz-Albrecht, ¶0011).”
Regarding claim 16:
Kurokawa and Cruz-Albrecht teach the system of claim 15.
Cruz-Albrecht teaches:
1. wherein the structure difference existed between the first semiconductor component and the second semiconductor component causes a difference of weighting values provided by the first semiconductor component and the second semiconductor component, respectively.
(Cruz-Albrecht, ¶0046)
“In addition in each time slot 58 the stored synaptic weight value in each memristor 35 in the memristor array 34 may be updated according to a update value provided by the STDP circuit 26 [i.e. wherein the structure difference existed between the first semiconductor component and the second semiconductor component causes a difference of weighting values]. The update value is used to increment or decrement the currently stored synaptic conductance value in the memristor 35 for the virtual synapse [i.e. provided by the first semiconductor component and the second semiconductor component, respectively].”
One of ordinary skill in the art, at the time the invention was filed, would have been motivated to modify Kurokawa with Cruz-Albrecht. The motivation is the same as claim 15.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL JUSTIN BREENE whose telephone number is (571)272-6320. Examiner
interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-
based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO
Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael J Huntley can be reached on 303-297-4307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786 9199 (IN USA OR CANADA) or 571-272-1000.
/P.J.B./ Examiner, Art Unit 2129
/MICHAEL J HUNTLEY/Supervisory Patent Examiner, Art Unit 2129