DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The Amendment filed on 12/18/25, responding to the Office action mailed on 09/24/25, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this office action are claims 1, 2, 7-23 and 25, with claims 12-23 and 25 stand withdrawn.
Election/Restrictions
In response to the request to rejoin withdrawn claims 13-23 and 25 based on amendments, the request is hereby granted for claims 13, 17, 18, 21-23, and 25; and the claims are rejoined for examination in the instant Office action in view of the amendment reading on the elected specie. The rejoin request is denied for claims 14-16, 19, and 20 as they read on non-elected species; and these claims stands withdrawn.
Claim Objections
Claims 1, 13, and 23 are objected to because of the following informalities.
Claim 1 recites limitation “wherein the array of die stacks are between the first die and the package substrate”; this is grammatically incorrect as “the array of die stacks” should be singular to refer to the array. It is recommended that the limitation to be amended as --wherein the array of die stacks is between the first die and the package substrate--.
Claim 11 recites limitation “between the array of die stacks”, this creates confusion in claim interpretation. The recommended claim language is --between the
Claims 1, 13, and 23 recites limitation “the electrical contacts outside of the footprint of the first die”, which is missing the necessary verb in the sentence. It is recommended that the limitation to be amended as --the electrical contacts are positioned outside of the footprint of the first die—to clarify the claim scope.
The recommended claim languages will be used for examination in the instant Office action for the purpose of compact prosecution. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 recites the limitation "the plurality of die stacks" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, the limitation is interpreted as “the
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 10, 11, 13, 17, 18, 21-23, and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sutardja et al. (US 20140106508, Sutardja hereinafter).
As to claim 1, Sutardja teaches an electronic package (Fig. 3B), comprising:
a package substrate (see annotation below);
a first die (308) electrically coupled to the package substrate;
an array of die stacks (see annotated figure below) electrically coupled to the first die, wherein the array of die stacks is between the first die and the package substrate, wherein the array of die stacks is entirely within a footprint of the first die, wherein the first die extends laterally beyond the array of die stacks, and wherein individual ones of the array of die stacks comprise a plurality of second dies (304b and 304d) arranged in a vertical stack; and
a base substrate (see annotation below), wherein the base substrate is between the array of die stacks and the first die, wherein the base substrate is electrically coupled to the package substrate by electrical contacts (328), the electrical contacts are positioned outside of the footprint of the first die, and the electrical contacts extending from a top of the array of die stacks to a bottom of the array of die stacks, and wherein each die stack of the array of die stacks is directly electrically connected to both the base substrate and the package substrate by interconnects (326 and 330).
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As to claim 2, Sutardja teaches an electronic package of claim 1, wherein the first die is a compute die (i.e. processor [0004] and [0033]), and wherein the plurality of second dies are memory dies ([0027]).
As to claim 10, Sutardja teaches an electronic package of claim 1, wherein a power delivery path (i.e., via 322a, see Fig. 3B) from the package substrate to the first die passes through one or more of the plurality of second dies.
As to claim 11, Sutardja teaches an electronic package of claim 1, wherein a power delivery path (i.e., via 328 positioned in the middle of the die, see Fig. 3B) from the package substrate to the first die passes between the
As to claim 13, Sutardja teaches an electronic package (see Fig. 3B), comprising:
a package substrate (see annotated drawing above);
a base substrate (see annotated drawing above) over the package substrate;
an array of die stacks (see annotated figure above) over the base substrate, wherein each die stack of the array of die stacks is directly electrically connected to both the base substrate and the package substrate by interconnects (326 and 330); and
a first die (308) over the array of die stacks, wherein the array of die stacks is entirely within a footprint of the first die, and wherein the first die extends laterally beyond the array of die stacks, and wherein the base substrate is electrically coupled to the package substrate by electrical contacts (328), the electrical contacts are positioned outside of the footprint of the first die, and the electrical contacts extending from a top of the array of die stacks to a bottom of the array of die stacks.
As to claim 17, Sutardja teaches an electronic package of claim 13, wherein a power delivery path (i.e., via middle 328, see Fig. 3B) from the package substrate to the first die passes through the
As to claim 18, Sutardja teaches an electronic package of claim 13, wherein a power delivery path (i.e., via middle 328, see Fig. 3B) from the package substrate to the first die passes between die stacks.
As to claim 21, Sutardja teaches an electronic package of claim 13, wherein individual die stacks comprise two or more second dies (304b and 304d) arranged in a vertical stack.
As to claim 22, Sutardja teaches an electronic package of claim 21, wherein the first die is a compute die (i.e. processor [0004] and [0033]), and wherein the second dies are memory dies ([0027]).
As to claim 23, Sutardja teaches an electronic system (see Fig. 3B) comprising:
a board (i.e., printed circuit board [0051]);
a package substrate (see annotated figure above) attached to the board;
a first die (308) electrically coupled to the package substrate; and
an array of die stacks (see annotated figure above) electrically coupled to the first die, wherein the array of die stacks is entirely within a footprint of the first die, wherein the first die extends laterally beyond the array of die stacks, and wherein individual ones of the die stacks comprise a plurality of second dies (304b and 304d) arranged in a vertical stack; and
a base substrate (see annotated figure above), wherein the base substrate is between the array of die stacks and the first die, wherein the base substrate is electrically coupled to the package substrate by electrical contacts (328), the electrical contacts are positioned outside of the footprint of the first die, and the electrical contacts extending from a top of the array of die stacks to a bottom of the array of die stacks, and wherein each die stack of the array of die stacks is directly electrically connected to both the base substrate and the package substrate by interconnects (326 and 330).
As to claim 25, Sutardja teaches an electronic system of claim 23, wherein a power delivery path (i.e., via middle 328 or 322a, see Fig. 3B) from the package substrate to the first die passes between die stacks or passes through the die stacks.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Sutardja in view of Bae et al. (US 2019/0221527 and Bae hereinafter).
As to claims 7-9, Sutardja teaches the electronic package of claim 1, but does not teach the base substrate is a passive or an active substrate for power delivery. Sutardja’s base substate is of a redistribution platform with routing of conductive paths.
Bae teaches a redistribution platform 106 that can provide circuits, either passive and active circuit through the formation of various linear and non-linear structures (see [0082]).
Since Sutardja and Bae are in the similar field of endeavor of electronic devices, a person having ordinary skill in the art at the time of invention would have readily recognized the desirability and advantages of modifying Sutardja, as suggested by Bae, by employing redistribution platform with passive or active circuitry for power delivery as the base substrate. It is conventional to have passive or active circuitry in the redistribution layer in order to apply and/or transmit electric signals to/from dies within the electronic device. Bae's redistribution platform would have performed the same functions as in the combination, and no unexpected results would have arisen from the combination. All the claim elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1395 (Supreme Court 2007) (KSR).
Response to Arguments
Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eva Yan Montalvo whose telephone number is (571)270-3829. The examiner can normally be reached M-TH 9AM-7PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Fristoe can be reached at (571) 272-4926. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818
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