Prosecution Insights
Last updated: May 29, 2026
Application No. 16/920,107

NETWORK SWITCHING WITH CO-RESIDENT DATA-PLANE AND NETWORK INTERFACE CONTROLLERS

Non-Final OA §103
Filed
Jul 02, 2020
Priority
Sep 16, 2018 — divisional of 11/509,750
Examiner
LAM, YEE F
Art Unit
2465
Tech Center
2400 — Computer Networks
Assignee
Marvell Asia Pte. Ltd.
OA Round
9 (Non-Final)
77%
Grant Probability
Favorable
9-10
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
489 granted / 636 resolved
+18.9% vs TC avg
Strong +22% interview lift
Without
With
+21.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
33 currently pending
Career history
679
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
92.2%
+52.2% vs TC avg
§102
1.7%
-38.3% vs TC avg
§112
5.1%
-34.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 636 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-3, and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Shuichi Karino (US 20110320632 A1, hereinafter Karino), in view of Ronciak et al. (US 20060067349 A1, hereinafter Ronciak). Regarding claim 1, Karino teaches a method for network switching with co-resident data-plane processors and network interface controller, comprising (in general, see fig. 9 along with fig. 10-11 and their respective paragraphs including but not limited to 67-80): receiving a description of an outgoing packet at an internal facing interface of a network interface controller portion of a network interface resource implemented on a chip (Karino, see at least fig. 9 and para. 71-74 in view of para. 49, for one unlimited example, “…In this processing example, a transmission packet transmitted from the virtual machine 300 is firstly inputted to the network adaptor 100… If the transmission packet belongs to the flow “flow1” or “flow2”, an exact match entry is hit in the transmission filter table FILT2. Accordingly, the transmission filter 120 transmits the transmission packet to the data link…”), the network interface resource comprising: a data-plane packet input processor, a data-plane packet output processor, and the network interface controller (Karino, see at least fig. 9 in view of fig. 6, for one unlimited example, “…FIG. 6 is a block diagram showing an exemplary overall configuration of the network adaptor 100 according to this embodiment. The network adaptor 100 includes virtual NICs (indicated with dashed line frames in FIG. 6), a reception filter 110, a transmission filter 120…”; note that this interpretation merely an example, since fig. 5 could also be applied), providing the outgoing packet processed by the network interface controller to the data-plane packet input processor (Karino, see at least para. 74, “…If the transmission packet belongs to a different flow, on the other hand, no exact match entry is hit in the transmission filter table FILT2. Accordingly, the transmission filter 120 loops back the transmission packet as a reception packet to the reception filter 110..”); determining by the data-plane packet input processor a target entity; and providing the outgoing packet to the target entity according to the determination (Karino, see at least para. 74 and 75, for one unlimited example “…the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, note that a target entity is interpreted to be a next destination of one or more packets to be sent, queued, stored, etc., in other words, it is also possible the next destination would be VM 300 when a match is made as shown in para. 75). Karino differs from the claim, in that, it does not specifically disclose the description including information for locating different parts of the outgoing packet in memory. Ronciak, from the similar field of endeavor, teaches the description including information for locating different parts of the outgoing packet in memory (Ronciak, see at least fig. 2 and para. 22-23, e.g. disclosing two embodiments in that one for ingress packets and another one for egress packets). Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak into the method of Karino for greatly reducing or eliminating the amount of run-time configuration performed. Regarding claim 2, Karino in view of Ronciak teaches providing the outgoing packet processed by the network interface controller to the data-plane packet input processor comprises: providing the outgoing packet processed by the network interface controller to the data-plane packet input processor via a loopback entity. (Karino, see at least para. 68 along with para. 74, e.g. for one example, but not limited to, “…The second transmitting action is to loop back transmission packets as reception packets to the reception filter 110 (that is, the reception route). In this case, the transmission filter 120 loops back transmission packets as reception packets to the reception filter 110…”) Regarding claim 3, Karino in view of Ronciak teaches providing the outgoing packet to the target entity according to the determination comprises: providing the outgoing packet to a packet handling entity; and processing the outgoing packet in accordance with a packet management policy at the packet handling entity. (Karino, see at least para. 71-74, “…The two route patterns will be described below with reference to FIG. 9 and FIG. 11…”; Ronciak, see at least para. 18, “…For example, a processor 104 can implement a policy for assigning flows to many different transmit queues…”). Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak into the method of Karino for greatly reducing or eliminating the amount of run-time configuration performed. Regarding claim 5, Karino in view of Ronciak teaches the processing the outgoing packet in accordance with the packet management policy at the packet handling entity comprises: providing the outgoing packet to a different destination than the target entity. (Karino, see at least para. 72-74, e.g. disclosing two embodiments in that one for transmitting packets and another one for receiving packets, note that the outgoing packet could thus become transmitting packets or receiving packets depending on situations). Regarding claim 6, Karino in view of Ronciak teaches the processing the outgoing packet in accordance with the packet management policy at the packet handling entity comprises: providing the processed outgoing packet to a network via the data-plane packet output processor. (Karino, see at least para. 72-74, e.g. disclosing two embodiments in that one for transmitting packets and another one for receiving packets, note that the outgoing packet could thus become transmitting packets or receiving packets depending on situations). Regarding claim 7, Karino in view of Ronciak teaches providing the outgoing packet to the target entity according to the determination comprises: providing the outgoing packet processed by the data-plane packet input processor to a storage (Karino, see at least para. 74 and 75, “…Accordingly, the transmission filter 120 loops back the transmission packet as a reception packet to the reception filter 110. No exact match entry is hit also in the reception filter table FILT1. Hence, the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, as well as “…If the reception packet belongs to the flow “flow1” or “flow2”, an exact match entry is hit in the reception filter table FILT1. Accordingly, the reception filter 110 stores the reception packet in the reception queue 101 associated with to the corresponding virtual machine 300…”); requesting the outgoing packet by the target entity (Karino, see at least para. 127-128, for an unlimited example, “…The virtual switch packet transmission/reception function 320 stores the received transmission packets in the buffer and requests the hypervisor 50 to transfer the packets…”); and processing the outgoing packet by a packet handling entity in accordance with a packet management policy (Karino, see at least para. 71-74, “…The two route patterns will be described below with reference to FIG. 9 and FIG. 11…”; Ronciak, see at least para. 18, “…For example, a processor 104 can implement a policy for assigning flows to many different transmit queues…”). Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak into the method of Karino for greatly reducing or eliminating the amount of run-time configuration performed. Regarding claim 8, Karino in view of Ronciak teaches the processing the outgoing packet by the packet handling entity in accordance with the packet management policy comprises: providing the processed outgoing packet to the target entity. (Karino, see at least para. 74 and 75, for one unlimited example “…the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, note that a target entity is interpreted to be a next destination of one or more packets to be sent, queued, stored, etc., in other words, it is also possible the next destination would be VM 300 when a match is made as shown in para. 75). Regarding claim 9, Karino in view of Ronciak teaches the processing the outgoing packet by the packet handling entity in accordance with the packet management policy comprises: providing the outgoing packet to a different destination than the target entity. (Karino, see at least para. 74 and 75, for one unlimited example “…the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, note that a target entity is interpreted to be a next destination of one or more packets to be sent, queued, stored, etc., in other words, it is also possible the next destination would be VM 300 when a match is made as shown in para. 75). Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Karino in view of Ronciak, as applied to claim 1 above, and further in view of Ronciak et al. (US 20060067228 A1, hereinafter Ronciak_28). Regarding claim 4, Karino in view of Ronciak teaches the processing the outgoing packet in accordance with the packet management policy at the packet handling entity. (Karino, see at least para. 71-74, “…The two route patterns will be described below with reference to FIG. 9 and FIG. 11…”; Ronciak, see at least para. 18, “…For example, a processor 104 can implement a policy for assigning flows to many different transmit queues…”) Karino in view of Ronciak differs from the claim, in that, it does not specifically disclose discarding the outgoing packet. Ronciak_28, for example, from the similar field of endeavor, teaches discarding the outgoing packet (Ronciak_28, see at least para. 20 along with fig. 3, e.g. ejecting or removing packets). Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak_28 into the method of Karino in view of Ronciak for effectively use of computing resources and packet processing time. Regarding claim 10, Karino in view of Ronciak and Ronciak_28 teaches the processing the outgoing packet by the packet handling entity in accordance with the packet management policy comprises: discarding the outgoing packet. (Karino, see at least para. 71-74; Ronciak, see at least para. 18; Ronciak_28, see at least para. 20 along with fig. 3, e.g. ejecting or removing packets). Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak_28 into the method of Karino in view of Ronciak for effectively use of computing resources and packet processing time. Response to Arguments Applicant's arguments filed 10/14/2025 have been fully considered but they are not persuasive. Examiner provides response in following sections. Regarding independent claim 1, applicant argues that (applicant’s emphasis included, if any): “Applicant respectfully submits that even if the references could be combined, which Applicant does not concede, the cited hypothetical combination does not disclose at least "a network interface resource implemented on a chip... the network interface resource comprising: a data-plane packet input processor, a data-plane packet output processor, and the network interface controller," as required by Applicant's independent Claim 1. At pages 3 and 4 of the Office Action, the Office cites Karino as purportedly disclosing same. Applicant respectfully disagrees. Specifically, at pages 3 and 4 of the Office Action, the Office cites FIG. 5, FIG. 6, and FIG. 9 of Karino and, while such figures may include components, such as a network adapter 100, virtual NICs (indicated with dashed lines), a reception filter 100, a transmission filter 120, etc., Applicant is unable to determine which elements of the cited figures the Office is interpreting as purportedly disclosing "a data-plane packet input processor, a data-plane packet output processor, and [a] network interface controller," much less "a network interface resource implemented on a chip" that comprises such elements, as required by Applicant's independent Claim 1. Applicant requests guidance to understand which components of Karino the Office is citing as purportedly disclosing the above-noted elements, as required (emphasis added) by 37 C.F.R.§ 1.104 (i.e., "[w]hen a reference is complex or shows or describes inventions other than that claimed by the applicant, the particular part relied on must be designated as nearly as practicable"). Applicant respectfully submits that the Office does not provide such designation because Karino does not disclose same.” (Remarks, page 2-3) Examiner respectfully disagrees. Karino in at least fig. 6 and fig. 9 disclose the argued features. For example, Karino in at least para. 53 of fig. 6 discloses an exemplary overall configuration of the network adaptor 100 comprising virtual NICs (indicated with dashed line frames in FIG. 6), reception filter 110, transmission filter 120, etc.. Fig. 9 of Karino gives a more detailed view of the network adaptor 100 which including FILT2 with the transmission filter 120 on the output side as well as FILT1 with the reception filter 110 on the input side. Hence, Karino indeed teaches or suggests the argued features of "a network interface resource implemented on a chip... the network interface resource comprising: a data-plane packet input processor, a data-plane packet output processor, and the network interface controller," as recited in claim 1. Further, applicant argues that (applicant’s emphasis included, if any): “In addition, the cited hypothetical combination does not disclose "providing the outgoing packet processed by the network interface controller to the data-plane packet input processor," as recited in Applicant's independent Claim 1. In the Office Action, the Office cites p0074 of Karino as purportedly disclosing same. Applicant respectfully disagrees. Cited p0074 of Karino is reproduced below for reference. If the transmission packet belongs to a different flow, on the other hand, no exact match entry is hit in the transmission filter table FILT2. Accordingly, the transmission filter 120 loops back the transmission packet as a reception packet to the reception filter 110. No exact match entry is hit also in the reception filter table FILT1. Hence, the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S. In other words, the packet is once inputted to the network adaptor 100 and then processed by the virtual switch 200. This corresponds to the second route pattern. See Karino, p0074. As should appreciated from the cited passage of Karino, namely p0074 reproduced above, the cited passage does not disclose "a data-plane packet input processor" and "network interface controller," much less "providing [an] outgoing packet processed by the network interface controller to the data-plane packet input processor," as recited in Applicant' s independent Claim 1. In contrast to the above-noted elements, the cited passage of Karino, reproduced above, describes that a transmission filter 120 loops back a transmission packet as a reception packet to a reception filter 110. Nowhere does Karino describe that a filter is a processor or that a filter is a network interface controller. As such, Karino's transmission filter 120 that loops back a transmission packet as a reception packet to a reception filter 110 does not disclose "providing [an] outgoing packet processed by the network interface controller to the data-plane packet input processor," as recited in Applicant's independent Claim 1. "All words in a claim must be considered in judging the patentability of that against the prior art." MPEP 2143.03 (emphasis added). Further, the cited passage of Karino, reproduced above, provides no teaching or suggestion of "[an] outgoing packet [that is] processed by [a] network interface controller," as required by Applicant's independent Claim 1. Rather, the cited passage, reproduced above, describes that "the packet is once inputted to the network adaptor 100 and then processed by the virtual switch 200." (Remarks, page 3-4) Examiner respectfully disagrees. Karino in at least para 74 discloses the transmission packet being loopback as a reception packet to the reception filter 110, and such transmission packet has been processed in one or more of transmission queue 102 (e.g. virtual NICs). Hence, Karino, alone or combined, indeed teaches or suggests the argued features of “...providing the outgoing packet processed by the network interface controller to the data-plane packet input processor...”, as recited in claim 1. Regarding claims 4 and 10, applicant argues that (applicant’s emphasis included, if any): “Even if the cited references could be combined, which Applicant does not concede, Ronciak_28 fails to at least remedy the above-mentioned deficiencies of Karino and Ronciak as set forth above with reference to Applicant's independent Claim 1, from which Claims 4 and 10 depend. Specifically, as should be appreciated from page 5 of the Office Action mailed from the U.S. Patent and Trademark Office on July 14, 2025 in the co-pending U.S. Application No.: 17/968,697, the Office correctly acknowledges that Ronciak_28 does not disclose "a network interface resource ... comprising: [a] data-plane packet input processor, a data-plane packet output processor, and[a] network interface controller," as recited in Applicant's independent Claim 1. As such, the cited hypothetical combination of Karino, Ronciak, and Ronciak_28 is missing at least the above-noted elements of independent Claim 1, as set forth above and, thus, the Office fails to establish a prima facie case of obviousness with respect to same.” (Remarks, page 4-5) Examiner respectfully disagrees. As stated in claim 1 response above, Karino (not Ronciak_28) indeed teaches or suggests the argued features of "a network interface resource implemented on a chip... the network interface resource comprising: a data-plane packet input processor, a data-plane packet output processor, and the network interface controller," as recited in claim 1. Hence, claims 4 and 10 rejections are maintained Accordingly, all pending dependent claims of the independent claim 1, in view of the response above, the examiner has maintained the rejection as presented and believes all rejections are proper and should be sustained. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEE F LAM whose telephone number is (571)270-7577. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ayman Abaza can be reached on 571-270-0422. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YEE F LAM/Primary Examiner, Art Unit 2465
Read full office action

Prosecution Timeline

Show 13 earlier events
Jun 11, 2025
Request for Continued Examination
Jun 16, 2025
Response after Non-Final Action
Jul 14, 2025
Non-Final Rejection mailed — §103
Oct 14, 2025
Response Filed
Nov 17, 2025
Final Rejection mailed — §103
Feb 17, 2026
Request for Continued Examination
Feb 26, 2026
Response after Non-Final Action
May 26, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

9-10
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+21.8%)
2y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 636 resolved cases by this examiner. Grant probability derived from career allowance rate.

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