DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
Claim 1 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1 and 3 of U.S. patent 10116772 B2 (hereinafter “patent 10116772”). Although the conflicting claims are not identical, they are not patentably distinct from each other because of the following:
Regarding claim 1, by omitting “…a network facing outgoing interface of the network interface controller is communicatively coupled to a network facing interface of the packet input processor via a second hardware loopback entity…", combination of claims 1 and 3 of patent 10116772 is directed to a same or substantially similar invention as claim 1 of the instant application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Shuichi Karino (US 20110320632 A1, hereinafter Karino), in view of Ronciak et al. (US 20060067349 A1, hereinafter Ronciak) and Ezekiel Kruglick (US 20160055041 A1, hereinafter Kruglick).
Regarding claim 1,
Karino teaches a method for network switching with co-resident data-plane processors and network interface controller, comprising (Karino, in general, see fig. 9 along with fig. 10-11 and their respective paragraphs including but not limited to 67-80):
receiving a description of an outgoing packet at an internal facing interface of a network interface controller portion of a network interface resource implemented as a physical entity on a single chip (Karino, see at least fig. 9 and para. 71-74 in view of para. 49, for one non-limited example, “…In this processing example, a transmission packet transmitted from the virtual machine 300 is firstly inputted to the network adaptor 100. At this time, the transmission packet is directly inputted to the network adaptor 100 by using the direct data transfer function 140 in the network adaptor 100 not through the virtual switch 200. The transmission filter 120 extracts the transmission packet from the selected transmission queue 102. If the transmission packet belongs to the flow “flow1” or “flow2”, an exact match entry is hit in the transmission filter table FILT2. Accordingly, the transmission filter 120 transmits the transmission packet to the data link…”, note that para. 49 discloses hardware network adaptor 100),
the network interface resource on the single chip comprising a data-plane packet input processor, a data-plane packet output processor, and the network interface controller (Karino, see at least fig. 9 in view of fig. 6 and para. 49, “…FIG. 6 is a block diagram showing an exemplary overall configuration of the network adaptor 100 according to this embodiment. The network adaptor 100 includes virtual NICs (indicated with dashed line frames in FIG. 6), a reception filter 110, a transmission filter 120, a storage unit 130 and a direct data transfer function 140… The virtual NICs are respectively prepared for the virtual machines 300 (VM1, VM2, - - - ). Each virtual NIC includes a reception queue 101 and a transmission queue 102...”, note that: (a) while these are not all components in network adaptor 100, fig. 6 discloses network adaptor 100 comprises a plurality of components as listed above, (b) for examining purposes, one, or more, or combination of these components could be interpreted as each of the claimed features “a data-plane packet input processor, a data-plane packet output processor, and the network interface controller”, and (c) with many possible examples and while not limiting to these, here are several examples in which one or more of these examples could be applied: (i) reception queue 101, transmission queue 102, within one or more virtual NICs respectively, (ii) reception filter 110, transmission filter 120, one or more virtual NICs respectively, (iii) reception queue 101, transmission filter 120, one or more virtual NICs respectively, (iv) reception filter 110, transmission queue 102, one or more virtual NICs respectively, etc.);
providing the outgoing packet processed by the network interface controller to the data-plane packet input processor on the single chip via a loopback entity on the single chip, the loopback entity separate from the data-plane packet output processor (Karino, see at least para. 74 in view of para. 69 of fig. 10 and/or fig. 11, “…If the transmission packet belongs to a different flow, on the other hand, no exact match entry is hit in the transmission filter table FILT2. Accordingly, the transmission filter 120 loops back the transmission packet as a reception packet to the reception filter 110. No exact match entry is hit also in the reception filter table FILT1. Hence, the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S...”, note that para. 69 of fig. 10 discloses one non-limiting example of how transmission filter table FILT2 provides “loopback”, also note that fig. 11 discloses a connecting entity between transmission filter 120 and reception filter 110 could also provide “loopback”);
determining by the data-plane packet input processor a target entity; and providing the outgoing packet to the target entity according to the determination (Karino, see at least para. 74 and 75, for one non-limiting example “…the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, note that a target entity is interpreted to be a next destination of one or more packets to be sent, queued, stored, etc., in other words, it is also possible the next destination would be VM 300 when a match is made as shown in para. 75).
Karino does not specifically teach (a) the description including information for locating different parts of the outgoing packet in memory, and (b) the loopback entity...coupled to a medium access controller (MAC) on the single chip.
Ronciak teaches (a) the description including information for locating different parts of the outgoing packet in memory (Ronciak, see at least fig. 1-2 and at least para. 22-23 of fig. 2, e.g. disclosing two embodiments in that one for ingress packets and another one for egress packets).
Kruglick teaches (b) the loopback entity...coupled to a medium access controller (MAC) on the single chip (Kruglick, see at least fig. 3 and its corresponding paragraphs, at least para. 28, “...The loopback controller 302 may be coupled to and/or implemented at the I/O ports (that is, the MAC layers 206 and/or the MAC/PHY layers 208)...”).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak and Kruglick into Karino for greatly reducing or eliminating the amount of run-time configuration performed as well as may allow reduction of off-chip delays and processor I/O loading.
Regarding claim 3, Karino in view of Ronciak and Kruglick teaches providing the outgoing packet to the target entity according to the determination comprises: providing the outgoing packet to a packet handling entity; and processing the outgoing packet in accordance with a packet management policy at the packet handling entity. (Karino, see at least para. 71-74, “…The two route patterns will be described below with reference to FIG. 9 and FIG. 11…”; Ronciak, see at least para. 18, “…For example, a processor 104 can implement a policy for assigning flows to many different transmit queues…”).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak and Kruglick into Karino for greatly reducing or eliminating the amount of run-time configuration performed.
Regarding claim 5, Karino in view of Ronciak and Kruglick teaches the processing the outgoing packet in accordance with the packet management policy at the packet handling entity comprises: providing the outgoing packet to a different destination than the target entity. (Karino, see at least para. 72-74, e.g. disclosing two embodiments in that one for transmitting packets and another one for receiving packets, note that the outgoing packet could thus become transmitting packets or receiving packets depending on situations).
Regarding claim 6, Karino in view of Ronciak and Kruglick teaches the processing the outgoing packet in accordance with the packet management policy at the packet handling entity comprises: providing the processed outgoing packet to a network via the data-plane packet output processor. (Karino, see at least para. 72-74, e.g. disclosing two embodiments in that one for transmitting packets and another one for receiving packets, note that the outgoing packet could thus become transmitting packets or receiving packets depending on situations).
Regarding claim 7, Karino in view of Ronciak and Kruglick teaches providing the outgoing packet to the target entity according to the determination comprises:
providing the outgoing packet processed by the data-plane packet input processor to a storage (Karino, see at least para. 74 and 75, “…Accordingly, the transmission filter 120 loops back the transmission packet as a reception packet to the reception filter 110. No exact match entry is hit also in the reception filter table FILT1. Hence, the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, as well as “…If the reception packet belongs to the flow “flow1” or “flow2”, an exact match entry is hit in the reception filter table FILT1. Accordingly, the reception filter 110 stores the reception packet in the reception queue 101 associated with to the corresponding virtual machine 300…”);
requesting the outgoing packet by the target entity (Karino, see at least para. 127-128, for an unlimited example, “…The virtual switch packet transmission/reception function 320 stores the received transmission packets in the buffer and requests the hypervisor 50 to transfer the packets…”);
and
processing the outgoing packet by a packet handling entity in accordance with a packet management policy (Karino, see at least para. 71-74, “…The two route patterns will be described below with reference to FIG. 9 and FIG. 11…”; Ronciak, see at least para. 18, “…For example, a processor 104 can implement a policy for assigning flows to many different transmit queues…”).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak and Kruglick into Karino for greatly reducing or eliminating the amount of run-time configuration performed.
Regarding claim 8, Karino in view of Ronciak and Kruglick teaches the processing the outgoing packet by the packet handling entity in accordance with the packet management policy comprises: providing the processed outgoing packet to the target entity. (Karino, see at least para. 74 and 75, for one unlimited example “…the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, note that a target entity is interpreted to be a next destination of one or more packets to be sent, queued, stored, etc., in other words, it is also possible the next destination would be VM 300 when a match is made as shown in para. 75).
Regarding claim 9, Karino in view of Ronciak and Kruglick teaches the processing the outgoing packet by the packet handling entity in accordance with the packet management policy comprises: providing the outgoing packet to a different destination than the target entity. (Karino, see at least para. 74 and 75, for one unlimited example “…the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, note that a target entity is interpreted to be a next destination of one or more packets to be sent, queued, stored, etc., in other words, it is also possible the next destination would be VM 300 when a match is made as shown in para. 75).
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Karino in view of Ronciak and Kruglick, as applied to claim 1 above, and further in view of Ronciak et al. (US 20060067228 A1, hereinafter Ronciak_28).
Regarding claim 4, Karino in view of Ronciak and Kruglick teaches the processing the outgoing packet in accordance with the packet management policy at the packet handling entity. (Karino, see at least para. 71-74, “…The two route patterns will be described below with reference to FIG. 9 and FIG. 11…”; Ronciak, see at least para. 18, “…For example, a processor 104 can implement a policy for assigning flows to many different transmit queues…”)
Karino in view of Ronciak and Kruglick does not specifically teach discarding the outgoing packet.
Ronciak_28 teaches discarding the outgoing packet (Ronciak_28, see at least para. 20 along with fig. 3, e.g. ejecting or removing packets).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak_28 into the method of Karino in view of Ronciak and Kruglick for effectively use of computing resources and packet processing time.
Regarding claim 10, Karino in view of Ronciak, Kruglick, and Ronciak_28 teaches the processing the outgoing packet by the packet handling entity in accordance with the packet management policy comprises: discarding the outgoing packet. (Karino, see at least para. 71-74; Ronciak, see at least para. 18; Ronciak_28, see at least para. 20 along with fig. 3, e.g. ejecting or removing packets).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak_28 into the method of Karino in view of Ronciak for effectively use of computing resources and packet processing time.
Response to Arguments
Applicant's arguments filed 08/26/2026 have been fully considered. Regarding independent claim 1, since applicant's amendment necessitated new ground(s) of rejection presented in this Office action, previous Office action's rejections are moot. Accordingly, corresponding dependent claims have also been rejected in this Office action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEE F LAM whose telephone number is (571)270-7577. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ayman Abaza can be reached on 571-270-0422. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YEE F LAM/Primary Examiner, Art Unit 2465
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