DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/17/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Shuichi Karino (US 20110320632 A1, hereinafter Karino), in view of Ronciak et al. (US 20060067349 A1, hereinafter Ronciak).
Regarding claim 1, Karino teaches a method for network switching with co-resident data-plane processors and network interface controller, comprising (Karino, in general, see fig. 9 along with fig. 10-11 and their respective paragraphs including but not limited to 67-80):
receiving a description of an outgoing packet at an internal facing interface of a network interface controller portion of a network interface resource implemented as a physical entity on a chip (Karino, see at least fig. 9 and para. 71-74 in view of para. 49, for one non-limited example, “…In this processing example, a transmission packet transmitted from the virtual machine 300 is firstly inputted to the network adaptor 100. At this time, the transmission packet is directly inputted to the network adaptor 100 by using the direct data transfer function 140 in the network adaptor 100 not through the virtual switch 200. The transmission filter 120 extracts the transmission packet from the selected transmission queue 102. If the transmission packet belongs to the flow “flow1” or “flow2”, an exact match entry is hit in the transmission filter table FILT2. Accordingly, the transmission filter 120 transmits the transmission packet to the data link…”, note that para. 49 discloses hardware network adaptor 100),
the network interface resource on the chip comprising a data-plane packet input processor, a data-plane packet output processor, and the network interface controller (Karino, see at least fig. 9 in view of fig. 6 and para. 49, “…FIG. 6 is a block diagram showing an exemplary overall configuration of the network adaptor 100 according to this embodiment. The network adaptor 100 includes virtual NICs (indicated with dashed line frames in FIG. 6), a reception filter 110, a transmission filter 120, a storage unit 130 and a direct data transfer function 140… The virtual NICs are respectively prepared for the virtual machines 300 (VM1, VM2, - - - ). Each virtual NIC includes a reception queue 101 and a transmission queue 102...”, note that: (a) while these are not all components in network adaptor 100, fig. 6 discloses network adaptor 100 comprises a plurality of components as listed above, (b) for examining purposes, one, or more, or combination of these components could be interpreted as each of the claimed features “a data-plane packet input processor, a data-plane packet output processor, and the network interface controller”, and (c) with many possible examples and while not limiting to these, here are several examples in which one or more of these examples could be applied: (i) reception queue 101, transmission queue 102, within one or more virtual NICs respectively, (ii) reception filter 110, transmission filter 120, one or more virtual NICs respectively, (iii) reception queue 101, transmission filter 120, one or more virtual NICs respectively, (iv) reception filter 110, transmission queue 102, one or more virtual NICs respectively, etc.);
providing the outgoing packet processed by the network interface controller to the data-plane packet input processor via a loopback entity, the loopback entity separate from the data-plane packet output processor (Karino, see at least para. 74 in view of para. 69 of fig. 10 and/or fig. 11, “…If the transmission packet belongs to a different flow, on the other hand, no exact match entry is hit in the transmission filter table FILT2. Accordingly, the transmission filter 120 loops back the transmission packet as a reception packet to the reception filter 110. No exact match entry is hit also in the reception filter table FILT1. Hence, the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S...”, note that para. 69 of fig. 10 discloses one non-limiting example of how transmission filter table FILT2 provides “loopback”, also note that fig. 11 discloses a connecting entity between transmission filter 120 and reception filter 110 could also provide “loopback”);
determining by the data-plane packet input processor a target entity; and providing the outgoing packet to the target entity according to the determination (Karino, see at least para. 74 and 75, for one non-limiting example “…the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, note that a target entity is interpreted to be a next destination of one or more packets to be sent, queued, stored, etc., in other words, it is also possible the next destination would be VM 300 when a match is made as shown in para. 75).
Karino does not specifically teach the description including information for locating different parts of the outgoing packet in memory.
Ronciak teaches the description including information for locating different parts of the outgoing packet in memory (Ronciak, see at least fig. 1-2 and at least para. 22-23 of fig. 2, e.g. disclosing two embodiments in that one for ingress packets and another one for egress packets).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak into Karino for greatly reducing or eliminating the amount of run-time configuration performed.
Regarding claim 3, Karino in view of Ronciak teaches providing the outgoing packet to the target entity according to the determination comprises: providing the outgoing packet to a packet handling entity; and processing the outgoing packet in accordance with a packet management policy at the packet handling entity. (Karino, see at least para. 71-74, “…The two route patterns will be described below with reference to FIG. 9 and FIG. 11…”; Ronciak, see at least para. 18, “…For example, a processor 104 can implement a policy for assigning flows to many different transmit queues…”).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak into the method of Karino for greatly reducing or eliminating the amount of run-time configuration performed.
Regarding claim 5, Karino in view of Ronciak teaches the processing the outgoing packet in accordance with the packet management policy at the packet handling entity comprises: providing the outgoing packet to a different destination than the target entity. (Karino, see at least para. 72-74, e.g. disclosing two embodiments in that one for transmitting packets and another one for receiving packets, note that the outgoing packet could thus become transmitting packets or receiving packets depending on situations).
Regarding claim 6, Karino in view of Ronciak teaches the processing the outgoing packet in accordance with the packet management policy at the packet handling entity comprises: providing the processed outgoing packet to a network via the data-plane packet output processor. (Karino, see at least para. 72-74, e.g. disclosing two embodiments in that one for transmitting packets and another one for receiving packets, note that the outgoing packet could thus become transmitting packets or receiving packets depending on situations).
Regarding claim 7, Karino in view of Ronciak teaches providing the outgoing packet to the target entity according to the determination comprises:
providing the outgoing packet processed by the data-plane packet input processor to a storage (Karino, see at least para. 74 and 75, “…Accordingly, the transmission filter 120 loops back the transmission packet as a reception packet to the reception filter 110. No exact match entry is hit also in the reception filter table FILT1. Hence, the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, as well as “…If the reception packet belongs to the flow “flow1” or “flow2”, an exact match entry is hit in the reception filter table FILT1. Accordingly, the reception filter 110 stores the reception packet in the reception queue 101 associated with to the corresponding virtual machine 300…”);
requesting the outgoing packet by the target entity (Karino, see at least para. 127-128, for an unlimited example, “…The virtual switch packet transmission/reception function 320 stores the received transmission packets in the buffer and requests the hypervisor 50 to transfer the packets…”);
and
processing the outgoing packet by a packet handling entity in accordance with a packet management policy (Karino, see at least para. 71-74, “…The two route patterns will be described below with reference to FIG. 9 and FIG. 11…”; Ronciak, see at least para. 18, “…For example, a processor 104 can implement a policy for assigning flows to many different transmit queues…”).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak into the method of Karino for greatly reducing or eliminating the amount of run-time configuration performed.
Regarding claim 8, Karino in view of Ronciak teaches the processing the outgoing packet by the packet handling entity in accordance with the packet management policy comprises: providing the processed outgoing packet to the target entity. (Karino, see at least para. 74 and 75, for one unlimited example “…the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, note that a target entity is interpreted to be a next destination of one or more packets to be sent, queued, stored, etc., in other words, it is also possible the next destination would be VM 300 when a match is made as shown in para. 75).
Regarding claim 9, Karino in view of Ronciak teaches the processing the outgoing packet by the packet handling entity in accordance with the packet management policy comprises: providing the outgoing packet to a different destination than the target entity. (Karino, see at least para. 74 and 75, for one unlimited example “…the reception filter 110 transmits the reception packet to the virtual switch 200 through the reception queue 101-S…”, note that a target entity is interpreted to be a next destination of one or more packets to be sent, queued, stored, etc., in other words, it is also possible the next destination would be VM 300 when a match is made as shown in para. 75).
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Karino in view of Ronciak, as applied to claim 1 above, and further in view of Ronciak et al. (US 20060067228 A1, hereinafter Ronciak_28).
Regarding claim 4, Karino in view of Ronciak teaches the processing the outgoing packet in accordance with the packet management policy at the packet handling entity. (Karino, see at least para. 71-74, “…The two route patterns will be described below with reference to FIG. 9 and FIG. 11…”; Ronciak, see at least para. 18, “…For example, a processor 104 can implement a policy for assigning flows to many different transmit queues…”)
Karino in view of Ronciak does not specifically teach discarding the outgoing packet.
Ronciak_28 teaches discarding the outgoing packet (Ronciak_28, see at least para. 20 along with fig. 3, e.g. ejecting or removing packets).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak_28 into the method of Karino in view of Ronciak for effectively use of computing resources and packet processing time.
Regarding claim 10, Karino in view of Ronciak and Ronciak_28 teaches the processing the outgoing packet by the packet handling entity in accordance with the packet management policy comprises: discarding the outgoing packet. (Karino, see at least para. 71-74; Ronciak, see at least para. 18; Ronciak_28, see at least para. 20 along with fig. 3, e.g. ejecting or removing packets).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to incorporate Ronciak_28 into the method of Karino in view of Ronciak for effectively use of computing resources and packet processing time.
Response to Arguments
Applicant's arguments filed 02/17/2026 have been fully considered. Regarding independent claim 1, since applicant's amendment necessitated new ground(s) of rejection presented in this Office action, previous Office action's rejections are moot. Accordingly, corresponding dependent claims have also been rejected in this Office action.
Applicant's arguments filed 02/17/2026 have been fully considered but they are not persuasive. Examiner provides response in following sections.
Regarding independent claim 1, applicant argues that (applicant’s emphasis included, if any):
“Response to Arguments- No Guidance Provided by the Office as Requested
As submitted in Applicant's Reply filed on October 14, 2025 (hereinafter, "Previous Reply"), the Office cites FIG. 5, FIG. 6, and FIG. 9 of U.S. Published Application No. 2011/0320632 A1 to Shuichi Karino (hereinafter, "Karino") and, while such figures may include components, such as a network adapter 100, virtual NICs (indicated with dashed lines), a reception filter 100, a transmission filter 120, etc., Applicant is unable to determine which elements of the cited figures the Office is interpreting as purportedly disclosing "a data-plane packet input processor, a data-plane packet output processor, and [a] network interface controller," much less "a network interface resource implemented [] on a chip" that comprises such elements, as required by Applicant's independent claim 1, as previously presented and as currently amended. Further, the Office does not cite any element of any reference as purportedly disclosing the claimed "chip," as required by Applicant's independent claim 1, as previously presented and as currently amended.
As requested in Applicant's Previous Reply and not addressed by the Office, Applicant requests guidance to understand which components of Karino the Office is citing as purportedly disclosing the above-noted elements, as required (emphasis added) by 37 C.F.R.§ 1.104 (i.e., "[w]hen a reference is complex or shows or describes inventions other than that claimed by the applicant, the particular part relied on must be designated as nearly as practicable"). Applicant respectfully submits that the Office does not provide such designation as requested because Karino does not disclose same as submitted below.” (Remarks, page 5-6)
Examiner respectfully disagrees. In previous Office Action (OA) mailed on 11/17/2025, the Response to Arguments section (see at least page 10) clearly addressed the argued features of "a data-plane packet input processor, a data-plane packet output processor, and [a] network interface controller". For example, the previous OA stated, in part, “...Karino in at least para. 53 of fig. 6 discloses an exemplary overall configuration of the network adaptor 100 comprising virtual NICs (indicated with dashed line frames in FIG. 6), reception filter 110, transmission filter 120,...”. In addition, claim 1 rejection in the previous OA has already pointed out that NIC 100 is in form of a hardware (see Karino para. 49 as stated in claim 1 rejection). Hence, the examiner does not agree there was no guidance provided by the Office as requested. Indeed, guidance was clearly provided in the previous OA and in claim 1 rejection.
NOTE: due to newly amended features in the current claim set dated 02/17/2026, the above interpretation(s) of the argued features may have changed accordingly. Any updated interpretations would be provided in the current OA.
Further, applicant argues that (applicant’s emphasis included, if any):
“Applicant respectfully submits that even if the references could be combined, which Applicant does not concede, the cited hypothetical combination does not disclose at least "a network interface resource implemented as a physical entity on a chip... the network interface resource on the chip comprising a data-plane packet input processor, a data-plane packet output processor, and the network interface controller," as required by Applicant's independent claim 1, as currently amended, where underline denotes insertion of claim elements. At pages 3 and 4 of the Final Office Action, the Office cites Karino as purportedly disclosing the above-noted elements prior to amendment. Applicant respectfully disagrees.
Specifically, Karino is silent regarding "a chip," as required by Applicant's independent claim 1, as previously presented and as currently amended. Further, while Karino may disclose a processor, nowhere does Karino disclose that the cited reception filter 100 and transmission filter 120 are processors and, thus, such filters do not disclose "a data-plane packet input processor" and "a data-plane packet output processor," respectively, as recited in Applicant's independent claim 1, as previously presented and as currently amended. In addition, the cited virtual network interface cards (NICs) of Karino are virtual NICs, that is, software abstractions of NICs, and such software abstractions do not disclose the claimed "network interface controller" because Karino does not disclose that "a network interface resource implemented as a physical entity on a chip" comprises same, as required by Applicant's independent claim 1, as currently amended.” (Remarks, page 6-7)
Examiner respectfully disagrees. As stated above, “...claim 1 rejection in the previous OA has already pointed out that NIC 100 is in form of a hardware (see Karino para. 49 as stated in claim 1 rejection)...”. To be more specific, Karino para. 49 discloses, in part, “...FIG. 4 is the block diagram showing the hardware configuration of each server (physical server) 10 according to this embodiment. The server 10 contains a CPU (Central Processing Unit) 20, a main memory 30 and a network adaptor (network interface apparatus) 100...”. Hence, it is very clear that network adaptor 100 (shown in both fig. 6 and 9 of Karino) is in form of a hardware (i.e. physical circuity).
NOTE: applicant appears to equate that virtual NIC of Karino is of the network interface controller of claim 1, i.e. applicant appears to agree that guidance was indeed provided. Nonetheless, due to newly amended features in the current claim set dated 02/17/2026, interpretation(s) of the argued features may have been changed accordingly. Any updated interpretations would be provided in the current OA.
Further, applicant argues that (applicant’s emphasis included, if any):
“Further, the cited transmission filter 120 of Karino loops back a transmission packet as a reception packet if there is no exact match entry in the transmission filter table for the header information of the transmission packet. See Karino, paragraph [0070]. As should be appreciated from the foregoing, Karino does not disclose that a filter is processor and describing that a filter loops back a transmission packet does not teach or suggest "providing [an] outgoing packet processed by [a] network interface controller to [a] data-plane packet input processor via a loopback entity, the loopback entity separate from the data-plane packet output processor," as required by Applicant's independent claim 1, as currently amended, where underline denotes insertion of claim elements.” (Remarks, page 7)
Examiner respectfully disagrees, and believes the arguments are centered on the newly amended features in the underlined portion above, which have been properly addressed in claim 1 rejection in the current OA. Examiner suggests applicant to review the relevant section for details. In addition, filters of Karino (which is within the network adaptor 100) are circuitries that process incoming and outgoing packets. Hence, filters of Karino could indeed be interpreted as processors by a skilled artisan.
NOTE: applicant appears to equate that filters of Karino are of the processors of claim 1, i.e. applicant appears to agree that guidance was indeed provided. Nonetheless, due to newly amended features in the current claim set dated 02/17/2026, interpretation(s) of the argued features may have been changed accordingly. Any updated interpretations would be provided in the current OA.
Further, applicant argues that (applicant’s emphasis included, if any):
“Ronciak was cited for purportedly disclosing a description that includes information for locating different parts of an outgoing packet in memory and does not remedy the above-noted deficiencies of Karino. Further, at page 4 of the Final Office Action, the Office correctly acknowledges that Karino does not disclose "the description including information for locating different parts of the outgoing packet in memory," as required by Applicant's independent claim 1, as previously presented and as currently amended, and cites Ronciak as purportedly disclosing same. Applicant respectfully disagrees. In contrast to the above-noted elements, Ronciak's packet descriptor identifies a location of packet data in memory.
The location identified by Ronciak's packet descriptor enables Ronciak to direct memory access (DMA) packet data to enqueue or dequeue such packet data. Thus, the cited packet descriptor identifies a starting location of the packet data for directly transferring same and does not "includ[e] information for locating different parts of [an] outgoing packet in memory," as required by Applicant's independent claim 1, as previously presented and as currently amended (emphasis added).” (Remarks, page 7)
Examiner respectfully disagrees, Ronciak in its para. 22 discloses that “...The packet descriptors, in turn, reference entries in the different receive queues 112 b, 114 b, 116 b the controller 100 can use to enqueue the ingress packet data. After accessing a packet descriptor for the desired receive queue 112 b, 114 b, 116 b, the controller 100
can use Direct Memory Access (DMA) to enqueue the received ingress packet data...”. A similar or corresponding process is disclosed in para. 23 for egress packets with transmit queues. Hence, Ronciak, or Karino-Ronciak, indeed teaches or suggests the argued features of “...the description including information for locating different parts of the outgoing packet in memory," as recited in claim 1.
Accordingly, all dependent claims of the independent claim 1, in view of the response above, the examiner has maintained the rejection as presented and believes all rejections are proper and should be sustained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEE F LAM whose telephone number is (571)270-7577. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ayman Abaza can be reached on 571-270-0422. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YEE F LAM/Primary Examiner, Art Unit 2465
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