DETAILED ACTION
Claims 1-20 are currently pending in the application. Claims 1-20 are original claims to patent US 9,081,625 B2 with claims 1-20 being amended.
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Reissue Applications
For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions.
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 9,081,625 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Application History
The instant continuation reissue application (16/926,188) is a reissue of patent 9,081,625 (application 13/652,512) and a continuation of application 16/817,238, itself a reissue of patent 9,081,625 (application 13/652,512).
As summarized from the Decision on Petition (04/27/2023), the instant application was initially treated as a 35 USC 111(a) Bauman-type continuation application, but is now treated as a continuation reissue application under 35 USC 251. The petition concluded, “[t]his application is being directed to the Office of Patent Application Processing for processing as a reissue application (and issuance of an updated filing receipt consistent with the continuity data set forth on the updated Application Data Sheet filed August 15, 2022)”.
Information Disclosure Statements
The information disclosure statements (IDS) submitted on 07/10/2020 are considered by the examiner in accordance with 37 CFR 1.98, 37 CFR 1.555, and MPEP 2257, to the fullest extent of the items presented including any concise explanation. Documents not meeting particular criteria are lined through and not considered.
Objections - ADS
The ADS filed 08/15/2022 is objected to because of the following informalities: the Domestic Benefit section needs to correctly identify the relationships of continuation and reissue for applications 16/926,188 (current continuation reissue application), 16/817,238, 13/652,512. The corrected ADS should comply with 37 CFR 1.76(c)(2), which requires that any changes to an ADS be identified with markings (see Reissue Application Filing Guide at http://www.uspto.gov/sites/default/files/forms/uspto_reissue_ads_guide_Sept2014.pdf for more information). Applicant can also use the Corrected Web-based ADS. See the Quick Start Guide for Corrected Web-based ADS at https://www.uspto.gov/sites/default/files/documents/Corrected-WebADS-QSG.pdf.
For example, the Domestic Benefit section of the ADS needs to have the following (3) general entries (albeit with corresponding dates/fields indicated as appropriate for the ADS):
16/926,188
Continuation of
16/817,238
16/926,188
Reissued of
13/652,512
16/817,238
Reissued of
13/652,512
Objections - Declaration
The reissue oath/declaration filed with this application is defective and objected to because it fails: (1) to identify at least one error under 35 USC 251 (37 CFR 1.175(a)); and (2) to identify the broadened claims (37 CFR 1.175(a)). “Any error in the claims must be identified by reference to the specific claim(s) and the specific claim language wherein lies the error” (see MPEP 1414 II).
Objections - Claims
Claims 1-20 are objected to because of the following informalities: (1) the amendment filed 07/10/2020 does not make changes relative to the patent as required by CFR 1.173(g). For example, original claims 1-20 have already been reissued in RE49,781 and therefore do not exist in the original patent 9,081,625.
Claim Rejections – 35 USC § 251
Claims 1-20 are rejected under 35 U.S.C. 251 as not correcting an error in the original patent (see 37 CFR 1.177(b); and MPEP 1451). For example, claims 1-20 have already been reissued in RE49,781 and therefore do not exist in the original patent 9,081,625. To overcome this rejection, the instant application (16/926,188) should amend the claims to cancel claims 1-20 and add claims starting at new claim 21.
Claim Rejections – 35 USC § 251
Claims 1-20 are rejected as being based upon a defective reissue declaration under 35 U.S.C. 251 as set forth above because the declaration filed with this application fails: (1) to identify at least one error under 35 USC 251 (37 CFR 1.175(a)); and (2) to identify the broadened claims (37 CFR 1.175(a)). “Any error in the claims must be identified by reference to the specific claim(s) and the specific claim language wherein lies the error” (see MPEP 1414 II).
Claims 1-20 are rejected under 35 U.S.C. 251 as being broadened in a reissue application filed outside the two year statutory period. The claims are impermissibly broadened by the removal of any or any combination of the following limitations. For example, the preliminary amendment of independent claim 1 broadens the claim by removing: “computer implemented”; “individual”; “determining from the at least one configuration parameter if a first set of one or more cores are selected to be disabled from operation; in response to none of the first set of cores being selected to be disabled”; “second” with relation to a set of cores; “first” with relation to an operating state; and “in response to the first set of cores being selected to be disabled, disabling the first set of cores and determining a second operating state that reduces jitter for a third set of one or more enabled cores; determining if the third set of enabled cores are selected to be jitter controlled; and in response to the third set of enabled cores being selected to be jitter controlled, setting the third set of enabled cores to the second operating state that reduces jitter”. The preliminary amendment of independent claim 9 broadens the claim by removing: “in communication” with relation to a plurality of cores; “in communication” with relation to control logic; “having firmware executing”; “wherein the firmware”; “determine from the at least one configuration parameter if a first set of one or more cores are selected to be disabled from operation; in response to none of the first set of cores being selected to be disabled”; “second” with relation to set of cores; “first” with relation to an operating state; and “in response to the first set of cores being selected to be disabled, disable the first set of cores from operation based on a physical location of each core and determine a second operating state that reduces jitter for a third set of one or more enabled cores; determine if the third set of enabled cores are selected to be jitter controlled; and in response to the third set of enabled cores being selected to be jitter controlled, set the third set of enabled cores to the second operating state that reduces jitter”. The preliminary amendment of independent claim 9 broadens the claim by removing: a processor having “control logic”; coupled “via a system interconnect”; “the control logic having firmware executing thereon to reduce execution jitter, wherein the firmware configures the control logic”; “determine from the at least one configuration parameter if a first set of one or more cores are selected to be disabled from operation; in response to none of the first set of cores being selected to be disabled”; “second” with relation to a set of cores; “first” with relation to an operating state; and “in response to the first set of cores being selected to be disabled, disable the first set of cores from operation and determine a second operating state that reduces jitter for a third set of one or more enabled cores; determine if the third set of enabled cores are selected to be jitter controlled; and in response to the third set of enabled cores being selected to be jitter controlled, set the third set of enabled cores to the second operating state that reduces jitter”. The dependent claims suffer from the same impermissible broadening by virtue of their dependence on their respective independent claim.
A claim is broader in scope than the original claims if it contains within its scope any conceivable product or process which would not have infringed the original patent. A claim is broadened if it is broader in any one respect even though it may be narrower in other respects. See MPEP 1412.03.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1-20 are indefinite because the invention of claims 1-20 is not particularly pointed out and distinctly claimed. Claims 1-20 present one coverage in reissue application 16/817,238 and another in the present continuation reissue application. This is inconsistent. See 37 CFR 1.177(b) and MPEP 1451.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 9,817,660. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are an obvious variation of the 9,817,660 patented claims. For example, a person of ordinary skill in the art would recognize the broader instant claim limitations to be a subset of the 9,817,660 patented claim limitations. See the following comparison:
Claim 1 (16/926,188)
9,817,660
A method of reducing execution jitter within
a processor having a control logic and a plurality of cores, the method comprising:
Claim 1 recites, “[a] computer implemented method of reducing execution jitter within a processor having control logic and a plurality of individual cores, the method comprising:”.
receiving a core configuration parameter;
Claim 1 of the ‘660 patent shows at least a configuration parameter used in relation to several cores and sets of cores. The parameter is received in some manner in order to be used or operated upon.
determining, based upon the core configuration parameter, if a set of cores is selected to be jitter controlled; and
Claim 1 shows the configuration parameter leading to “determining if the third set of enabled cores are selected to be jitter controlled”. This is shown because the claim states the sets of cores are configurable with regard to an operating state that reduces jitter and the operating state is based in part on the number of disabled cores. Claim 1 shows based on the configuration parameter the first set of cores is disabled and an operating state for the third set is determined, thus leading to “determining if the third set of enabled cores are selected to be jitter controlled”.
in response to the set of the cores being selected to be jitter controlled, setting the set of cores to an operating state that reduces jitter,
Claim 1 of the ‘660 patent shows the configuration parameter leading to “determining an operating state that reduces jitter for the third set of one or more enabled cores” and “setting the third set of enabled cores to the operating state that reduces jitter”.
wherein the operating state restricts a highest clock frequency with which a set of instructions
or threads is executed by any enabled core among the set of cores.
Claim 4 of the ‘660 patent shows setting a clock frequency (that is to say restricting to a highest clock frequency) for the third set of cores.
Claim 2
9,817,660
The method of claim 1, wherein the core configuration parameter comprises an ordered lookup table of the set of cores.
See claim 2.
Claim 3
9,817,660
The method of claim 1, further comprising:
receiving the core configuration parameter from a basic input output system stored in memory; and loading the core configuration parameter into the control logic.
See claim 3.
Claim 4
9,817,660
The method of claim 1, wherein the highest clock frequency is based on a number of disabled cores.
Claim 1 of the ‘660 patent shows “the operating state being in part based on the number of disabled cores” and claim 4 shows the operating state comprising an operating frequency (or highest clock frequency).
Claim 5
9,817,660
The method of claim 1, wherein a disabled core does not operate and is selected to be disabled based on a physical location.
See claim 5.
Claim 6
9,817,660
The method of claim 1, further comprising:
determining a second operating state for a second set of cores;
determining if the second set of cores is selected to be jitter controlled; and
in response to the second set of cores being selected to be jitter controlled, setting the second set of cores to the second operating state, wherein the second operating state restricts another highest clock frequency with which another set of instructions or threads is executed by any enabled core among the second set of cores.
See claims 6 and 4.
Claim 7
9,817,660
The method of claim 1, further comprising:
loading, into the control logic, an ordered lookup table of cores ordered by maximum physical spacing between cores;
enabling operation of a first core in the ordered lookup table;
enabling operation of a next sequential core in the ordered lookup table.
See claim 7.
Claim 8
9,817,660
The method of claim 1, further comprising:
selecting a first core of the plurality of cores;
placing the first core in a first position in an ordered lookup table;
determining if all cores have been placed in the lookup table; and
in response to all cores not having been placed in the table, selecting a second core with maximum spacing from other cores that are not yet selected for the table and placing the selected second core in a next sequential position in the
ordered lookup table.
See claim 8.
Claims 9-20
9,817,660
The limitations of claims 9-20 correspond to the limitations of claims 1-8.
The limitations of claims 1-8 of patent ‘660 (as well as claims 9-20) are correspond to the limitations of application 16/926,188.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. RE49,781. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are an obvious variation of the RE49,781 patented claims. For example, a person of ordinary skill in the art would recognize the broader instant claim limitations to be a subset of the RE49,781 patented claim limitations. See the following comparison:
Claim 1 (16/926,188)
RE49,781
A method of reducing execution jitter within
a processor having a control logic and a plurality of cores, the method comprising:
Claim 1 recites, “[a] computer implemented method of reducing execution jitter within a processor having a control logic and a plurality of individual cores, the method comprising:”.
receiving a core configuration parameter;
Claim 1 of the ‘781 patent shows at least a configuration parameter used in relation to several cores and sets of cores.
determining, based upon the core configuration parameter, if a set of cores is selected to be jitter controlled; and
Claim 1 shows the configuration parameter leading to “determining if a second set of one or more cores is selected to be jitter controlled”. This is shown because claim 1 shows based on the configuration parameter none of the first set of cores being selected to be disabled.
in response to the set of the cores being selected to be jitter controlled, setting the set of cores to an operating state that reduces jitter,
Claim 1 of the ‘781 patent shows the configuration parameter leading to “in response to the second set of cores being selected to be jitter controlled, setting the second set of cores to a first operating state that reduces jitter”.
wherein the operating state restricts a highest clock frequency with which a set of instructions
or threads is executed by any enabled core among the set of cores.
Claim 4 of the ‘781 patent shows setting a clock frequency (that is to say restricting to a highest clock frequency) for the third set of cores.
Claim 2
RE49,781
The method of claim 1, wherein the core configuration parameter comprises an ordered lookup table of the set of cores.
See claim 2.
Claim 3
RE49,781
The method of claim 1, further comprising:
receiving the core configuration parameter from a basic input output system stored in memory; and loading the core configuration parameter into the control logic.
See claim 3.
Claim 4
RE49,781
The method of claim 1, wherein the highest clock frequency is based on a number of disabled cores.
See claim 4.
Claim 5
RE49,781
The method of claim 1, wherein a disabled core does not operate and is selected to be disabled based on a physical location.
See claim 5.
Claim 6
RE49,781
The method of claim 1, further comprising:
determining a second operating state for a second set of cores;
determining if the second set of cores is selected to be jitter controlled; and
in response to the second set of cores being selected to be jitter controlled, setting the second set of cores to the second operating state, wherein the second operating state restricts another highest clock frequency with which another set of instructions or threads is executed by any enabled core among the second set of cores.
See claims 6 and 4.
Claim 7
RE49,781
The method of claim 1, further comprising:
loading, into the control logic, an ordered lookup table of cores ordered by maximum physical spacing between cores;
enabling operation of a first core in the ordered lookup table;
enabling operation of a next sequential core in the ordered lookup table.
See claim 7.
Claim 8
RE49,781
The method of claim 1, further comprising:
selecting a first core of the plurality of cores;
placing the first core in a first position in an ordered lookup table;
determining if all cores have been placed in the lookup table; and
in response to all cores not having been placed in the table, selecting a second core with maximum spacing from other cores that are not yet selected for the table and placing the selected second core in a next sequential position in the
ordered lookup table.
See claim 8.
Claims 9-20
RE49,781
The limitations of claims 9-20 correspond to the limitations of claims 1-8.
The limitations of claims 1-8 of patent ‘781 (as well as claims 9-20) are correspond to the limitations of application 16/926,188.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H WOOD whose telephone number is (571)272-3736. The examiner can normally be reached Monday-Friday 7am-3pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Kosowski can be reached on (571)272-3744. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/William H. Wood/
Primary Examiner, CRU 3992
Conferees:
/RSD/
/ALEXANDER J KOSOWSKI/Supervisory Patent Examiner, Art Unit 3992