DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responsive to the amendment filed on 08/10/2026 Claims 1-30 are pending.
Response to Arguments
In respond to Applicant’s argument regarding rejection 35 U.S.C. 101 on Remarks page 10, “amended claim 1 recites a specific accelerator-based implementation of those operations, including hardware-constrained sub-portion sizing tied to operand sizes of a matrix multiplication instruction of the accelerator and reduction using results stored in memory of the accelerator. Even assuming arguendo that the claim could be characterized as reciting an alleged abstract idea, the claim integrates any such idea into a practical application under Step 2A, Prong Two, at least because the recited elements define a particular technological configuration for performing the claimed operations on accelerator hardware. See, e.g., M.P.E.P. §§2106.04(d), 2106.05(a).”
Examiner respectfully disagrees because the amended claim 1 recites a plurality of threads of an accelerator, sizes of the sub-portions corresponds to operand sizes of a matrix multiplication instruction, storing result at a high level of generality, that amount to no more than mere instructions to apply the judicial exception using computer components. Furthermore, the description of operand sizes of instruction is at most considered as insignificant extra solution activity because any mathematical operation instruction would include a certain size of data being operated on, and the step of storing data is also an insignificant post activity and determined by the Court to be well-understood, routine and conventional activity (see MPEP 2106.05(d)(II)(iv) Storing and retrieving information in memory).
Applicant further asserted on page 10, “Further, any improvement here is not attributed to matrix multiplication or reduction in the abstract, but instead to the additional recited technological features, namely the instruction- sized sub-portions and the reduction using results stored in accelerator memory. These additional limitations also amount to significantly more than any alleged abstract idea under Step 2B, because the accelerator, the plurality of threads, the instruction-sized sub-portions, and the use of accelerator memory-stored results operate together as an ordered combination to implement a specific technological arrangement for accelerator-based matrix processing, rather than a generalized instruction to perform matrix operations on generic computing components. See, e.g., M.P.E.P. $2106.05(d).”
Examiner respectfully disagrees because Applicant fails to explain how the technological improvement is provided by the instruction sized sub-portions and the reduction using results stored in memory recited at a high level of generality. Furthermore, as explained above, the plurality of threads, the instruction, the use of memory are merely recited at a high level of generality and amount to no more than mere instruction to apply the judicial exception using computer components (see MPEP 2106.05(f) recites “simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more”). Moreover, the claim merely recites a matrix multiplication instruction to be performed by the accelerator, which is equivalent to a generalized instruction to perform matrix operations on generic computing components.
Claim Objections
Claims 2-10, 12-20, and 22-30 are objected to because of the following informalities:
Claim 2 line 2-3; claim 12 line 2-3; claim 22 line 2-3 "a first matrix of two or more matrices" should be "a first matrix of the two or more matrices" as antecedently recited.
Claim 6 line 2; claim 16 line 2; claim 26 line 2 “a plurality of the one or more threads” should be “the plurality of threads” as antecedently recited.
Claims 6-8 line 3, 5; claims 16-18 line 3-4; claims 26-28 line 2-4 “the one or more threads” should be “the plurality of threads” as antecedently recited.
Claim 24 line 2-3“the second plurality of the sub-portions” and claim 23 line 2-3 recites “a plurality of second sub-portions”. Examiner suggests amending the language in either claim 23 or 24 to stay consistent for clarification purposes. (note that claims 3-4, 13-14 recite similar limitation. Thus, examiner suggests amending the claim in a similar manner).
dependent claims are also objected for inheriting the same deficiencies in which claims they depend on.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7, 17, and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 27 recites “an application of the reduction operations”. It is unclear whether the reduction operations refers to a plurality of reduction operations being performed in a plurality of hierarchical operations or the multiple instances of reduction operations being recited in the claims. For examination purposes, Examiner interprets such limitation as an application of the reduction operations of the plurality of hierarchical operations.
Claim 17 line 3 recites “the reduction operation”. it is unclear whether “the reduction operation” is referring to the reduction operation of two or more matrices as recited in claim 11 line 3, or the reduction of results of a matrix multiplication (MM) of respective sub-portions as recited in claim 11 line 5-6, or reduction of the results of the matrix multiplication as recited in claim 11 line 14 or the reduction operation of the MM of a first matrix of two or more matrices and a second matrix of the two or more matrices as recited in claim 12 line 2-3, or the reduction operation of a result of a portion of the MM that involves one of the first plurality of sub-portions as recited in claim 12 line 7-8. Figure 6 illustrates step 645 to perform matrix element redistribution prior to reduction operation at higher hierarchical levels. For examination purposes, Examiner interprets such the reduction operation as a reduction operation at a higher hierarchical level.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-30 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract without significantly more.
Claim 1 recites an apparatus for performing a matrix multiplication and reduction operation of two or more matrices.
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites perform a matrix multiplication and reduction operation of two or more matrices by at least performing a plurality of hierarchical operations each comprising reduction of results of a matrix multiplication (MM) of respective sub-portions of the two or more matrices, wherein sizes of the sub-portions in each of the plurality of hierarchical operations correspond to an order of a respective one of the plurality of hierarchical operations; performs reduction of the results of the matrix multiplication. such limitation covers mathematical calculations, relationship, and/or formula (e.g., performing multiplication and reduction operation on matrices, see at least figures 2-3, and 6 describing the concept of performing such mathematical operation in a plurality of hierarchical operations level). Therefore, the claim include limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites one or more processors comprising circuitry, a plurality of threads of an accelerator, a memory. However, the additional elements are recited at a high level of generality, i.e., as computer components to perform computer functions of processing data and storing data. Furthermore, the claim recites the limitation of the sizes of the sub-portions for at least one level of the hierarchy correspond to operand sizes of a matrix multiplication instruction, and the step of storing results of the matrix multiplication instruction. However, such limitations are at most considered as insignificant extra/post solution activity because they recite elements that are well-known. Such elements fail to provide meaningful limitations on the judicial exception, and amount to no more than mere instructions to apply the exception using computer elements. Thus, the claim is directed to an abstract idea.
Under Step 2B, as discussed with respect to Prong Two of Step 2A, the additional elements in the claim amount no more than mere instructions to apply the exception using a generic component. The same conclusion is reached in step 2B, i.e., mere instruction to apply an exception on computer elements cannot integrate a judicial exception into a practical application at step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception. Furthermore, the limitation that describes data sizes corresponds to operand size of an instruction and storing the results are determined to be well-understood, routine, and conventional activity under step 2B, see at least MPEP 2106.05(d)(II)(iv). Storing and retrieving information in memory, and John L., et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology, 2014 page 132 describes configuration of an instruction having data sources corresponding to the sizes of the data being operated on and also a destination register for storing results in the case of multiply-add instruction described in page 136. Thus, the additional elements fail to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 2 further recites the plurality of hierarchical operations perform a reduction operation of the MM of a first matrix of two or more matrices and a second matrix of the two or more matrices, and represent, at each hierarchical operation of the plurality of hierarchical operations, the first matrix via a first plurality of the sub-portions; and apply, at the respective hierarchical operation, a reduction operation to a result of a portion of the MM that involves one of the first plurality of the sub-portions, to generate a corresponding vector of two or more vectors. Such limitation covers mathematical calculations, relationship, and/or formula (e.g., performing matrix multiplication and reduction at a plurality of hierarchical levels, see at least figures 5-6). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 3 further recites represent the second matrix via a plurality of second sub-portions. Such limitation covers mathematical calculations, relationship, and/or formula (merely describes the second matrix for performing matrix multiplication operation). The claim does not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two, and provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 4 further recites in the respective hierarchical operation, a number of matrix elements in each of the first plurality of sub-portions is equal to a number of matrix elements in each of the second plurality of sub-portions. Such limitation covers mathematical calculations, relationship, and/or formula (e.g., performing matrices operation having similar dimension). The claim does not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two, and provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 5 further recites wherein to perform a hierarchical operation of a lowest hierarchical order, the MM operation of matrices of predetermined dimension. Such limitation covers mathematical calculations, relationship, and/or formula (e.g., performing matrices operation having a predetermined dimension).The claim further recites the one or more circuits are to use one or more instances of a hardware instruction, such additional element is recited at a high level of generality, i.e., as a computer component for performing computer function of executing an instruction, which amounts to no more than mere instructions to apply the judicial exception using computer component. Thus, The claim does not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two, and provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 6 further recite wherein the one or more circuits are to perform the hardware instruction using a plurality of the one or more threads, each thread of the one or more threads being associated with: a plurality of input matrix elements of each of matrices input into the hardware instruction; and a plurality of output matrix elements of a matrix output by the hardware instruction. Such additional element of performing hardware instruction using a plurality of threads, each thread being associated with input matrix elements and output matrix element of matrices are recited at a high level of generality and are at most considered as insignificant extra solution activity under step 2A prong two and are determined to be well-understood, routine and conventional under step 2B, see at least Dakkak, section 2.2 page 2 illustrates threads within a warp utilize multiple tensor cores concurrently to perform the mma_sync instruction. Mukunoki – NPL Automatic Thread-Block Size Adjustment for Memory-Bound BLAS Kernels on GPUs, section II page 378 describes execution model of CUDA is referred as to single instruction multiple thread (SIMT) model, a multiprocessor executes threads in a unit of 32 threads, the unit of 32 threads is called a warp, and all 32 threads in a warp perform the same instruction concurrently. Also see Gonzalo – NPL Automatic Generation of Warp-level primitives and Atomic Instructions for Fast and Portable Parallel Reduction on GPUs, figure 2 page 76 describes a CUDA block is broken down to 2 warps with 32 threads to perform operation in parallel. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 further recites wherein the one or more circuits are to redistribute at least some of the plurality of output matrix elements to different threads of the one or more threads prior to an application of the reduction operations. Such additional element of redistribute data between different threads is recited at high level of generality and is at most considered as insignificant extra solution activity under step 2A prong two and is determined to be well-understood, routine and conventional under step 2B, see at least Gonzalo page 74 describes warp shuffle instructions, these instructions allow threads in the same warp to exchange private register values via execution unit data path, Mukunoki page 381 describes the use of warp shuffle instruction, Dakkak page 4 section 3 also describes warp level implemented using shuffle instruction that allow threads within a warp to share value via registers without using share memory. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 8 further recites wherein the one or more circuits are to store the plurality of input matrix elements and the plurality of output matrix elements, associated with each thread of the one or more threads, in registers accessible by a respective thread of the one or more threads. Such additional element of storing the input matrix elements and output matrix elements associated with each thread in registers is considered as insignificant extra activity under step 2A prong two and is determined to be well-understood, routine and conventional under step 2B, see at least Hennessy, John L. et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology., 2014. ProQuest Ebook Central, chapter 6 section 6.9 Multithreading: Exploiting Thread-Level Parallelism within a Processor page 609, describes multithreading, wherein the processor must duplicate the independent state of each thread. For example, a separate cope of the register file … are required for each thread. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 9 further recites wherein to apply the reduction operation to the result of the portion of the MM operation, the one or more circuits are to multiply the result of the portion of the MM operation by an auxiliary matrix that comprises at least one of a row of zero elements or a column of zero elements. Such limitation covers mathematical calculations, relationship, and/or formula (e.g., performing reduction on matrix multiplication). The claim does not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two, and provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 10 further recites wherein the one or more circuits are to perform a hierarchical operation of a highest order using a kernel that is different from one or more kernels that are used to perform other hierarchical operations. Such additional element of using different kernel at different hierarchical operation is at most insignificant extra solution activity under step 2A prong two and is determined to be well-understood, routine and conventional under step 2B, see at least Dakkak page 2 section 2 listing 1 illustrates a kernel within a warp level, and section 4.3 page 6 describes grid level reduction involves two kernel launches, thus different kernel is used for different hierarchical. Gonzalo, page 76 right column describes Tangram generates a second kernel launch, at the grid level, or another device function call at the block level, thus at different level or hierarchical, different kernel is used. Mukunoki page 381 describes the use of kernels GEM-V, GEMV-T, and TRMV-LNN for different levels or hierarchical operations. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 11-20 recite system claims having limitations similar to claims 1-10. Thus, they are rejected for the same reasons.
Claims 21-30 recites method claims that would practice on the apparatus claims 1-10. Thus, they are rejected for the same reasons.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUY DUONG whose telephone number is (571)272-2764. The examiner can normally be reached Mon-Friday 7:30-5:30.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
