Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/03/2024 has been entered.
NON-FINAL OFFICE ACTION
This Office Action is a Reissue of U.S. Application No. 12/575,287 (the ‘287 application) now U.S. Patent No. 8,473,223 B2 issued on June 25, 2013 to Leu (the ‘223 patent).
The status of the claims amended on 4/25/2023 is as follows;
Claims 1, 2, 6-11, and 15-22 are pending.
Claims 1, 2, 6-8, 10, 11, and 13-17 are original claims.
Claims 1, 9, 10 and 18 are original amended claims.
Claims 3-5 and 12-14 are canceled.
Claims 19 and 20 are new previously presented claims.
Claims 21 and 22 are new claims.
Claims 1, 2, 6-11, and 15-22 are rejected.
CLAIM INTERPRETATION
During examination, claims are given the broadest reasonable interpretation consistent with the specification and limitations in the specification are not read into the claims. See MPEP § 2111 et seq.
A. Lexicographic Definitions
After careful review of the original specification, the prosecution history, and unless expressly noted otherwise by the Examiner below, the Examiner finds that he is unable to locate any lexicographic definitions (either express or implied) with reasonable clarity, deliberateness, and precision. Because the Examiner is unable to locate any lexicographic definitions with reasonable clarity, deliberateness, and precision, the Examiner concludes that Applicant is not their own lexicographer. See MPEP § 2111.01 IV.
B. ‘Sources’ for the 'Broadest Reasonable Interpretation'
For terms not lexicographically defined by Applicant, the Examiner hereby adopts the following interpretations under the broadest reasonable interpretation standard. In other words, the Examiner has provided the following interpretations simply as express notice of how he is interpreting particular terms under the broadest reasonable interpretation standard. Additionally, these interpretations are only a guide to claim terminology since claim terms must be interpreted in context of the surrounding claim language.1 In accordance with In re Morris, 127 F.3d 1048, 1056 (Fed. Cir. 1997), the Examiner points to these other “sources” to support his interpretation of the claims. Finally, the following list is not intended to be exhaustive in any way:
“Processor” #1
“1: one that processes 2. a: (1) a computer (2) The part of a computer system that operates on data – called also a central processing unit.” Microsoft Press Computer Dictionary, 2nd Edition, Microsoft Press, Redmond, WA, 1994. 2
Contour
1: an outline esp. of a curving or irregular figure : shape also : the line representing this outline 2 : the general form or structure of something. Merriam-Webster’s collegiate Dictionary 10th edition 1997
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 10 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The applicant has amended the term previously at issue to “extracting a contour of the defect from the defect image by cutting defect contour from the defect image [file] through image processing techniques”.
The examiner maintains that “cutting defect contour from the defect image [file] through image processing techniques” is not supported by the specification. It is unclear as to what and how the defect contour is cut from the defect image since image processing techniques are not defined in the specification other than overlaying a defect clip with a design area as explained with respect to the correction of the coordinates detailed below. Accordingly the 35 U.S.C. §112(1st ¶) rejection is maintained.
35 U.S.C. §112(1st ¶) Ariad rejection
Claims 1 and 10 recites computer-implemented functions including, among other limitations, “cutting defect contour from the defect image [file] through image processing techniques”
Applicant(s) is/are respectfully reminded, for computer-implemented functional claims, “examiners should determine whether the specification discloses the computer and the algorithm (e.g., the necessary steps and/or flowcharts) that perform the claimed function in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor invented the claimed subject matter.” MPEP § 2161.01(I).
As an initial matter, the Examiner notes that claims 1 and 10 are an originally-filed and amended claim. However, amended claims 1-10 does not disclose how the “cutting defect contour from the defect image [file] through image processing techniques” themselves, or how the “image processing techniques” itself, is “not supported by the specification” and so does not provide the necessary written description support for pending claims 1 and 10. Accord Ariad, 598 F.3d at 1349 (indicating original claim language does not necessarily satisfy the written description requirement for the claimed subject matter). That is to say, claims 1 and 10 by them self does not provide an algorithm that performs the function “cutting defect contour from the defect image [file] through image processing techniques” in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor invented the claimed subject matter.
Furthermore, Applicant’s specification does not describe an algorithm that performs the function “cutting defect contour from the defect image [file] through image processing techniques” in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor invented the claimed subject matter. For example, Applicant’s specification discloses “.” Spec. C4:L10-26. However, such disclosure is not an algorithm (e.g., the necessary steps and/or flowcharts) that performs the claimed function in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor invented the claimed subject matter.
Applicant is also reminded, “[i]f the specification does not provide a disclosure of the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention including how to program the disclosed computer to perform the claimed function, a rejection under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, for lack of written description must be made.” MPEP § 2161.01(I).
Therefore, because an algorithm for the function “cutting defect contour from the defect image [file] through image processing techniques” is not disclosed in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor invented the claimed subject matter, and in accordance with MPEP § 2161.01, claim 1 and 10 are rejected for lack of written description.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-11 and 13-22 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Nehmadi et al US Patent Application Publication 2008/0295048 (Nehmadi) in view of Nehmadi et al US Patent Application Publication 2006/0269120 (Nehmadi ‘120) in view of U.S. Patent 8,139,849 to Yamaguchi et al which is cited to support the applicant admitted prior art.
In the rejection below claims with similar features are bundled together. For example, the rejection with respect to claim 1 applies equally to claim 10 as well as new claims 21 and 22.
Claim 1, 10, 21 and 22
Claim 1. A computer-implemented method, made by a computer having a processor and a storage device, for utilizing fabrication defect of an article, executed by the processor, the method comprising steps of: See Nehmadi paragraph [0067] and figure 7 that outlines a computer system that executes a set of instructions to perform any of methodologies discussed herein.
obtaining a defect image from a fabrication process for fabricating the article, wherein the defect image comprises a defect and fabricated circuit patterns around the defect; See Nehmadi Figure 1 and paragraphs [0029]-[0038].
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Nehmadi discloses an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data to update the fabrication process or the design (see abstract and para. [0032]) The geometric characteristics include may include, for example, the size of the defects, the volume of the defects, and the location of the defects within the designs on which the defects were found, etc.
obtaining coordinates of the defect from a defect data, wherein the coordinates of the defect is measured by defect scan and inspection tool; Nehmadi Para. [0031] defect map 145 figure 1 defect scan and inspection tool 140 . Nehmadi Para. [0035] discusses geometric characteristics of the individual defect which include size, volume and location.
retrieving a layout of the article comprising design circuit patterns; Nehmadi Para. [0031] design 120 figure 1.
superposing the defect image on the layout according to the coordinates of the defect, wherein correction of the coordinates is achieved by matching the fabricated circuit patterns of the defect image and the design circuit patterns of the layout; ;
Specifically, Nehdami para. [0047] discloses using a CAD program that aligns a defect map and a CAD model to correlate a defect’s position relative to a structure in the design. “By analyzing the neighborhood (the design layout in the area surrounding the defect) of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized into design bins by common structures in which they occur.
Nehmadi discloses that the geographical representations of both of the defect and the design map are known and aligned. This is superposing according to the coordinates of the defect. The examiner maintains that aligning, superposing, overlaying and comparing a defect map clip with a CAD model are all analogous terms. Further, it would have been obvious to one of ordinary skill in CAD and defect analysis to compare structures that have a geographic location using any of aligning, superposing, overlaying or comparing since the terms are analogous.
extracting a contour of the defect from the defect image by cutting defect contour from the defect image thru image processing techniques; Para.[0047]-[0049] and figure 4A. The ‘223 specification states that following;
The extraction of the contour of defect 101 is achieved by either cutting the contour of defect 101 from the defect image 100 by some image processing techniques, or analyzing overlaps and differences between the fabricated circuit patterns 102 and the design circuit patterns 201.
‘223 specification C4:10-20
In this case clips may be generated from a CAD model and the area surrounding the defect aligned and compared. For example, area "clips" can be generated from the CAD model for the areas surrounding each defect.” This is a defect clip which is interpreted as a cutting. “A clip may be a rectangle of a predetermined size centered on the defect. The clips are compared to one another to identify matching structural elements.” That is defect clips may be compared to one another to identify matching structural elements. The term defect clip is not used in Nehdami. However, Nehdami points to US PUB 20060269120 (Nehdami ‘120), which is incorporated by reference, to discuss structural binning in order to further explain figure 4A. Nehdami ‘120 discloses the generation of defect clips in figure 2 and para. [0015], [0045]-[0047].
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Specifically, Nehdami ‘048 para. [0047] discloses using a CAD program that aligns a defect map and a CAD model to correlate a defect’s position relative to a structure in the design. By analyzing the neighborhood (the design layout in the area surrounding the defect) of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized into design bins by common structures in which they occur. For example, area "clips" can be generated from the CAD model for the areas surrounding each defect. A clip may be a rectangle of a predetermined size centered on the defect. The clips are a combination of the defect map and the CAD model and include the geometric characteristics of the defect. Therefore, Nehdami also discloses the amended subject matter of “after the correction of coordinates”
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Nehmadi ‘120 Fig. 2
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Nehmadi ‘120 Fig. 3
Therefore, the examiner finds that the combination of Nehmadi with Nehmadi ‘120 disclose extracting a contour of the defect from the defect image by cutting defect contour from the defect image file by analyzing overlaps and differences between the fabricated circuit patterns 102 and the design circuit patterns 201 and making a defect clip and storing a defect clip. This applies to all independent claims inclusive of new claims 21-22. Additionally, as admitted by the applicant in the 4/15/2024 remarks, US patent 8,139,847 teaches a well known image processing technique/system capable of extracting a portion of a defect from an image. The examiner finds extracting to be cutting defect tour from the defect image file with is applicant admitted prior art.
One would be motivated to combine the references in that they are in the same field of invention, Nehmadi ‘048 incorporates by reference Nehmadi ‘120 and the combination of the references would yield predictable results since one of ordinary skill would understand how to use well known image processing techniques taught by Nehmadi ‘048 and ‘120 and what is applicant admitted prior art. with respect to by cutting defect contour from the defect image thru image processing techniques.
superposing the contour of the defect on the layout according to the coordinates of the defect after the correction of the coordinates wherein the design circuit patterns of the layout are overlaid with the fabricated circuit patterns of the defect; and
The examiner finds that the applicant argues that the feature that cannot be found in the Nehmadi reference with respect to “cutting the defect contour from the defect image through image processing techniques” . The examiner maintains that this is a well-known feature that is known to one of ordinary skill in the art as described in 8,139,847 to Yamaguchi. The ‘847 patent teaches the following;
Other than that, it is possible to configure to extract (automatically extract by a program of the controlling means 118) a defect portion 1824 by the image processing, by specifying the defect portion 1824 to be taught (1825, 1826), thereby selecting a more correct defect area 1827.
‘847 C14:L7-11
The ‘847 reference disclose a program to extract a defect portion using a controlling means but does not describe how this is done or provide an algorithm. The examiner finds that since this process/program is well-known in the art then “cutting the defect contour from the defect image thru image processing techniques” is applicant’s admitted prior art.
See Nehmadi para. [0031] where the defect map may be correlated with the design, para.[0037] states that the geometric characteristics may include, for example, the size of defects, he volume of defects, and the location of defects identified on a defect map, and para. [0047] that discloses aligning a defect map with a CAD model to correlate a defect’s position relative to a structure in the design. Nehmadi discloses that the geographical representations of both of the defect and the design map are known and aligned. This is superposing according to the coordinates of the defect. The examiner maintains that aligning, superposing, overlaying and comparing a defect map clip with a CAD model clip are all analogous terms. Additionally, this teaching equally applies to the amended subject matter of “after the correction of the coordinates” since the defect map is aligned with the design map or “design circuit patter”. Further, it would have been obvious to one of ordinary skill in the CAD and defect analysis to compare structures that have a specific geographic location using any of aligning, superposing, overlaying or comparing since the terms are analogous.
determining whether the defect causes an open failure or a short failure on the layout by analyzing overlaps between the contour of the defect and the design circuit patterns, wherein the defect causes the open failure when the contour of the defect intercepts one of the design circuit patterns; the defect causes the short failure when the contour of the defect bridges two of the design circuit patterns. See para. [0051]-[0066] and figures 5 and 6 which discusses bridging and open circuit defects.
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Claim 2 and 11.
Claim 2. The computer-implemented method according to claim 1, wherein after the step of "retrieving a layout comprising design circuit patterns," the method further comprises a step of: correcting the coordinates of the defect by matching the fabricated circuit patterns of the defect image and the design circuit patterns of the layout.
To determine the definition of “correcting the coordinates” the examiner turns to the specification of the ‘223 patent where Leu refers to a related patent application 12/318,974 by the same inventor which is now Patent 8,095,895. None of the application or the patent is incorporated by reference. The ‘895 patent states the following;
Next, the inspection image 10 and the design layout 20 will be matched for correcting the coordinates of the defects 11, 12, and 13 on the design layout 20. Although the defect scan and inspection tool has measured the coordinates of the defects 11, 12, and 13, those are not accurate. Thus, it is meaningless to use the wrong coordinates to locate the defects 11, 12, and 13 on the design layout 20 and to diagnose the defects 11, 12, and 13. Therefore, the wrong coordinates of the defects 11, 12, and 13 need to be corrected.
Please refer to the FIG. 4, to solve the above mentioned issue, the boundaries of the fabricated patterns 14 of the inspection image 10 are aligned with those of the conductive regions 21 of the design layout 20, thereby the accurate coordinates of the defects 11, 12, and 13 on the design layout 20 can be found. (Step S104).
‘985 patent 3:30-45 emphasis added by examiner
As noted above Nehmadi para. [0031] discloses where the defect map may be correlated with the design and para. [0047] that discloses aligning a defect map with a CAD model to correlate a defect’s position relative to a structure in the design by aligning the clips. As best that can be determined by the examiner this is correcting the coordinates.
Claim 4 and 13
Claim 4. The computer-implemented method according to claim 3, wherein the systematic defect comprises: necking, bridging, missing, or collapsing.
Nehmadi Para.[0051]-[0052] discloses bridging.
Claim 5 and 14
Claim 5. The computer-implemented method according to claim 3, wherein the process related defect comprises: residue, scratch, corrosion, pitting, haze, water mark, peeling, photo resist lifting, or bubble.
Nehmadi Para.[0005] and [0021] discloses particles, open lines, shorts between lines, loose surface particles, loose fibers and microscopic particles which are residue.
Claims 6, 7, 8 and 15, 16, 17
Claim 6. The computer-implemented method according to claim 1, further comprising a step of: repeating the steps for different defect images from the fabrication process.
Claim 7. The computer-implemented method according to claim 6, further comprising steps of: obtaining a new layout of a new article, wherein the new layout comprises design circuit patterns; superposing the contours of the defects on the new layout according to the coordinates of the defects respectively; and determining whether each of the defects causes the open failure or the short failure on the new layout by analyzing overlaps between the contour of each of the defects and the design circuit patterns of the new layout.
Claim 8. The computer-implemented method according to claim 7, wherein at the step of "superposing the contours of the defects on the new layout according to the coordinates of the defects respectively" the method further comprises steps of: extracting local layouts from the new layout; and superposing the contours of defects on the local layouts respectively.
With respect to claims 6-8 and 15-17 that repeat the steps of claim 1 for a new layout of a new article the inspection process 140 of Nehmadi is used for all of the defects identified in the process. Figure 1 outlines the method starting with the fabrication 130 to the inspection process 140 to the inline defect analysis process 150 which send the defect to be reviewed 160 and adjustments are then made to the design or the fabrication process and the process is then repeated.
Para. [0032] states the automated defect review process 160 may extract information leading to modifications to improve the design 165 or adjust the fabrication process to improve the process. The new design would still be subject to the inspection process.
See Nehmadi para. [0031] where the defect map may be correlated with the design and para. [0047] that discloses aligning a defect map with a CAD model to correlate a defect’s position relative to a structure in the design. See para. [0055]-[0065] and figures 4a, 5 and 6.
[0032] As illustrated, embodiments of the present invention may provide an automated defect review process 160. The automated defect review process 160 may process a relatively large amount of defect data in an effort to extract information that may be used to gain insight into design process interaction (DPI), that is, the sensitivity of particular designs to process variations. For example, the automated defect review process 160 may extract information leading to modifications to improve the design 165 or adjusting the fabrication process to improve the process 175. Since the inspection process 140 may identify tens of thousands to hundreds of thousands of defects for the automated defect review process 160 to review, the inline defect analysis process 150 may parse the defects identified by the inspection process 140 to identify a subset of defects that warrant further investigation.
Nehmadi para. [0032] emphasis added by the examiner
Claim 9 and 18.
Claim 9. The computer-implemented method according to claim 1, further comprises a step of combining a defect diagnosis with Design of Experiment, process split of module, or integration process parameters, wherein the step comprises;
The ‘223 patent describes the Design of Experiment, process split of module, or integration parameters “so as to find some rules to modify the layout, or design a new layout, for reducing the failure and increasing the yield.” (see ‘223 5:1-17). Nehmadi para. [0029] FIG. 1 illustrates an exemplary workflow for semiconductor design and fabrication, in accordance with embodiments of the present invention. As illustrated, wafers 110 may be produced in accordance with a design 120, via a fabrication process 130 controlled by a set of process parameters 135. These process parameters may include a wide variety of parameters, for example, lithography parameters, etch parameters, and any other type of parameters.
[0032] As illustrated, embodiments of the present invention may provide an automated defect review process 160. The automated defect review process 160 may process a relatively large amount of defect data in an effort to extract information that may be used to gain insight into design process interaction (DPI), that is, the sensitivity of particular designs to process variations. For example, the automated defect review process 160 may extract information leading to modifications to improve the design 165 or adjusting the fabrication process to improve the process 175. Since the inspection process 140 may identify tens of thousands to hundreds of thousands of defects for the automated defect review process 160 to review, the inline defect analysis process 150 may parse the defects identified by the inspection process 140 to identify a subset of defects that warrant further investigation.
Nehmadi Para [0032] emphasis added by the examiner
Integration process parameters are defined in the ‘223 patent 5:1-17 as defect type, yield, composition and distribution. Nehmadi para. [0038]-[0041] disclose defect yield and defect types that the geographic characteristics may include the size of a defect, volume of a defect, and a location of a defect which equate to defect composition and distribution.
extracting diagnosis result of the defect;
Figure 2A and the description of the inline defect analyzer discloses how each defect is processed in order to get rid of historical nuisance defects and process defects that focuses on defects with a higher yield impact loss. See para. [0036]-[0038].
determining a type of the defect, wherein the type comprises: random particle defect, systematic defect, and process related defect;
Para. [0042] disclose systematic defects are defects conditioned by the specifics of a design layout or the fabrication equipment and occur in specific design elements which are systematic defects and process related defects. Random particle defects and systematic defects are also described in paragraphs [0004]-[0005] and [0020]-[0021], [0051]-[0052]. Defects are determined in the defect review process 160.
extracting the Design of Experiment, process split of module, or integration process parameters;
See Nehmadi para [0032] For example, the automated defect review process 160 may extract information leading to modifications to improve the design 165 or adjusting the fabrication process to improve the process 175.
performing data analysis between the diagnosis result and the Design of Experiment, process split of module, or integration process parameters; and
concluding the correlation between defect and the module or integration process parameters, and optimize for minimum defect yield impact.
Figure 2A and the description of the inline defect analyzer discloses how each defect is processed in order to get rid of historical nuisance defects and process defects that focuses on defects with a higher yield impact loss in order to minimize impact. See para. [0036]-[0038]. The inline defect analyzer 206 may be a SEMVision inspection system that performs data analysis using the processes describe above to improve the design or the fabrication process.
New Claims 19 and 20.
19. (new) The computer-implemented method according to claim 1, further comprising the steps of:
correlating the defect with a process condition;
modifying the process condition to prevent the defect; and
fabricating a wafer using the modified process condition.
20. (new) The method according to claim 10, further comprising the steps of:
correlating the defect with a process condition;
modifying the process condition to prevent the defect; and
fabricating a wafer using the modified process condition.
Please see the rejection above with respect to claims 9 and 18 and see Nehmadi para. [0032].
Figure 1 outlines the method starting with the fabrication 130 to the inspection process 140 to the inline defect analysis process 150 which send the defect to be reviewed 160 and adjustments are then made to the design or the fabrication process and the process is then repeated.
Nehmadi para. [0029] FIG. 1 illustrates an exemplary workflow for semiconductor design and fabrication, in accordance with embodiments of the present invention. As illustrated, wafers 110 may be produced in accordance with a design 120, via a fabrication process 130 controlled by a set of process parameters 135. These process parameters may include a wide variety of parameters, for example, lithography parameters, etch parameters, and any other type of parameters.
Para. [0032] states the automated defect review process 160 may extract information leading to modifications to improve the design 165 or adjust the fabrication process adjusting the parameters disclosed above to improve the process. The new design would still be subject to the inspection process.
Response to Arguments
Applicant's arguments filed 12/3/2024 have been fully considered but they are not persuasive.
The 35 U.S.C. §112 rejection
Applicants remarks on pages 8 states that In view of the foregoing amendments, it is believed that the disclosure would reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA , the inventor(s), at the time the application was filed, had possession of the claimed invention. Reconsideration and withdrawal of the 35 USC 112 rejection are respectfully requested.
The amendment to the claim step of “extracting a contour of the defect from the defect image by cutting defect contour from the defect image [file] through image processing techniques”
The examiner find this is supported in the specification C4:L46-56 this discloses the following image processing technique.
Furthermore, in some cases, the coordinates of the defect 101 measured by the defect scan and inspection tool is not accurate, so it needs to be corrected, otherwise the determination of failure would be wrong. The correction of the coordinates can be achieved by matching the fabricated circuit patterns 101 of the defect image 100 and the design circuit patterns 201 of the layout 200, so the correction is performed after obtaining the layout 200, i.e. the step S107. The detailed algorithm for correcting the coordinates can refer to a related patent application, which application Ser. No. 12/318,974, of the same inventor to this invention.
‘223 C4:L46-56 emphasis added by the examiner
The PG pub of 12/318,974 is US PG Pub 2010/0180239 which states that the correction is done as described in paragraph [0029] below.
[0029] Please refer to the FIG. 4, to solve the above mentioned issue, the boundaries of the fabricated patterns 14 of the inspection image 10 are aligned with those of the conductive regions 21 of the design layout 20, thereby the accurate coordinates of the defects 11, 12, and 13 on the design layout 20 can be found. (Step S104).
‘230 para. [0029]
The examiner notes that if the result of correction of the coordinates is matching a defect clip with the design layout which aligns the clips. There is no image processing technique that is disclosed that cuts the contour of the defect and as such the 35 U.S.C. §112(1st ¶) rejection is maintained.
The 35 U.S.C. §103 rejection
The applicant argues the 35 U.S.C. §103 rejection on pages 8-12 of the 12/3/2024 remarks that Nehmadi ‘048 and Nehmadi ‘012 do not disclose the following:
Applicant agrees that either a clip taught by Nehmadi or by Nehmadi'120 is in rectangle shape, and relevant drawings and illustration are referred to FIG.4A and Para. [0047] in Nehmadi and FIG.4, FIG.5 and Para. [0046]-[0049] in Nehmadi' 120, respectively. In contrast, clip in rectangle shape raises issues of wrong determination, which would be definitely like to be resolved by the present invention, please see '223 patent C 1: L 26-3 7 as follows:
to dig out.
Some foundry fabs have considered the influence of defect to product yield. The foundry fabs used the defect area, which is generated from a defect scan and inspection tool, to determine whether the defect causes a killing failure and reduces the product yield. But the defect area represents, a defect by a rectangular shape, which is usually larger than actual defect shape. This results in a wrong determination.
The examiner is not persuaded that a clip in a rectangle shape would raise issues of wrong determination since the correction of coordinates step aligns the defect clip and the design clip. Additionally, the term “wrong determination” does not explain what is wrong and/or how a determination is made. Accordingly the above argument is not persuasive.
Therefore, there is a need for the design house or the foundry fab to accurately determine whether defects, generated during fabricating stage, cause failure or not, so as to further estimate product yield.
For Nehmadi, the result of matching and aligning of two clips is used to categorize defects into same or different structural defect bin (see Para. [0047]), so a method for determining these categorized defects are likely to be nuisance defects (see FIG.4B and Para. [0050], as well as FIG.4C and Para. [0054]) is taught by Nehmadi. In the method taught by Nehmadi, a criticality factor (CF) is introduced to help determine the impact of a defect on the yield, and the CF represents a probability of a random defect with a certain size or volume to kill a device (see Para. [0051 ]). Nehmadi further discloses a method for calculating a defect criticality factor (CF) (see Para. [0059]-[0061]). Please see the expression for CF (see Para. [0061]) as follows:
…
According to illustration aforementioned, the teaching of Nehmadi is to categorize defects with comparing clips in rectangle shape and determine nuisance defects with calculation of criticality factor (CF) in statistics, where both the categorizing step and result taught by Nehmadi fails in the determination of detects impact on circuit, and the criticality factor taught by Nehmadi is just a probability value. No matter how high the probability from criticality factor taught by Nehmadi is, the result is acquired from measurement based on statistics and dose not represent true short or open failure caused by the defect existence on the article.
However, the method in amended Claim 1 is capable of accurately determining whether any defect causes a failure on the article during the fabrication process (see '223 patent C 1: L46-
49). The actual contour of the defect is extracted from the defect image, also recited in amended Claim, so the determination of failure for the defect is more accurate (see '223 patent C2: L 16-18).
Moreover, on page 7-8 of Office Action, the Examiner is also opinion that "Nehmadi discloses an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data to update the fabrication process or the design (see abstract and para. [0032 }) The geometric characteristics include may include, for example, the size of the defects, the volume of the defects, and the location of the defects within the designs on which the defects were found, etc."
It is kindly noted that the geometric characteristics are totally different from the contour of the defect extracted from the defect image claimed in amended Claim 1. In Para. [0035], Nehmadi discloses defects are identified on the wafers and defect data are collected during the inspection process, and the geometric characteristics may include, for example, the size of defects, the volume of defects, and the location of defects within the designs on which the defects were found, etc. Besides, in Para. [0006]-[0007], Nehmadi discloses using inspection systems to detect defects is only the first step in managing defectivity. Inspection equipment of optical inspection is generally pushed to its sensitivity limit in order to detect sub-micron sized defects-is often plagued with many false alarms or nuisance defects, as they are known, which serve to frustrate any attempts to reliably observe true defects or sources of defects.
Similarly, as discussed in '223 patent C3: L 34-42, the defect scan and inspection tool produces defect image and defect data for each of the defects. The defect data includes product name, defect process stage, defect size, defect coordinates, lot number, and wafer number. Accordingly, Applicant agrees the teaching of geometric characteristics for defects that are measured or acquired during inspection process, regardless in Nehmadi or '223 patent disclosures. However, since geometric characteristics result from optical inspection equipment, the geometric characteristics taught by Nehmadi are totally different from the contour of the defect extracted from the defect image claimed in amended Claim 1.
It is unclear to the examiner why the geometric conditions (GC) are totally different from the contour of the defect in that all of the information about the defect is contained within the GC. Furthermore, para [0006[-[0007] are mischaracterized above in that instead of using an optical device the system of Nehmadi uses a Scanning electron microscope. Accordingly these arguments are not persuasive.
Amended Claim 1 recites the extracting a contour of the defect from the defect image by cutting defect contour from the defect image through image processing techniques, as well as amended Claim 10, or analyzing overlaps and differences between the fabricated circuit patterns and the design circuit patterns in Claims 21 and 22. Thus, the extracted contour of the defect is a contour in actual length and curvature/arc for the defect on the article. Because of the actual contour extracted out in amended Claim 1, it is used to, by cutting defect contour from the defect image through image processing techniques, as well as amended Claim 10, or analyzing overlaps and differences between the fabricated circuit patterns and the design circuit patterns in Claims 21 and 22, determine whether the defect causes an open failure or a short failure on the layout. The result of open or short failure determined by the method in amended Claim is a definite result, instead of probability through Cf-like statistic factor like Nehmadi's disclosure. Since the categorization of defects with comparing clips in rectangle shape and determination of nuisance defects with Cf (criticality factor) are taught by Nehmadi, it is neither explicitly nor implicitly obvious for one of ordinary skilled in the art to acquire the method in amened Claim 1 by modifying the teaching of Nehmadi.
The examiner maintains that Nehdami discloses analyzing overlaps and differences between the fabricated circuit patterns and the design circuit patterns as disclosed above with respect to the correction of the coordinates by overlapping the defect clips with the design in order to detect all defects. Then the random defects or the critical defects warrants further review by the defect review tool. With respect to cutting the defect contour from the defect image using image processing techniques the examiner relies on 8,139,847 to Yamaguchi. The ‘847 patent teaches the following;
Other than that, it is possible to configure to extract (automatically extract by a program of the controlling means 118) a defect portion 1824 by the image processing, by specifying the defect portion 1824 to be taught (1825, 1826), thereby selecting a more correct defect area 1827.
‘847 C14:L7-11
The ‘847 reference disclose a program to extract a defect portion using a controlling means but does not describe how this is done or provide an algorithm. The examiner finds that since this process/program is well-known in the art then “cutting the defect contour from the defect image thru image processing techniques” is applicant’s admitted prior art.
The examiner maintains that the combination of Nehmadi ‘048, Nehmadi ‘120 and Yamaguchi teach all of the claim elements and as such the above arguments are not persuasive.
The examiner notes that Nehmadi ‘048 discloses the alignment of the default area with the design of the wafer. Nehmadi ‘120 is used to disclose defect clip and align the defect clip to the design area of the wafer. The use of binning is not the only teaching of Nehmadi ’120. The binning of defects with the high CF are further analyzed for additional issues such as open or short circuits. See para. [0033] that states “any defect identified by only one of the methods via simulation or inspection) may be categorized appropriately for further analysis. The examiner agrees that Nehmadi ‘120 discloses defect binning. However that is not the only teaching of Nehmadi ’120. Nehmadi ‘048 detect defects in order to correct them [0004] and Nehmadi ‘120 discloses the use of defect clips and the automated categorization allows critical structures to be identified for further investigation into the relationship of design features and/or process parameters (design process interaction) that cause the corresponding defects. [0032].
Nehmadi ‘048 discloses below how a defect is assigned a CF and how that CF is translated into an open or short condition for further review. Accordingly, the rejection is maintained.
[0051] Some random defects may affect the functionality of a design. However, as earlier noted, a random defect may have little or no impact on the yield and conversely, a random defect may have a significant impact on yield. At block 422, a criticality factor (CF) is calculated for each random defect to help determine the impact of a random defect on the yield. In other words, a criticality factor (CF) is calculated to help identify which random defects are likely to be nuisance defects. In particular, the CF represents a probability of a random defect with a certain size or volume to kill a device. Random defects with a low probability to kill a device are nuisance defects. The CF may be calculated using the relevant design data, e.g., the layout of the relevant design on which the random defect is found and the geometric characteristics of the individual random defects, such as the size or volume of the defect. In one embodiment, a CF is calculated by determining a probability of the random defect to bridge two lines (cause a shorting failure) and a likelihood of the defect to open a line (cause an open failure). Such failures affect the functionality of a design. One embodiment of a CF calculation algorithm will be discussed in more detail below in conjunction with FIG. 5.
[0052] For example, random defects likely to bridge two lines or open a line have high CF values and are identified as critical defects. Whereas, random defects that have a low probability to cause a short failure or open failure have lower CF values and are identified as nuisance defects. At block 424, since the random defects with higher CF values are likely to affect the functionality of a design, they are selected to be sampled for review. In one embodiment, the random defects may be selected if the CF exceeds a threshold or satisfies some other requirements.
The Examiner maintains that the design layout and a defect map identifying the locations of the defect are taught by Nehmadi. This is a layout compared to a defect map that has geometric characteristics including volume, depth and location . As disclosed above, Nehmadi ‘048 in para. [0047] discloses comparing the layout and the defect map by aligning clips. The Examiner agrees that the “aligning step” is the same as the step of “superposing the defect image on the layout according to the coordinates of the defect". However, there are no argument presented as to why these two steps are “…not the same as the following step as "superposing the contour of the defect on the layout...". See the following paragraphs that disclose and design layout and a defect map.
[0034] As earlier noted, a wafer may be produced according to a wafer design via a fabrication process controlled by a set of process parameters. Wafer design data may be stored in a design data database 202. The design data database 202 may store design data such as the wafer design layout, the routing information for the design layout, etc. In one embodiment, the design data may be in the form of a computer automated design (CAD) model of the design, for example, in a graphics form (such as GDS, GDS-II, and the like). The design data database 202 may also store historical design data for previously designed wafers. The inline defect analyzer 206 receives the design data from the design data database 202 to correlate the design data to defect data received from defect reporter 204.
[0035] Defect reporter 204 may be part of a defect inspection system (not shown) (e.g., a defect inspection system performing the inspection process 140 in FIG. 1). As earlier described, during the fabrication process wafers may not be formed to exactly match the design. Hence, one or more wafers undergo a defect inspection process to determine how the actual wafers vary from the design. During the inspection process, defects are identified on the wafers. Defect reporter 204 collects defect data (e.g., the geometric characteristics of individual defects) for the identified defects. The geometric characteristics may include, for example, the size of defects, the volume of defects, and the location of defects within the designs on which the defects were found, etc. In one embodiment, as part of the inspection process, a defect map identifying the locations of defects in the wafers may be generated. The defects indicated in the map may be, for example, locations of elements (e.g., lines, holes/vias) formed in the wafers where crucial dimensions are outside a specified range. In one embodiment, the defect reporter 204 may collect the geometric characteristics of the defects from the defect map. The defect reporter 204 may also store historical defect data for defects previously identified during previous wafer processing.
Nehmadi para. [0034]-[0035] emphasis added by the examiner.
The examiner maintains that the CAD program used by Nehmadi such as GDS is also used by the ‘223 patent. Additionally, Nehmadi collects the geometric characteristics of the individual defects and has a defect map that identifies the locations of the defects. Geometric characteristics include coordinates of the defects. The examiner agrees that 8,139,847B2 (filing date: 2009/02/13), discloses “it is possible to configure to extract (automatically extracted by a program of the controlling means 118) a defect portion 1824 by the image process, by specifying the defect portion 1824 to be taught (1825, 1826), thereby selecting a more correct defect data (col. 14, lines 7-11) (See 4/15/24 Rem pp 10). However, the ‘847 patent does not disclose how this is done or provide an algorithm. Since Nehmadi discloses the geometric characteristics of the individual defects it would be known to use a well-known technique such as that described in the ‘847 patent in order to perform “cutting the contour of defect 101 from the defect image file”. This feature is applicant admitted prior art as outlined above.
The applicant argues on pages 11-13 that Nehmadi does not disclose the following;
The rejection is respectfully traversed on the basis that the disclosure of Nehmadi ‘048 in view of Nehmadi ‘120 did not disclose “extracting a contour of the defect from the defect image by cutting defect contour from the defect image file” and “superposing the contour of the defect on the layout according to the coordinates of the defect, wherein the design circuit patterns of the layout are overlaid with the fabricated circuit patterns of the defect” as recited in Claims 1 and 10.
The examiner maintains that superposing and aligning are terms that are used to mean the same thing as evidenced in paragraph [0047]. Binning may involve aligning a defect map and a CAD model to correlate a defect’s position relative to a structure in the design. Clips are defined from the CAD model and defect maps and compared or “aligned” and then placed in a structural BIN for later analysis. The defect map has the geographical coordinates of the defect as disclosed above that include the size of defects, the volume of defects, and the location of defects.
The CAD model of Nehmadi ‘048 can be in GDS which is the same format taught in the ‘233 patent as disclosed above. The discussion with respect to designed based binning has no bearing on how the clips are compared in paragraph [0047] reproduced below.
[0047] FIG. 4A illustrates grouping defects based on design-based binning in accordance with one embodiment of the invention. Design-based binning is the grouping of defects based on a defect's location on a wafer and relation to design elements (device structures). Binning may involve aligning a defect map and CAD model to correlate a defect's position relative to a structure in the design. As previously described, due to the repetitive nature of typical device layouts, a systematic defect mechanism will typically trigger multiple defects on various locations across a die (as well as across common location on multiple dice on a wafer). By analyzing the neighborhood (the design layout in the area surrounding the defect) of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized into design bins by common structures in which they occur. For example, area "clips" can be generated from the CAD model for the areas surrounding each defect. A clip may be a rectangle of a predetermined size centered on the defect. The clips are compared to one another to identify matching structural elements. For example, if two clips can be aligned, they are added to the same structural defect bin. By categorizing defects into structural bins, it is thus possible to track the number of defects associated with each corresponding structure.
Nehmadi ‘048 [0047] emphasis added by the examiner
The applicant argues that the addition of Nehmadi ‘120 discloses a clip aligned to a clip instead of a clip aligned to a CAD model. The examiner added Nehmadi ‘120 because the reference uses the term “defect clip” as outlined in the rejection maintained above.
Specifically, Nehdami ‘048 para. [0047] discloses using a CAD program that aligns a defect map and a CAD model to correlate a defect’s position relative to a structure in the design. By analyzing the neighborhood (the design layout in the area surrounding the defect) of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized into design bins by common structures in which they occur. For example, area "clips" can be generated from the CAD model for the areas surrounding each defect. A clip may be a rectangle of a predetermined size centered on the defect. The clips are a combination of the defect map and the CAD model and include the geometric characteristics of the defect.
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Nehmadi ‘120 Fig. 2
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Nehmadi ‘120 Fig. 3
Therefore, the examiner finds that the combination of Nehmadi ‘048 with Nehmadi ‘120 and Yamaguchi disclose extracting a contour of the defect from the defect image by cutting defect contour from the defect image through image processing techniques and additionally by analyzing overlaps and differences between the fabricated circuit patterns 102 and the design circuit patterns 201 and making a defect clip and storing a defect clip.
The examiner recognizes that the binning issue is different than the aligning of the defect image and the cad map but does not detract from the fact that the defect map and the CAD model are aligned.
The applicant argues that Nehmadi ‘048 and Nehmadi ‘120 do not achieve the objective as determining whether the defect causes an open failure or a short failure on the layout by analyzing overlaps between the contour of the defect and the design circuit patterns, wherein the defect causes the open failure when the contour of the defect intercepts one of the design circuit patterns; the defect causes the short failure when the contour of the defect bridges two of the design circuit patterns as recited in claims 1 and 10.
As discussed above, Nehdami discloses aligning the contour of the defect on the layout according to the coordinates of the defects and further determining if the defect causes a short or open condition as described in Nehmadi ‘048 figure 5 and the relative discussion in the specification para [0058]-[0059]. The examiner notes that this figure and the specification while present in every rejection have not been addressed by the applicant.
Therefore, the examiner finds that the 35 U.S.C. §103 rejection is maintained and Nehmadi ‘048 in view of Nehmadi ‘120 and Yamaguchi does disclose “extracting a contour of the defect from the defect image by cutting defect contour from the defect image file”. Yamaguchi. The ‘847 patent teaches the following;
Other than that, it is possible to configure to extract (automatically extract by a program of the controlling means 118) a defect portion 1824 by the image processing, by specifying the defect portion 1824 to be taught (1825, 1826), thereby selecting a more correct defect area 1827.
‘847 C14:L7-11
Therefore, ‘847 reference disclose a program to extract a defect portion using a controlling means but does not describe how this is done or provide an algorithm. The examiner finds that since this process/program is well-known in the art then “cutting the defect contour from the defect image thru image processing techniques” is applicant’s admitted prior art.
Therefore, using applicant’s admitted prior art of Yamaguchi and “superposing the contour of the defect on the layout according to the coordinates of the defect, wherein the design circuit patterns of the layout are overlaid with the fabricated circuit patterns of the defect” and that as recited in Claims 1, 10, 21 and 22. Additionally the combination of references determine whether the defect causes an open failure or a short failure on the layout by analyzing overlaps between the contour of the defect and the design circuit patterns, wherein the defect causes the open failure when the contour of the defect intercepts one of the design circuit patterns; the defect causes the short failure when the contour of the defect bridges two of the design circuit patterns as recited in the independent claims.
Conclusion
A shortened statutory period for reply to this Non-final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the non-final rejection. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to JOHN M. HOTALING II whose telephone number is (571) 272-4437. The Examiner can normally be reached 7:30 am to 4 pm ET, Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Andrew J. Fischer can be reached on (571) 272 6779. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/JOHN M HOTALING II/Reexamination Specialist, Art Unit 3992
Conferees:
/C. Michelle Tarae/Reexamination Specialist, Art Unit 3992
/ANDREW J. FISCHER/Supervisory Patent Examiner, Art Unit 3992
1 While most interpretations are cited because these terms are found in the claims, the Examiner may have provided additional interpretations to help interpret words, phrases, or concepts found in the interpretations themselves, the '223 Patent, or in the prior art.
2 Based upon the Original Disclosure, the art of record, and the knowledge of one of ordinary skill in this art as determined by the factors discussed in MPEP §2141.03 (where practical), the Examiner finds that the Microsoft Press Computer Dictionary is an appropriate technical dictionary known to be used by one of ordinary skill in this art. See e.g. Altiris Inc. v. Symantec Corp., 318 F.3d 1363, 1373 (Fed. Cir. 2003) where the Federal Circuit used the Microsoft Press Computer Dictionary (3d ed.) as “a technical dictionary” to define the term “flag.” See also In re Barr, 444 F.2d 588 (CCPA 1971)(noting that its appropriate to use technical dictionaries in order to ascertain the meaning of a term of art) and MPEP §2173.05(a) titled “New Terminology.”