Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other references: Loh (US 20130297906); Kashyap (US 20160162186)
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 9, 10, 11, 16, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Gavens (US 20190294553) and in view of Brenner (US 20030110204) and further in view of Kadem (US 9098203)
Claim 1. Gavens553 discloses A method (e.g., a method for use by a data storage controller) , comprising:
determining a number of commands included in a queue of a plurality of queues of a memory die of a memory sub-system, each command being associated with a respective operation to be performed on the memory sub-system (e.g., determining a number of entries in a memory access queue associated with a memory device, 0008, 0044; die manager to control access to the multiple NAND dies, 0046; assessing a fill status of a memory access queue, 0005),
assigning a command to the queue of the plurality of queues based at least in part on the number of commands that are included in the queue (eg., determination may be made based on the number of entries in the corresponding queues 202.sub.1-N, with cached commands used for a particular die if the number of entries in the corresponding queue exceeds the predetermined queue threshold value (T), and non-cached commands used for a particular die otherwise (e.g. if the number of entries for the corresponding queue is less than or equal to T). One or more queue entry/threshold comparators 210 may be used to compare the queue entry count for a particular queue against the queue threshold value (T). , 0048).
Gavens553 does not disclose, but Brenner discloses
by one or more controllers; by the one or more controllers located external to the memory die (eg., 0042 Fig 1 - The load balancing may be performed by the dispatcher 150.) ;
wherein each queue of the plurality of queues is associated with a respective priority level and is configured to maintain a respective set of commands to be performed on the memory sub-system; and the respective priority level of the queue of the memory die relative to a respective priority level of at least one other queue of the memory die; issuing one or more commands from the respective sets of commands of the plurality of queues based at least in part on the respective priority levels (eg., [0034] The threads in a run queue (local and global) may have priorities associated with them. The run queue maintains the priority information of the highest waiting thread on the run queue in a run queue structure. The dispatcher 150 uses this priority information to make decisions of which run queue to search for the next thread to dispatch; 0048 - he CPUs and corresponding local run queues that are searched are restricted to those associated with the node to which the existing process' threads were assigned).
the plurality of queues located on the memory die and the one or more controllers located external to the memory die, (eg., 0058 - her run queues assigned to the node for processing on the potentially idle CPU. The dispatcher 150 scans the local run queues of the node to which the potentially idle CPU is assigned for a local run queue);
level of the queue relative to the respective priority level of the at least one other queue of the memory die and on the number of commands in the queue exceeding a threshold number of commands (eg., 0010 - load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced ; 0066 - steal threshold is a fraction of the smoothed average load factor on all the local run queues in the node. This load factor is determined by sampling the number of threads on each local run queue )
transferring by the one or more controllers located external to the memory die, one or more commands from the queue of the plurality of queues of the memory die to a global pool of commands associated with the one or more controllers according to an order that is based at least in part on the respective priority level (eg., [0042] Threads are added to the global run queue based on load balancing among the nodes 120-140 and the CPUs 111-117. The load balancing may be performed by the dispatcher 150. Load balancing includes a number of methods of keeping the various run queues of the multiple run queue system 100 equally utilized; [0034] The threads in a run queue (local and global) may have priorities associated with them.);
and on the number of commands in the queue exceeding a respectiv4e threshold number of commands for the queue, wherein each queue of the plurality of queues of the memory die is associated with a respective threshold number of commands (eg., [0058] If a CPU is about to become idle, the dispatcher 150 attempts to "steal" threads from other run queues assigned to the node for processing on the potentially idle CPU. The dispatcher 150 scans the local run queues of the node to which the potentially idle CPU is assigned for a local run queue that satisfies the following criteria: [0059] 1) the local run queue has the largest number of threads of all the local run queues of the node; [0060] 2) the local run queue contains more threads than the node's current steal threshold (defined hereafter); [0061] 3) the local run queue contains at least one unbound thread; and [0062] 4) the local run queue has not had more threads stolen from it than a maximum steal threshold for the current clock cycle.);
issuing, by the one or more controllers located external to the memory die, the one or more commands from the global pool of commands according to the order in which the one or more commands are transferred to the global pool of commands (eg., 0033 - processing time from the CPUs and thus, compete on a priority basis for the CPUs' resources.; 0050 - he global run queue that is preferred by a round-robin search).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue and the queue threshold value as disclosed by Gavens553, with Brenner providing the benefit of keeping the various run queues of the multiple run queue system 100 equally utilized … intended to be implemented in conjunction with one another in order to provide optimum load balancing across the MP system 110. (see Brenner, 0042).
Gavens553 in view of Brenner does not disclose, but Kedem discloses
moving … wherein the one or more commands are included in the global pool and removed from the queue based at least in part on moving the one or more commands (eg., col 7:5-25 - The scheduler 116 includes local schedulers 302 and a global scheduler 304, where each bank command sub-buffer 306 has a corresponding local scheduler 302. Each local scheduler 302 selects the highest priority memory access command within their respective bank command sub-buffers 306, and presents it to the global scheduler 304. The global scheduler 304 causes one or more of the memory access commands provided by the local schedulers 302 to be issued to the memory controller, such as the memory controller 104. The global scheduler 304 issues the commands in a round-robin fashion, or based on their relative priorities (system priority, weighted priority, or both). The global scheduler 304 issues the commands in parallel, depending on the memory interface specification being used).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue and the queue threshold value as disclosed by Gavens553, with Brenner with Kadem, providing the benefit of a system comprising a buffer configured to hold a queued plurality of memory access commands and a priority determination engine that is configured to determine a memory access command priority based at least on first inputs related to characteristics of the memory access command and on second inputs related to a state of a memory. An access scheduler selects an order for the plurality of memory access commands to be issued to the memory based at least on the determined priority of the memory access command (col 1:53-62).
Claim 10. Gavens553 discloses
wherein the one or more commands for performing an operation on the memory die includes a read command, a write command, a host read command, a host write command, or a combination thereof (e.g., commands received from a host device by reading or writing data to or from a set of NAND memory dies, 0003).
Claim 21. Gavens553 discloses wherein the one or more commands are issued to one or more controllers of the memory sub-system from the queue of the memory die (eg., die transaction queues 1432 may include the above-described read request queues. The queues 1432 (which may include separate individual queues for each die, as already explained) include lists of pending host commands that are awaiting execution on the NVM die , 0084).
Claim 11. Gavens553 discloses A system comprising: (e.g., data storage system 100 , 0032 Fig. 1)
a plurality of memory components (e.g., a flash storage device having a set of NAND dies), 0032 Fig. 1); and a processing device, operatively coupled with the plurality of memory components, to: (e.g., a data storage controller 108, 0032 Fig. 1)
determine a number of commands that are included in one of a plurality of queues of a memory die of a memory sub-system, the commands being associated with a respective operation to be performed on the memory sub-system (e.g., determining a number of entries in a memory access queue associated with a memory device, 0008, 0044; die manager to control access to the multiple NAND dies, 0046; assessing a fill status of a memory access queue, 0005),
assign a command to the queue based at least in part on the number of commands that are included in the queue (eg., determination may be made based on the number of entries in the corresponding queues 202.sub.1-N, with cached commands used for a particular die if the number of entries in the corresponding queue exceeds the predetermined queue threshold value (T), and non-cached commands used for a particular die otherwise (e.g. if the number of entries for the corresponding queue is less than or equal to T). One or more queue entry/threshold comparators 210 may be used to compare the queue entry count for a particular queue against the queue threshold value (T). , 0048).
Gavens553 does not disclose, but Brenner discloses
by one or more controllers; by the one or more controllers located external to the memory die (eg., 0042 Fig 1 - The load balancing may be performed by the dispatcher 150.) ;
wherein each queue of the plurality of queues is associated with a respective priority level and is configured to maintain a respective set of commands to be performed on the memory sub-system; and the respective priority level of the queue of the memory die relative to a respective priority level of at least one other queue of the memory die; issuing one or more commands from the respective sets of commands of the plurality of queues based at least in part on the respective priority levels (eg., [0034] The threads in a run queue (local and global) may have priorities associated with them. The run queue maintains the priority information of the highest waiting thread on the run queue in a run queue structure. The dispatcher 150 uses this priority information to make decisions of which run queue to search for the next thread to dispatch; 0048 - he CPUs and corresponding local run queues that are searched are restricted to those associated with the node to which the existing process' threads were assigned).
the plurality of queues located on the memory die and the one or more controllers located external to the memory die, (eg., 0058 - her run queues assigned to the node for processing on the potentially idle CPU. The dispatcher 150 scans the local run queues of the node to which the potentially idle CPU is assigned for a local run queue);
level of the queue relative to the respective priority level of the at least one other queue of the memory die and on the number of commands in the queue exceeding a threshold number of commands (eg., 0010 - load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced ; 0066 - steal threshold is a fraction of the smoothed average load factor on all the local run queues in the node. This load factor is determined by sampling the number of threads on each local run queue )
transferring by the one or more controllers located external to the memory die, one or more commands from the queue of the plurality of queues of the memory die to a global pool of commands associated with the one or more controllers according to an order that is based at least in part on the respective priority level (eg., [0042] Threads are added to the global run queue based on load balancing among the nodes 120-140 and the CPUs 111-117. The load balancing may be performed by the dispatcher 150. Load balancing includes a number of methods of keeping the various run queues of the multiple run queue system 100 equally utilized; [0034] The threads in a run queue (local and global) may have priorities associated with them.);
and on the number of commands in the queue exceeding a respectiv4e threshold number of commands for the queue, wherein each queue of the plurality of queues of the memory die is associated with a respective threshold number of commands (eg., [0058] If a CPU is about to become idle, the dispatcher 150 attempts to "steal" threads from other run queues assigned to the node for processing on the potentially idle CPU. The dispatcher 150 scans the local run queues of the node to which the potentially idle CPU is assigned for a local run queue that satisfies the following criteria: [0059] 1) the local run queue has the largest number of threads of all the local run queues of the node; [0060] 2) the local run queue contains more threads than the node's current steal threshold (defined hereafter); [0061] 3) the local run queue contains at least one unbound thread; and [0062] 4) the local run queue has not had more threads stolen from it than a maximum steal threshold for the current clock cycle.);
issuing, by the one or more controllers located external to the memory die, the one or more commands from the global pool of commands according to the order in which the one or more commands are transferred to the global pool of commands (eg., 0033 - processing time from the CPUs and thus, compete on a priority basis for the CPUs' resources.; 0050 - he global run queue that is preferred by a round-robin search).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue and the queue threshold value as disclosed by Gavens553, with Brenner providing the benefit of keeping the various run queues of the multiple run queue system 100 equally utilized … intended to be implemented in conjunction with one another in order to provide optimum load balancing across the MP system 110. (see Brenner, 0042).
Gavens553 in view of Brenner does not disclose, but Kedem discloses
moving … wherein the one or more commands are included in the global pool and removed from the queue based at least in part on moving the one or more commands (eg., col 7:5-25 - The scheduler 116 includes local schedulers 302 and a global scheduler 304, where each bank command sub-buffer 306 has a corresponding local scheduler 302. Each local scheduler 302 selects the highest priority memory access command within their respective bank command sub-buffers 306, and presents it to the global scheduler 304. The global scheduler 304 causes one or more of the memory access commands provided by the local schedulers 302 to be issued to the memory controller, such as the memory controller 104. The global scheduler 304 issues the commands in a round-robin fashion, or based on their relative priorities (system priority, weighted priority, or both). The global scheduler 304 issues the commands in parallel, depending on the memory interface specification being used).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue and the queue threshold value as disclosed by Gavens553, with Brenner with Kadem, providing the benefit of a system comprising a buffer configured to hold a queued plurality of memory access commands and a priority determination engine that is configured to determine a memory access command priority based at least on first inputs related to characteristics of the memory access command and on second inputs related to a state of a memory. An access scheduler selects an order for the plurality of memory access commands to be issued to the memory based at least on the determined priority of the memory access command (col 1:53-62).
Claim 16. Gavens553 discloses A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to(e.g., data storage system 100 , 0032 Fig. 1)
determine a number of commands included in a queue of a plurality of queues of a memory die of a memory sub-system, each command being associated with a respective operation to be performed on the memory sub-system (e.g., determining a number of entries in a memory access queue associated with a memory device, 0008, 0044; die manager to control access to the multiple NAND dies, 0046; assessing a fill status of a memory access queue, 0005),
assign a command to the queue of the plurality of queues based at least in part on the number of commands that are included in the queue (eg., determination may be made based on the number of entries in the corresponding queues 202.sub.1-N, with cached commands used for a particular die if the number of entries in the corresponding queue exceeds the predetermined queue threshold value (T), and non-cached commands used for a particular die otherwise (e.g. if the number of entries for the corresponding queue is less than or equal to T). One or more queue entry/threshold comparators 210 may be used to compare the queue entry count for a particular queue against the queue threshold value (T). , 0048).
Gavens553 does not disclose, but Brenner discloses
by one or more controllers; by the one or more controllers located external to the memory die (eg., 0042 Fig 1 - The load balancing may be performed by the dispatcher 150.) ;
wherein each queue of the plurality of queues is associated with a respective priority level and is configured to maintain a respective set of commands to be performed on the memory sub-system; and the respective priority level of the queue of the memory die relative to a respective priority level of at least one other queue of the memory die; issuing one or more commands from the respective sets of commands of the plurality of queues based at least in part on the respective priority levels (eg., [0034] The threads in a run queue (local and global) may have priorities associated with them. The run queue maintains the priority information of the highest waiting thread on the run queue in a run queue structure. The dispatcher 150 uses this priority information to make decisions of which run queue to search for the next thread to dispatch; 0048 - he CPUs and corresponding local run queues that are searched are restricted to those associated with the node to which the existing process' threads were assigned).
the plurality of queues located on the memory die and the one or more controllers located external to the memory die, (eg., 0058 - her run queues assigned to the node for processing on the potentially idle CPU. The dispatcher 150 scans the local run queues of the node to which the potentially idle CPU is assigned for a local run queue);
level of the queue relative to the respective priority level of the at least one other queue of the memory die and on the number of commands in the queue exceeding a threshold number of commands (eg., 0010 - load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced ; 0066 - steal threshold is a fraction of the smoothed average load factor on all the local run queues in the node. This load factor is determined by sampling the number of threads on each local run queue )
transferring by the one or more controllers located external to the memory die, one or more commands from the queue of the plurality of queues of the memory die to a global pool of commands associated with the one or more controllers according to an order that is based at least in part on the respective priority level (eg., [0042] Threads are added to the global run queue based on load balancing among the nodes 120-140 and the CPUs 111-117. The load balancing may be performed by the dispatcher 150. Load balancing includes a number of methods of keeping the various run queues of the multiple run queue system 100 equally utilized; [0034] The threads in a run queue (local and global) may have priorities associated with them.);
and on the number of commands in the queue exceeding a respectiv4e threshold number of commands for the queue, wherein each queue of the plurality of queues of the memory die is associated with a respective threshold number of commands (eg., [0058] If a CPU is about to become idle, the dispatcher 150 attempts to "steal" threads from other run queues assigned to the node for processing on the potentially idle CPU. The dispatcher 150 scans the local run queues of the node to which the potentially idle CPU is assigned for a local run queue that satisfies the following criteria: [0059] 1) the local run queue has the largest number of threads of all the local run queues of the node; [0060] 2) the local run queue contains more threads than the node's current steal threshold (defined hereafter); [0061] 3) the local run queue contains at least one unbound thread; and [0062] 4) the local run queue has not had more threads stolen from it than a maximum steal threshold for the current clock cycle.);
issuing, by the one or more controllers located external to the memory die, the one or more commands from the global pool of commands according to the order in which the one or more commands are transferred to the global pool of commands (eg., 0033 - processing time from the CPUs and thus, compete on a priority basis for the CPUs' resources.; 0050 - he global run queue that is preferred by a round-robin search).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue and the queue threshold value as disclosed by Gavens553, with Brenner providing the benefit of keeping the various run queues of the multiple run queue system 100 equally utilized … intended to be implemented in conjunction with one another in order to provide optimum load balancing across the MP system 110. (see Brenner, 0042).
Gavens553 in view of Brenner does not disclose, but Kedem discloses
moving … wherein the one or more commands are included in the global pool and removed from the queue based at least in part on moving the one or more commands (eg., col 7:5-25 - The scheduler 116 includes local schedulers 302 and a global scheduler 304, where each bank command sub-buffer 306 has a corresponding local scheduler 302. Each local scheduler 302 selects the highest priority memory access command within their respective bank command sub-buffers 306, and presents it to the global scheduler 304. The global scheduler 304 causes one or more of the memory access commands provided by the local schedulers 302 to be issued to the memory controller, such as the memory controller 104. The global scheduler 304 issues the commands in a round-robin fashion, or based on their relative priorities (system priority, weighted priority, or both). The global scheduler 304 issues the commands in parallel, depending on the memory interface specification being used).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue and the queue threshold value as disclosed by Gavens553, with Brenner with Kadem, providing the benefit of a system comprising a buffer configured to hold a queued plurality of memory access commands and a priority determination engine that is configured to determine a memory access command priority based at least on first inputs related to characteristics of the memory access command and on second inputs related to a state of a memory. An access scheduler selects an order for the plurality of memory access commands to be issued to the memory based at least on the determined priority of the memory access command (col 1:53-62).
6. Claims 2,5,6, 12, 15, 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gavens (US 20190294553) and in view of Brenner (cited above) and Kadem (cited above) and further in view of Gavens (US 20190286364)
Claim 2. Gavens553 in view of Brenner and Kadem does not disclose, but Gavens364 discloses
further comprising: prohibiting each of the plurality of queues that have a number of commands that exceeds the associated respective threshold number of commands from accepting additional commands until the number of commands is below the associated respective threshold number of commands (e.g., become full or filled above some limit (e.g. more than some threshold number of entries) so that a die manager may be unable to add atomic requests, 0079).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue as disclosed by Gavens553, in view of Brenner and Kadem with Gavens364, providing the benefit of request queues for multiple non-volatile memory dies are managed by a die manager independently of each other so that die-specific requests to non-volatile memory dies may be rapidly sent to the respective dies as die-specific triggering events occur that provide opportunities for a die to accept new requests (see Gavens364, 0022).
Claim 5. Gavens553 discloses
further comprising: storing, to a memory of the memory sub-system, at least one command associated with a queue having a respective number of commands that exceeds the associated respective threshold number of commands (e.g., One or more cached read submission controllers 212 may be used to submit reads to particular dies as cached reads (if the queue entry count of the queue for the particular die exceeds the queue threshold value (T)). , 0048); and
Gavens553 in view of Brenner and Kadem does not disclose, but Gavens364 discloses
assigning the command to the queue based at least in part on the respective number of commands falling below the threshold value (e.g., detection that space is available in a second request queue, or more than a threshold amount of space is available in a second request queue, 0079).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue as disclosed by Gavens553, in view of Brenner and Kadem with Gavens364, providing the benefit of request queues for multiple non-volatile memory dies are managed by a die manager independently of each other so that die-specific requests to non-volatile memory dies may be rapidly sent to the respective dies as die-specific triggering events occur that provide opportunities for a die to accept new requests (see Gavens364, 0022).
Claim 6. Gavens553 in view of Brenner and Kadem does not disclose, but Gavens364 discloses
wherein the respective threshold number of commands is based at least in part on resources of the memory sub-system available for performing operations on the memory sub-system (e.g., cached commands used for a particular die if the number of entries in the corresponding queue exceeds the predetermined queue threshold value (T), 0048).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue as disclosed by Gavens553, in view Brenner and Kadem with Gavens364, providing the benefit of request queues for multiple non-volatile memory dies are managed by a die manager independently of each other so that die-specific requests to non-volatile memory dies may be rapidly sent to the respective dies as die-specific triggering events occur that provide opportunities for a die to accept new requests (see Gavens364, 0022).
Claim 12 is rejected for reasons similar to claim 2 above.
Claim 15 is rejected for reasons similar to claim 5 above.
Claim 17 is rejected for reasons similar to claim 2 above.
Claim 20 is rejected for reasons similar to claim 15 above.
7. Claims 3, 4, 7,8,9, 13, 14, 18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gavens (US 20190294553) and in view of and further in view of Brenner (cited above) and Kadem (cited above) and Gavens (US 20190286364) and Rodriguez (US 20070174529)
Claim 3. Gavens553 in view of Brenner and Kadem does not disclose, but Gavens364 discloses
further comprising: assigning one or more additional commands to each queue having a respective number of commands below the threshold value (e.g., when space becomes available, this may be a triggering event because a new opportunity exists for a die manager to send new atomic requests., 0079); and
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue as disclosed by Gavens553, in view of Brenner with Gavens364, providing the benefit of request queues for multiple non-volatile memory dies are managed by a die manager independently of each other so that die-specific requests to non-volatile memory dies may be rapidly sent to the respective dies as die-specific triggering events occur that provide opportunities for a die to accept new requests (see Gavens364, 0022).
Gavens553 in view of Brenner and Kadem and Gavens364 does not disclose, but Rodriguez discloses
issuing the one or more additional commands from each queue based at least in part on the respective priority levels (e.g., arbitration may take into account the parameters (e.g., priority, quality of service) associated with the queues the queues, 0013; enable priority processing for particular queues or groups of queues… high, low,… higher priority queues may be processed (have grants issued) 0020; ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue as disclosed by Gavens553, in view of Brenner, and Kadem Gavens364 with Rodrizuez, providing the benefit of arbitration may take into account the parameters (e.g., priority, quality of service) associated with the queues the queues (see Rodriguez, 0013) data being received by the network processor has different parameters (e.g., priority, QoS requirements) the data may need to be processed differently (0020).
Claim 4. Gavens553 discloses further comprising: issuing all of the commands for each queue having the number of commands that exceed the associated respective threshold number of commands, wherein assigning one or more additional commands to each queue is based at least in part on issuing all of the commands (e.g., the determination may be made based on the number of entries in the corresponding queues 202.sub.1-N, with cached commands used for a particular die if the number of entries in the corresponding queue exceeds the predetermined queue threshold value (T), 0048).
Claim 7. Gavens553 in view of Brenner and Kadem and Gavens364 does not disclose, but Rodriguez discloses
further comprising: assigning, to a set of queues for a plurality of memory dies of the memory sub- system, one or more commands associated with operations to be performed on the memory sub-system, wherein each queue of the set of queues is associated with a respective priority level; and issuing commands from the set of queues according to the respective priority levels (e.g., arbitration may take into account the parameters (e.g., priority, quality of service) associated with the queues the queues, 0013; enable priority processing for particular queues or groups of queues… high, low,… higher priority queues may be processed (have grants issued) 0020; ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue as disclosed by Gavens553, in view of Brenner and Kadem with Gavens364, and Rodrizuez, providing the benefit of arbitration may take into account the parameters (e.g., priority, quality of service) associated with the queues the queues (see Rodriguez, 0013) data being received by the network processor has different parameters (e.g., priority, QoS requirements) the data may need to be processed differently (0020).
Claim 8. Gavens553 in view of Brenner and Kadem does not disclose, but Gavens364 discloses
determining a number of active memory dies of the memory sub-system; and prohibiting one or more active memory dies of the memory sub-system from accepting additional commands when the number of active memory dies exceeds the associated respective threshold number of commands (e.g., a second request queue may become full or filled above some limit (e.g. more than some threshold number of entries) so that a die manager may be unable to add atomic requests. , 0079).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue as disclosed by Gavens553, in view of Brenner and Kadem with Gavens364, providing the benefit of request queues for multiple non-volatile memory dies are managed by a die manager independently of each other so that die-specific requests to non-volatile memory dies may be rapidly sent to the respective dies as die-specific triggering events occur that provide opportunities for a die to accept new requests (see Gavens364, 0022).
Claim 9. Gavens553 discloses
determining that a plurality of active memory dies of the memory sub-system exceed the respective threshold number of commands, wherein prohibiting the one or more active memory dies from accepting additional commands is based at least in part on a number of commands associated with each of the one or more active memory dies (e.g., sized to store up to six entries and the inner queue 805.sub.1-N is sized to store up to five entries, 0062; the current number of entries… the number of entries is found to exceed the threshold , 0063 Fig. 9).
Claim 13 is rejected for reasons similar to claim 3 above.
Claim 14 is rejected for reasons similar to claim 4 above.
Claim 18 is rejected for reasons similar to claim 3 above.
Claim 19 is rejected for reasons similar to claim 4 above.
Response to Arguments
Applicant's arguments filed 9/16/2025 have been fully considered but they are not persuasive.
For claims 1, 11, 16, Applicant argues that the cited references do not disclose the amended limitations. The Office disagrees.
In this OA, Gavens553 in view of Brenner does not disclose, but Kedem discloses
moving … wherein the one or more commands are included in the global pool and removed from the queue based at least in part on moving the one or more commands (eg., col 7:5-25 - The scheduler 116 includes local schedulers 302 and a global scheduler 304, where each bank command sub-buffer 306 has a corresponding local scheduler 302. Each local scheduler 302 selects the highest priority memory access command within their respective bank command sub-buffers 306, and presents it to the global scheduler 304. The global scheduler 304 causes one or more of the memory access commands provided by the local schedulers 302 to be issued to the memory controller, such as the memory controller 104. The global scheduler 304 issues the commands in a round-robin fashion, or based on their relative priorities (system priority, weighted priority, or both). The global scheduler 304 issues the commands in parallel, depending on the memory interface specification being used).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the die manager to control access to multiple dies assessing a fill status of a memory access queue and the queue threshold value as disclosed by Gavens553, with Brenner with Kadem, providing the benefit of a system comprising a buffer configured to hold a queued plurality of memory access commands and a priority determination engine that is configured to determine a memory access command priority based at least on first inputs related to characteristics of the memory access command and on second inputs related to a state of a memory. An access scheduler selects an order for the plurality of memory access commands to be issued to the memory based at least on the determined priority of the memory access command (col 1:53-62).
Claims 2-10, 12-15, 17-20 are rejected based on dependency from claims 1, 11, 16.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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