DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on 10/23/2025. These drawings are acceptable.
Specification
Amendments to the Specification are acknowledged and are acceptable.
Response to Arguments
Applicant’s arguments, see REMARKS, filed 10/23/2025, with respect to rejection of claims 12 and 14-24 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph have been fully considered and are persuasive in view of the filed amendments. The rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph of 12 and 14-24 has been withdrawn.
Applicant's arguments filed 10/23/2025, with respect to rejection of claims 1, 3-12 and 14-24 under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Applicant argue, see REMARKS page 15, that “Specifically, Liu fails to teach or suggest that the multiple phase components of the decomposed recursive transfer function "include a decomposed version of the integrator element having parallel inputs." Instead, Liu decomposes the CIC filter into four subfilters that includes a integrator and a comb. Each subfilter receives a separate input that is delayed or not delayed. There are no integrator elements with parallel inputs as claimed.”
The Office respectfully disagrees. As applicants acknowledge, “Liu decomposes the CIC filter into four subfilters that includes a integrator and a comb” where each subfilter receives parallel input that is delayed or not delayed. The Office interpreted that the four subfilters represents the decomposed recursive transfer function of the CIC filter, where each of the four subfilters includes at least one decomposed version of the integrator element (Fig. 7: each “CIC filter” includes at least one decomposed version of the integrator element, defined by adder and feedback delay elements, similar to applicants disclosure, e.g. the decomposed recursive transfer function of the CIC filter (instant Fig. 5: CIC filter 500) includes decomposed integrator element, Q(z) (Fig. 5, 7B, 7C – integrator 502/750/770), including an adder and a feedback delay element) having parallel inputs (Fig. 4: the adder, of the integrator element, has two parallel inputs – similar to instant Fig. 5, 7B, 7C). Thus, Liu fairly teaches “the decomposed recursive transfer function include a decomposed version of the integrator element having parallel inputs.”
The Office maintains its pervious rejection of claims 1, 3-12 and 14-24 under 35 U.S.C. 103 as detailed below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 7-12 and 18-24 are rejected under 35 U.S.C. 103 as being unpatentable over Haddadin et al. (US 8725785 B1 previously cited) in view of Liu (NPL titled “A High Speed Digital Decimation Filter with Parallel Cascaded Integrator-Comb Pre-Filters," 2009 2nd International Congress on Image and Signal Processing, Tianjin, China, 2009, pp. 1-4”).
Regarding Claim 1, Haddadin et al. discloses;
A method (col. 2, line 30: “a method for performing a parallel-input parallel-output infinite impulse response filter”), comprising:
receiving two or more input samples of data values (col. 5, line 11-12 “ n being the sample number or time index”; Fig. 3, 9: first and second input samples, e.g. yo(n), y1(n) or v0(n), v1(n)); and
with…filter that has a recursive transfer function (Fig. 3, col. 5: equation (3) – where A(z) is recursive transfer function; Fig. 9, col. 10: Equation (17)-(19) - recursive transfer function), applying a filter operation (Fig. 3, 9, col. 10: filter operation 304 and 306, where filter 306 has recursive transfer function implemented using Equation (17)) on a first and a second input sample of data values in parallel to obtain filtered first and second input samples of data values (Fig. 3, 9: first and second input sample of data values, e.g. X(n) and XN-1(n) are filtered in parallel to obtain filtered first and second input samples of data values, y0(n), yM-1(n) and v0(n), v1(n), respectively, also see Equation (17)), the filter operation comprises a recursive filter operation (Abstract, Fig. 3, 9: filter 306 “performing parallel-input parallel-output infinite impulse response (IIR) filter filtering” i.e. performs recursive filtering operation) such that the filtering of the second input sample of data values that is subsequent in time relative to the first input sample of data values is dependent on the filtering of the first input sample of data values (Fig. 3, 9: the output of the summer 314 is delayed and fed back to summer 314 to be added to the subsequent input sample/output from the first filter operation 304), the applying the filter operation comprises:
applying polyphase decomposition to…decompose the recursive transfer function into multiple phase components (col. 6 “…the feed-forward filter 304 can be decomposed as a polyphase filter…the polyphase filter can expanded as the sum of a number of sub-filters which can be referred to as polyphase components” Also see equation (5)- “Ui(z) is the i-th phase”; col. 9, line 44-46: “The feed-back filter [306 - the IIR filter element] can also be implemented using a parallel-input parallel-output filter, using similar techniques as the feed-forward filter [304]”; col. 10, line 7-45: “the feedback filter can be decomposed into two linear operators”, i.e. using polyphase decomposition where feed-forward filter 304 and the feed-back filter 306 input sample of data values are independently processed. Also see Equation (17)-(19), for a two input sample example and Fig. 9 for implementation of the feedback filter)…and
using the multiple phase components of the recursive transfer function (Fig. 3, 9, col. 9, line 42 - col. 10, line 47: Equation (16), (18) – “the z-transform of vi(n), is the i-th phase at the output 312 of the feed-back filter”, i.e. feed-back transfer function including multiple phase component) in performing the filter operation to produce the filtered first and second data input sample values (Fig. 3, 9, col. 10, line 1-45: filter element (Fig. 1, 3, 9) parallelly processing the first and second input samples, e.g. , X(n) and XN-1(n), by respective transfer functions (z-1
A
~
1
(z), z-1
A
~
0
(z) and
A
~
0
(z), z-1
A
~
1
(z)) to produce the filtered first and second data input sample values, y0(n) and yM-1(n), respectively).
Haddadin et al. does not disclose the recursive transfer function is a:
“cascaded integrator-comb (CIC) filter having an integrator element”; the polyphase decomposition is applied to:
“the CIC filter element”; and
“that include a decomposed version of the integrator element having parallel inputs, wherein, for each of the parallel inputs, the decomposed integrator element includes a path leading from the parallel input to a respective integrator element output and this path includes only a single adder that adds the parallel input to a delayed output from the adder that is output by a delay element”.
On the other hand, Liu et al. discloses performing filtering using recursive transfer function of a:
“cascaded integrator-comb (CIC) filter having an integrator element” (Abstract, Fig. 2, 5, 7, Section III: PARALLEL-CIC STRCUTURE: “Cascaded Integrator-Comb (CIC)” filter having an “integrator” element , i.e. 1-Z-M (see equation (1)); the polyphase decomposition is applied to:
“the CIC filter element” (Section III: PARALLEL-CIC STRCUTURE: “The new structure embedded recursive filters into poly-phase decomposition, thus having the advantage of both.” That is, polyphase decomposition is applied to the CIC filter element); and
“that include a decomposed version of the integrator element having parallel inputs (Fig. 5, 7, Section III: PARALLEL-CIC STRCUTURE: “In the new structure, multiple CIC filters are paralleled and arranged in a poly-phase decomposition fashion. This leads to the transfer function of Hp(z)…” As depicted in Fig. 5, 7, equation of Hp(z), integrator element of the CIC filter have parallel inputs), wherein, for each of the parallel inputs, the decomposed integrator element includes a path leading from the parallel input to a respective integrator element output (Fig. 7: e.g. for each parallel input to the decomposed integrator element (see modified Fig. 7 below: includes a path leading from the parallel input, i.e. input to the adder, to a respective integrator element output, i.e. output of the adder) and this path includes only a single adder (modified Fig. 7 below includes only a single adder) that adds the parallel input to a delayed output from the adder that is output by a delay element (see modified Fig. 7 below: adds the parallel input with a delayed output from the adder that is output by a delay element, z-1.)”.
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Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that recursive filtering operation using recursive transfer function (Fig. 3, 9) in Haddadin et al.’s invention can be implemented using CIC filter with integrator element as taught by Liu where doing so would (Liu, Abstract) “achieves unprecedented clock rate and considerable area/complexity savings while providing frequency response.”
Regarding Claim 12, Haddadin et al. discloses;
A non-transitory computer-readable storage media storing instructions executable by processing logic to cause the processing logic (col. 12, line 10-19: “The methods 900, 950 can be implemented using a processor, including a digital signal processor, general purpose processor, or the like in which case computer readable instructions can be provided on a computer readable media to cause the processor to execute the method”) to perform the following:
receive two or more input samples of data values (col. 5, line 11-12 “ n being the sample number or time index”; Fig. 3, 9: first and second input samples, e.g. yo(n), y1(n) or v0(n), v1(n)); and
with…filter that has a recursive transfer function (Fig. 3, col. 5: equation (3) – where A(z) is recursive transfer function; Fig. 9, col. 10: Equation (17)-(19) - recursive transfer function), applying a filter operation (Fig. 3, 9, col. 10: filter operation 304 and 306, where filter 306 has recursive transfer function implemented using Equation (17)) on a first and a second input sample of data values in parallel to obtain filtered first and second input samples of data values (Fig. 3, 9: first and second input sample of data values, e.g. X(n) and XN-1(n) are filtered in parallel to obtain filtered first and second input samples of data values, y0(n), yM-1(n) and v0(n), v1(n), respectively, also see Equation (17)), the filter operation comprises a recursive filter operation (Abstract, Fig. 3, 9: filter 306 “performing parallel-input parallel-output infinite impulse response (IIR) filter filtering” i.e. performs recursive filtering operation) such that the filtering of the second input sample of data values that is subsequent in time relative to the first input sample of data values is dependent on the filtering of the first input sample of data values (Fig. 3, 9: the output of the summer 314 is delayed and fed back to summer 314 to be added to the subsequent input sample/output from the first filter operation 304), the applying the filter operation comprises:
applying polyphase decomposition to…decompose the recursive transfer function into multiple phase components (col. 6 “…the feed-forward filter 304 can be decomposed as a polyphase filter…the polyphase filter can expanded as the sum of a number of sub-filters which can be referred to as polyphase components” Also see equation (5)- “Ui(z) is the i-th phase”; col. 9, line 44-46: “The feed-back filter [306 - the IIR filter element] can also be implemented using a parallel-input parallel-output filter, using similar techniques as the feed-forward filter [304]”; col. 10, line 7-45: “the feedback filter can be decomposed into two linear operators”, i.e. using polyphase decomposition where feed-forward filter 304 and the feed-back filter 306 input sample of data values are independently processed. Also see Equation (17)-(19), for a two input sample example and Fig. 9 for implementation of the feedback filter)…and
using the multiple phase components of the recursive transfer function (Fig. 3, 9, col. 9, line 42 - col. 10, line 47: Equation (16), (18) – “the z-transform of vi(n), is the i-th phase at the output 312 of the feed-back filter”, i.e. feed-back transfer function including multiple phase component) in performing the filter operation to produce the filtered first and second data input sample values (Fig. 3, 9, col. 10, line 1-45: filter element (Fig. 1, 3, 9) parallelly processing the first and second input samples, e.g. , X(n) and XN-1(n), by respective transfer functions (z-1
A
~
1
(z), z-1
A
~
0
(z) and
A
~
0
(z), z-1
A
~
1
(z)) to produce the filtered first and second data input sample values, y0(n) and yM-1(n), respectively) with a throughput that is twofold of a throughput of the IIR filter element producing the filtered first and second data input samples serially (Fig. 3, 9, col. 10, line 1-45: IIR filter element (Fig. 9) parallelly processing the first and second input samples, e.g. yo(n) and y1(n), by respective transfer functions (z-1
A
~
1
(z), z-1
A
~
0
(z) and
A
~
0
(z), z-1
A
~
1
(z)) to produce the filtered first and second data input sample values, v0(n) and v1(n), respectively, hence resulting in “twofold” throughput when compared to v0(n) and v1(n) begin serially processed, i.e. not processed parallelly. Additionally, Equation (17), which is in form to applicants Equation 9, would similarly result in “twofold throughput of the IIR filter element producing the filtered first and second data input samples serially”).
Haddadin et al. does not disclose the recursive transfer function is a:
“cascaded integrator-comb (CIC) filter having an integrator element”; the polyphase decomposition is applied to:
“the CIC filter element”; and
“that include a decomposed version of the integrator element having parallel inputs, wherein, for each of the parallel inputs, the decomposed integrator element includes a path leading from the parallel input to a respective integrator element output and this path includes only a single adder that adds the parallel input to a delayed output from the adder that is output by a delay element”.
On the other hand, Liu et al. discloses performing filtering using recursive transfer function of a:
“cascaded integrator-comb (CIC) filter having an integrator element” (Abstract, Fig. 2, 5, 7, Section III: PARALLEL-CIC STRCUTURE: “Cascaded Integrator-Comb (CIC)” filter having an “integrator” element , i.e. 1-Z-M (see equation (1)); the polyphase decomposition is applied to:
“the CIC filter element” (Section III: PARALLEL-CIC STRCUTURE: “The new structure embedded recursive filters into poly-phase decomposition, thus having the advantage of both.” That is, polyphase decomposition is applied to the CIC filter element); and
“that include a decomposed version of the integrator element having parallel inputs (Fig. 5, 7, Section III: PARALLEL-CIC STRCUTURE: “In the new structure, multiple CIC filters are paralleled and arranged in a poly-phase decomposition fashion. This leads to the transfer function of Hp(z)…” As depicted in Fig. 5, 7, equation of Hp(z), integrator element of the CIC filter have parallel inputs), wherein, for each of the parallel inputs, the decomposed integrator element includes a path leading from the parallel input to a respective integrator element output (Fig. 7: e.g. for each parallel input to the decomposed integrator element (see modified Fig. 7 below: includes a path leading from the parallel input, i.e. input to the adder, to a respective integrator element output, i.e. output of the adder) and this path includes only a single adder (modified Fig. 7 below includes only a single adder) that adds the parallel input to a delayed output from the adder that is output by a delay element (see modified Fig. 7 below: adds the parallel input with a delayed output from the adder that is output by a delay element, z-1.)”.
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82
82
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Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that recursive filtering operation using recursive transfer function (Fig. 3, 9) in Haddadin et al.’s invention can be implemented using CIC filter with integrator element as taught by Liu where doing so would (Liu, Abstract) “achieves unprecedented clock rate and considerable area/complexity savings while providing frequency response.”
Regarding Claim 23, Haddadin et al. discloses;
One or more hardware components configured (Fig. 1, 3, 9-11: The filters may be implemented in hardware, e.g. an ASIC or FPGA (column 12 lines 20-23) or by using a processor, computer readable media and stored instructions (column 12 lines 10-19); digital logic may be expressed in languages such as VHDL and Verilog™ (column 12 lines 26-29)) to perform the following:
receive two or more input samples of data values (col. 5, line 11-12 “ n being the sample number or time index”; Fig. 3, 9: first and second input samples, e.g. yo(n), y1(n) or v0(n), v1(n)); and
applying the polyphase decomposition to the IIR filter element to decompose the recursive transfer function into multiple phase components (Fig. 3, col. 5: equation (3) – where A(z) is recursive transfer function; Fig. 9, col. 10: Equation (17)-(19) - recursive transfer function), applying a filter operation (Fig. 3, 9, col. 10: filter operation 304 and 306, where filter 306 has recursive transfer function implemented using Equation (17)) on a first and a second input sample of data values in parallel to obtain filtered first and second input samples of data values (Fig. 3, 9: first and second input sample of data values, e.g. X(n) and XN-1(n) are filtered in parallel to obtain filtered first and second input samples of data values, y0(n), yM-1(n) and v0(n), v1(n), respectively, also see Equation (17)), the filter operation comprises a recursive filter operation (Abstract, Fig. 3, 9: filter 306 “performing parallel-input parallel-output infinite impulse response (IIR) filter filtering” i.e. performs recursive filtering operation) such that the filtering of the second input sample of data values that is subsequent in time relative to the first input sample of data values is dependent on the filtering of the first input sample of data values (Fig. 3, 9: the output of the summer 314 is delayed and fed back to summer 314 to be added to the subsequent input sample/output from the first filter operation 304), the applying the filter operation comprises:
applying polyphase decomposition to the IIR filter element to decompose the recursive transfer function into multiple phase components (col. 6 “…the feed-forward filter 304 can be decomposed as a polyphase filter…the polyphase filter can expanded as the sum of a number of sub-filters which can be referred to as polyphase components” Also see equation (5)- “Ui(z) is the i-th phase”; col. 9, line 44-46: “The feed-back filter [306 - the IIR filter element] can also be implemented using a parallel-input parallel-output filter, using similar techniques as the feed-forward filter [304]”; col. 10, line 7-45: “the feedback filter can be decomposed into two linear operators”, i.e. using polyphase decomposition where feed-forward filter 304 and the feed-back filter 306 input sample of data values are independently processed. Also see Equation (17)-(19), for a two input sample example and Fig. 9 for implementation of the feedback filter)…and
using the multiple phase components of the recursive transfer function (Fig. 3, 9, col. 9, line 42 - col. 10, line 47: Equation (16), (18) – “the z-transform of vi(n), is the i-th phase at the output 312 of the feed-back filter”, i.e. feed-back transfer function including multiple phase component) in performing the filter operation to produce the filtered first and second data input sample values (Fig. 3, 9, col. 10, line 1-45: filter element (Fig. 1, 3, 9) parallelly processing the first and second input samples, e.g. , X(n) and XN-1(n), by respective transfer functions (z-1
A
~
1
(z), z-1
A
~
0
(z) and
A
~
0
(z), z-1
A
~
1
(z)) to produce the filtered first and second data input sample values, y0(n) and yM-1(n), respectively) with a throughput that is twofold of a throughput of the IIR filter element producing the filtered first and second data input samples serially (Fig. 3, 9, col. 10, line 1-45: IIR filter element (Fig. 9) parallelly processing the first and second input samples, e.g. yo(n) and y1(n), by respective transfer functions (z-1
A
~
1
(z), z-1
A
~
0
(z) and
A
~
0
(z), z-1
A
~
1
(z)) to produce the filtered first and second data input sample values, v0(n) and v1(n), respectively, hence resulting in “twofold” throughput when compared to v0(n) and v1(n) begin serially processed, i.e. not processed parallelly. Additionally, Equation (17), which is in form to applicants Equation 9, would similarly result in “twofold throughput of the IIR filter element producing the filtered first and second data input samples serially”).
Haddadin et al. does not disclose the recursive transfer function is a:
“cascaded integrator-comb (CIC) filter having an integrator element”; and
“that include a decomposed version of the integrator element having parallel inputs, wherein, for each of the parallel inputs, the decomposed integrator element includes a path leading from the parallel input to a respective integrator element output and this path includes only a single adder that adds the parallel input to a delayed output from the adder that is output by a delay element”.
On the other hand, Liu et al. discloses performing filtering using recursive transfer function of a:
“cascaded integrator-comb (CIC) filter having an integrator element” (Abstract, Fig. 2, 5, 7, Section III: PARALLEL-CIC STRCUTURE: “Cascaded Integrator-Comb (CIC)” filter having an “integrator” element , i.e. 1-Z-M (see equation (1)); and
“that include a decomposed version of the integrator element having parallel inputs (Fig. 5, 7, Section III: PARALLEL-CIC STRCUTURE: “In the new structure, multiple CIC filters are paralleled and arranged in a poly-phase decomposition fashion. This leads to the transfer function of Hp(z)…” As depicted in Fig. 5, 7, equation of Hp(z), integrator element of the CIC filter have parallel inputs), wherein, for each of the parallel inputs, the decomposed integrator element includes a path leading from the parallel input to a respective integrator element output (Fig. 7: e.g. for each parallel input to the decomposed integrator element (see modified Fig. 7 below: includes a path leading from the parallel input, i.e. input to the adder, to a respective integrator element output, i.e. output of the adder) and this path includes only a single adder (modified Fig. 7 below includes only a single adder) that adds the parallel input to a delayed output from the adder that is output by a delay element (see modified Fig. 7 below: adds the parallel input with a delayed output from the adder that is output by a delay element, z-1.)”.
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82
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Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that recursive filtering operation using recursive transfer function (Fig. 3, 9) in Haddadin et al.’s invention can be implemented using CIC filter with integrator element as taught by Liu where doing so would (Liu, Abstract) “achieves unprecedented clock rate and considerable area/complexity savings while providing frequency response.”
Regarding Claim 7 and 18, Haddadin et al. in view of Liu discloses all as applied to claim 1 and 12 above, where Haddadin et al. further teaches;
wherein the method is performed by executing a model (Fig. 1, 10, 11: “a parallel-input parallel-output infinite impulse response filter” model) on one or more processors (column 12 lines 10-19: by using a processor), and wherein the model comprises a modeled filter (Fig. 1, 10, 11, col. 5, line 28-31, col. 9, line 50 equation 2 and equation 16 – modeled filter) that performs the applying a filter operation on a first and a second input sample of data values in parallel to obtain filtered first and second input samples of data values (see Fig. 3, 9-11, filtered input sample data values y0(n), yM-1(n) and v0(n), v1(n), respectively).
Regarding Claim 8 and 19, Haddadin et al. in view of Liu discloses all as applied to claim 1 and 12 above, Haddadin et al. further teaches;
wherein the method is performed by a physical device (column 12 lines 20-23: The filters may be implemented in hardware, e.g. an ASIC or FPG).
Regarding Claim 9, Haddadin et al. in view of Liu discloses all as applied to claim 7 above, Haddadin et al. further teaches;
generating programming language instructions from the model, wherein when executed, the programming language instructions perform the method (column 12 lines 26-29: digital logic may be expressed in languages such as VHDL and Verilog™. That is the model can be generated and executed using languages such as VHDL and Verilog™).
Regarding Claim 20, Haddadin et al. in view of Liu discloses all as applied to claim 12 above, Haddadin et al. further discloses;
storing instructions for generating programming language instructions from the model, wherein when executed, the programming language instructions perform the method (column 12 lines 26-29: digital logic may be expressed in languages such as VHDL and Verilog™. That is the model can be generated and executed using languages such as VHDL and Verilog™), wherein when executed, the programming language instructions performs the receiving two or more input samples of data values and the applying a filter operation on a first and a second input sample of data values in parallel to obtain filtered first and second input samples of data values (see Fig. 3, 9-11: performing a parallel-input parallel-output infinite impulse response filter” to obtain filtered input sample data values y0(n), yM-1(n) and v0(n), v1(n), respectively).
Regarding Claim 10 and 21, Haddadin et al. in view of Liu discloses all as applied to claim 9 and 20 above, Haddadin et al. further teaches;
wherein the programming language instructions are generated in one of the following programming languages: VHDL, Verilog language (column 12 lines 26-29: digital logic may be expressed in languages such as VHDL and Verilog™), C language C++ language, Python language, or Java language.
Regarding Claim 11, 22 and 24, Haddadin et al. in view of Liu discloses all as applied to claim 1, 12 and 23 above, Haddadin et al. further teaches;
wherein the processing logic/one or more hardware components is one of (optional) a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) (column 12 lines 20-23: The filters may be implemented in hardware, e.g. an ASIC or FPGA) or a digital signal processor (DSP).
Claim 3-6 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Haddadin et al. (US 8725785 B1 previously cited) in view of Liu (NPL titled “A High Speed Digital Decimation Filter with Parallel Cascaded Integrator-Comb Pre-Filters," 2009 2nd International Congress on Image and Signal Processing, Tianjin, China, 2009, pp. 1-4”) further in view of Wozniak et al. (US 2020/0186744 A1 previously cited).
Regarding Claim 3 and 14, Haddadin et al. in view of Liu discloses all as applied to claim 1 and 12, including receiving and preforming the filter operation on the two or more input samples of data values in parallel (e.g. Fig. 1) as detailed above, however, they do not explicitly teach the two or more input samples are received in a:
frame.
On the other hand, Wozniak et al. discloses (Fig. 11, 12) receiving two or more brightness characterization input sample data values in a:
frame (Fig. 2, 11, 12, Para. [0023]: “frame 42”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that The IIR filter 100 (Fig. 1) accepting N parallel-input samples data values 118 in Haddadin et al. in view of Liu’s invention can be implemented in a frame as taught by Wozniak et al. where doing so would (Wozniak et al., Para. [0002], [0024]) allow for “identifying” and “mitigating”, removing or “modifying” undesirable, erroneous or otherwise user-specified samples of data values in the filtered samples of data values.
Regarding Claim 4 and 15, Haddadin et al. in view of Liu further in view of Wozniak et al. discloses all as applied to claim 3 and 14 above, where Wozniak et al. further teaches;
wherein there are more than two input samples of data values in the frame (Fig. 2, Para. [0024: “frame 42 including a plurality of pixels 44”, i.e. plurality of input samples of data values).
Regarding Claim 5 and 16, Haddadin et al. in view of Liu further in view of Wozniak et al. discloses all as applied to claim 4 and 15 above, where Wozniak et al. further teaches;
wherein there are N input samples in the frame (Fig. 2, Para. [0024: “frame 42 including a plurality of pixels 44”, i.e. plurality of input samples of data values), where N is a positive integer (Fig. 2: n positive sample data values) and wherein the performing, with processing logic, the polyphase decomposition of the recursive filter operation decomposes the recursive filter operation into N filter operations for filtering each of N input samples of data values (Fig, 12: IIR filter 58, i.e. recursive filter operation, performs N filter operation on the N input samples in the frame 42).
Regarding Claim 6 and 17, Haddadin et al. in view of Liu further in view of Wozniak et al. discloses all as applied to claim 5 and 16 above, where Wozniak et al. further teaches;
wherein a magnitude of N is dictated by storage considerations (Fig. 2, 12: the N sample data values are stored in finite storage device 204 ) and/or (optional limitation not addressed) power considerations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMNEET SINGH whose telephone number is (571)272-2414. The examiner can normally be reached 9:30am to 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sam K Ahn can be reached at 5712723044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMNEET SINGH/Examiner, Art Unit 2633 /SAM K AHN/Supervisory Patent Examiner, Art Unit 2633