Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7 February 2025 has been entered.
Response to Arguments
Applicant's arguments filed on 7 February 2025 have been fully considered but they are not persuasive.
In the remarks, Applicant argued in substance that:
(a) Applicant argues that support for such amendments is found, inter alia, in paragraph [0020-0023] of the present application regarding 112(a), written description, rejections for claim 1-18.
(b) Applicant also argues that “disclosing that the "CPU scheduler 155 therefore assigns threads for virtual cores 166, 168, and 176 to available PCPU cores," as in the Zaroo excerpt relied upon, does not teach or suggest "wherein the apparatus is configured such that a virtual processing core for performing one or more virtual functions is capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core such that at least one of the at least portion of the first processing core or the at least portion of the second processing core includes only a part thereof," as claimed by applicant.
Examiner respectfully traversed Applicant’s remarks:
As to point (a), the amendment filed on 23 February 2024 adds the following limitation to independent claims 1, 7, and 13: “a virtual processing core for performing one or more virtual functions is capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core” (emphasis added). Under 35 U.S.C. 112(a) (pre-AIA 35 U.S.C. 112, first paragraph), the specification must describe the claimed invention in sufficient detail that a person of ordinary skill in the art (POSITA) would reasonably conclude that the inventor had possession of the claimed invention at the time of filing. Mere background discussion or general statements of functionality without structural or descriptive support for the specific claimed limitation do not satisfy the written description requirement.
The specification passages relied upon by Applicant (e.g., paragraphs [0020]-[0023], and the disclosure of component 10-204 and component 10-214 such as paragraph [0109] and paragraph [0114]) provide high-level descriptions of virtualization technology and example components. For example, Paragraphs [0020]-[0023] generally describe virtualization techniques and examples (e.g., x86 virtualization, IOMMU, SR-IOV, memory/IO virtualization). These passages identify known virtualization mechanisms and discuss general virtualization concepts, but do not expressly describe or disclose a “virtual processing core for performing one or more virtual functions” that “is capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core.”
In addition, paragraph [0109] (Figure 10-2) states that “Component 10-204 may be a first type of virtualized core (or just virtual core or VC) comprising three cores,” and the specification elsewhere indicates this virtualized core may use two cores of SuperCore1 and one core of SuperCore2. Paragraph [0114] describes component 10-214 as “a circuit that performs one or more auxiliary and/or ancillary functions, helper functions, acceleration functions, co-processing functions, behaviors, etc. to one or more CPU cores.” These disclosures describe particular example components and possible auxiliary circuitry, but do not explicitly disclose the specific limitation recited in the amended claims, “virtual processing core for performing one or more virtual functions” that is “capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core.”
Specifically, the specification fails to provide adequate written-description support for the claim language for at least the following reasons:
a) No explicit disclosure of a “virtual processing core for performing one or more virtual functions.” The specification does not define or describe a “virtual processing core” in terms that clearly identify a structure or combination of structures that performs “one or more virtual functions.” The statements about a “virtualized core comprising two cores” do not equate to an explicit disclosure that such a virtual core “performs one or more virtual functions” as that phrase is newly amended on 23 February 2024.
b) No explicit disclosure that such a virtual processing core “is capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core.” While the specification describes a virtualized core that in an example uses cores from SuperCore1 and SuperCore2, it does not describe (with adequate specificity) that a single “virtual processing core” performing virtual functions can be realized by being virtualized using distinct portions of two different physical processing cores. The specification does not define what is meant by “portion” (e.g., hardware contexts, threads, functional units, time-slices, logical cores, micro-architectural resources), nor does it describe a concrete embodiment showing how portions of two distinct processing cores combine to form or realize the claimed “virtual processing core” that performs virtual functions.
c) Background and examples insufficient. General background descriptions of virtualization methods, and general examples of components (10-204, 10-214), without a clear, specific description or definition tying those examples to the precise claim limitation, do not reasonably convey to a POSITA that the inventor possessed the claimed subject matter at the time of filing. The specification’s general discussion of virtualization and standalone description of auxiliary circuitry do not amount to the specific structural and functional disclosure required to support the new limitation.
Thus, 112(a) rejections, written description, for claims 1-18 are sustained.
As to point (b), the Examiner’s rejection is not based solely on Zaroo paragraph [0037]. As set forth in the Office action, the rejection relies on Linley as the primary reference teaching virtual cores that can comprise multiple physical cores or portions of a physical core, with Kim and Zaroo providing structural elements (multiple cores, inter-core communication/bus, load balancing/task assignment) and scheduling/weighting teachings. Applicant’s response focuses narrowly on Zaroo’s thread assignment statement without addressing Linley’s explicit teaching that a single virtual core can be composed of multiple physical cores or only a portion of a physical core, nor does Applicant explain why Linley’s teaching would not be combined with the structural teachings of Kim and the scheduling teachings of Zaroo.
Zaroo discloses the CPU scheduler assigns threads for virtual cores to available PCPU cores according to ratios (e.g., 60:60:40). That teaching, together with Linley’s explicit statement that “a single virtual core can comprise multiple physical cores or only a portion of a physical core,” provides the person of ordinary skill with a clear disclosure and teachable basis for virtualizing a virtual processing core across portions of multiple physical cores (e.g., allocating PCPU time/threads according to weights, partitioning physical core resources among virtual cores).
The claim discloses “capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core,” which covers virtualization implemented by allocation/assignment of processing time, threads, contexts, or other partitioning of a physical core’s resources. Zaroo’s thread-assignment/weighting teaching directly implicates allocation of PCPU time/portions to virtual cores. Linley provides the explicit concept that virtual cores can be built from parts of physical cores. Kim discloses multi-core structures and interconnects. The combination therefore teaches the claimed capability.
Clear motivations are set forth in Office Action: Linley’s goal to implement virtual cores and improve utilization of the virtual cores; Kim’s teachings of multi-core structures and load balancing/task assignment across cores; and Zaroo’s scheduling/weighting approach to allocate PCPU resources among virtual cores in an intelligent manner. Applicant’s argument does not provide evidence of incompatibility among these teachings or explain why a POSITA would not have combined them. Absent such technical showing, the Examiner’s conclusion that a POSITA would have been motivated to combine is supported.
Applicant’s recitation of the three legal criteria for obviousness (motivation, expectation, and teaching of all limitations) is correct as a legal standard, but merely restating the standard without pointing to specific deficiencies in the Examiner’s factual findings or specific persuasive evidence (e.g., teachings that the references are incompatible, a teaching away, or objective indicia of nonobviousness) is insufficient to rebut the prima facie case. Applicant asserts Zaroo does not teach the recited limitation, but fails to address how Linley’s explicit teaching of virtual cores composed of physical core portions and the scheduling/allocation teachings of Zaroo together would not amount to the claimed capability. Mere disagreement or conclusory statements that Zaroo alone does not teach the limitation do not overcome the Examiner’s articulated showing that the combination of references does.
Thus, 103 rejections for claims 1-18 are sustained.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The amended claims 1, 7, and 13 filed on 23 February 2024 disclose “a virtual processing core for performing one or more virtual functions is capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core.” Nonetheless, the original specification does not provide any substantiation for this.
For instance, the specification of instant application discloses “Component 10-204 may be a first type of virtualized core (or just virtual core or VC) comprising three cores” (FIGURE 10-2, paragraph [0109]), “Component 10-214 may be a circuit that performs one of more auxiliary and/or ancillary functions, helper functions, acceleration functions, co-processing functions, behaviors, etc. to one of more CPU cores” (paragraph [0114]). In other words, virtualized core 10-204 uses two cores of SuperCore 1 and one core of SuperCore 2 while component 214 performs various functions to one or more CPU cores, however, the specification is silent with the amended limitations “a virtual processing core for performing one or more virtual functions” (emphasis added).
In addition, paragraphs [0020]-[0023] are high-level background about virtualization technology (what virtualization is; examples such as x86 hardware virtualization, IOMMU, SR-IOV, etc.). They do not describe the specific structural/functional disclosure required by the first paragraph of 35 U.S.C. 112 (pre-AIA ) / 112(a): that the inventor possessed a “virtual processing core for performing one or more virtual functions [that] is capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core.” requires the specification to reasonably convey to a person of ordinary skill in the art that the inventor possessed the claimed invention. Mere background descriptions or recitation of general techniques (virtualization, SR-IOV, IOMMU, etc.) ordinarily do not supply written-description support for a new structural limitation that claims a virtual core composed by using portions of two distinct physical cores.
Based on the analysis, it is determined that the amended claims 1, 7, and 13, along with their dependent claims, do not meet the written description requirement under 35 USC § 112(a). Therefore, they are rejected.
Claims 2-6, 8-12, and 14-19 are rejected as they depend on the respective parent claims that have already been rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Linley Gwennap (SOFT MACHINES TARGETS IPC BOTTLENECK, October 27, 2014, hereinafter Linley) in view of Kim et al. (US 2011/0107344, hereinafter Kim) and Zaroo (US 2011/0231857, hereinafter Zaroo).
Regarding claim 1, Linley discloses
An apparatus, comprising:
a processing unit including a plurality of processing cores including a first processing core and a second processing core (Fig. 3 physical cores);
wherein the apparatus is configured such that a virtual processing core is capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core such that at least one of the at least portion of the first processing core or the at least portion of the second processing core includes only a part thereof (Figure 3. Soft Machines virtual cores. A single virtual core can comprise multiple physical cores or only a portion of a physical core; page 3 right column: Soft Machines calls this approach “virtual cores.” From a software viewpoint, the heavy thread runs on a single virtual core that comprises more than one physical core, while the light thread runs on a virtual core that uses only a portion of a physical core).
Linley does not disclose a processing unit including a plurality of processing cores for executing program instructions including a first processing core and a second processing core connected via a first communication bus. Kim discloses a processing unit including a plurality of processing cores (paragraph [0089]: the single core OS 620 is running on the virtual cores 610, and the virtual cores 610 can use the multiple cores 210 and 220 efficiently with the load balancer 100 ... because the task switched to the sleep mode at the first core 210 is assigned to be efficiently executed at the second core 220 by the load balancer 100, the single core OS can be used on all of the cores) for executing program instructions (paragraph [0089]: because the task switched to the sleep mode at the first core 210 is assigned to be efficiently executed at the second core 220 by the load balancer 100, the single core OS can be used on all of the cores; paragraph [0090]: In view of each virtual core, the first cores 210, i.e., the cores transmitting the instructions and receiving the responses, are not needed to be identical with each other) including a first processing core and a second processing core connected via a first communication bus (paragraph [0029]: The bus 230 establishes an electrical pass for exchanging information and signals between the cores 210 and 220). It would have been obvious to one of ordinary skill in the art at the time the claimed invention was effectively filed to modify the teaching of Liney by executing a task on a virtual core using first core and second core connected via a bus of Kim. The motivation would have been to provide a multi-core apparatus and load balancing method of a multi-core apparatus that is capable of efficiently utilizing virtual cores (Kim paragraph [0011]).
Linley in view of Kim does not disclose a virtual processing core for performing one or more virtual functions is capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core. Zaroo discloses a virtual processing core for performing one or more virtual functions is capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core (paragraph [0037]: The virtualization software then takes the two threads created by the VMM (not shown) for VM 160, one thread for each virtual core, and assigns PCPU time according to the weight of 60. VM 170, having a single virtual core and an assigned weight of 40, will have a thread corresponding to virtual core 176 with a weight of 40. CPU scheduler 155 therefore assigns threads for virtual cores 166, 168, and 176 to available PCPU cores according to the ratio 60:60:40, respectively). It would have been obvious to one of ordinary skill in the art at the time the claimed invention was effectively filed to modify the teaching of Liney in view of Kim by assigning threads created by VMM for virtual cores to available PCPU cores according to the ratio (e.g., 60:60:40, respectively) of Zaroo. The motivation would have been to provide a method for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC) (Zaroo abstract).
Regarding claim 7 referring to claim 1, Linley discloses A computer program product embodied on a non-transitory computer readable medium, comprising: code for cooperating with ... (page 3 left column: VISC processor can be viewed as having global hardware for branch prediction as well as for fetching, grouping, tracking, and retiring instructions, but local hardware for scheduling and executing instructions and accessing memory).
Regarding claim 13 referring to claim 1, Linley discloses A method, comprising: cooperating with ... (See the rejection for claim 1).
Regarding claims 2, 8, and 14, Linley discloses
wherein the processing unit includes a central processing unit (page 1 left column: Soft Machines disclosed a new CPU technology that greatly improves performance on single-threaded applications; page 3 left column: Figure 3 shows an example with two active threads: one heavy (high performance) and one light. In a processor with several identical cores, each thread would run on one core, wasting cycles for the light thread and limiting performance for the heavy thread. In a VISC design with two physical cores, the heavy thread is split into two hardware threads, one running on each core. Note that the second core automatically shares its resources between the heavy thread and the light thread, because a VISC core can mix instructions from multiple threadlets).
Regarding claims 3, 9, and 15, Linley discloses
wherein the apparatus is configured such that at least one of the at least portion of the first processing core or the at least portion of the second processing core include a subset of circuits thereof (Figure 3. Soft Machines virtual cores. A single virtual core can comprise multiple physical cores or only a portion of a physical core; page 3 right column: Soft Machines calls this approach “virtual cores.” From a software viewpoint, the heavy thread runs on a single virtual core that comprises more than one physical core, while the light thread runs on a virtual core that uses only a portion of a physical core).
Regarding claims 4, 10, and 16, Linley discloses
wherein the apparatus is configured such that at least one of the at least portion of the first processing core or the at least portion of the second processing core include a subset of functionality thereof (Figure 3. Soft Machines virtual cores. A single virtual core can comprise multiple physical cores or only a portion of a physical core; page 3 right column: Soft Machines calls this approach “virtual cores.” From a software viewpoint, the heavy thread runs on a single virtual core that comprises more than one physical core, while the light thread runs on a virtual core that uses only a portion of a physical core).
Regarding claims 5, 11, and 17, Linley discloses
wherein the apparatus is configured such that the part includes a fractional part (Figure 3. Soft Machines virtual cores. A single virtual core can comprise multiple physical cores or only a portion of a physical core; page 3 right column: Soft Machines calls this approach “virtual cores.” From a software viewpoint, the heavy thread runs on a single virtual core that comprises more than one physical core, while the light thread runs on a virtual core that uses only a portion of a physical core).
Regarding claims 6, 12, and 18, Linley discloses
wherein the apparatus is configured such that the apparatus is configured such that the virtual processing core is capable of being virtualized utilizing the at least portion of the first processing core and the at least portion of the second processing core such that both the at least portion of the first processing core and the at least portion of the second processing core include only a part thereof (Figure 3. Soft Machines virtual cores. A single virtual core can comprise multiple physical cores or only a portion of a physical core; page 3 right column: Soft Machines calls this approach “virtual cores.” From a software viewpoint, the heavy thread runs on a single virtual core that comprises more than one physical core, while the light thread runs on a virtual core that uses only a portion of a physical core).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Linley in view of Kim and Zaroo as applied to claim 1, and further in view of Saeki (US 2017/0063979, hereinafter Saeki).
Regarding claim 19, Linley in view of Kim and Zaroo discloses wherein the one or more virtual functions is used in conjunction with Single Root I/O (“SR-IOV”). Saeki discloses wherein the one or more virtual functions is used in conjunction with Single Root I/O (“SR-IOV”) (paragraph [0027]: a user data processing device configured on a virtual machine, by using general-purpose functions such as SRIOV (Single Root I/O Virtualization) and a VF (Virtual Function) pass-through function, enables communication with the outside from a Guest OS (virtual machine) side via directly an NIC without passing through a host OS); paragraph [0043]: The present invention enables processing performance of user data packets to be scaled in accordance with the number of CPU cores; paragraph [0051]: A data plane packet processing device is achieved as software on a virtual machine that is configured through virtualization on a multi-core CPU mounted on a general-purpose server. The multi-core CPU is provided with a plurality of CPU cores; paragraph [0073]: the 0-th packet processing virtual machine 17-0 includes a plurality of CPU cores 18-0 to 18-m); paragraph [0074]: the plurality of queues 15-0 to 15-m individually correspond to the plurality of CPU cores 18-0 to 18-m which are assigned to the 0-th packet processing virtual machine 17-0. To the 0 to m-th queues 15-0 to 15-m, queue numbers of #0 to #m are individually assigned). It would have been obvious to one of ordinary skill in the art at the time the claimed invention was effectively filed to modify the teaching of Linley in view of Kim and Zaroo by enables processing performance of user data packets to be scaled through virtualization on a plurality of CPU cores included in the packet processing virtual machine by using general-purpose functions such as SRIOV (Single Root I/O Virtualization) of Saeki. The motivation would have been t enables processing performance of user data packets to be scaled in accordance with the number of CPU cores (Saeki paragraph [0043]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Naveh et al. (US 2014/0129808) discloses “the task controller can be configured to communicate with an advanced programmable interrupt controller (APIC) of the processor to thus provide virtualization between a virtual core to which the OS allocates a task and a physical core on which the task is actually executing” (paragraph [0017]), “different types of hardware or physical cores can be present, including a plurality of so-called large cores 1250-125n (generically large core 125), and a plurality of so-called small cores 1300-130 n, (generically small core 130) (note that different numbers of large and small cores may be present” (paragraph [0019]), “More specifically, via OS scheduler 155 threads, e.g., 0 and 1 of OS run queue 1500, can be scheduled to virtual core 1650, which the OS associates with large core 1250 and the threads 2 and 3 of run queue 150n can be scheduled to virtual core 165n, which the OS associates with large core 125n” (paragraph [0031]), and “the various cores may be coupled via an interconnect 615 to a system agent or uncore 620 that includes various components” (paragraph [0063]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISLEY N. KIM whose telephone number is (571)270-7832. The examiner can normally be reached M-F 11:30AM -7:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y. Blair can be reached on (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SISLEY N KIM/Primary Examiner, Art Unit 2196 10/15/2025