DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Amendments
Acknowledgment of receiving amendments to the claims, which were received by the Office on 03/12/2026.
Response to Arguments
Applicant's arguments filed 03/12/2026 have been fully considered but they are not persuasive.
In that remarks, applicant argues in substance:
Applicant argues: “The Office concedes, for example, that Kim does not teach such "connection units," but the Office then turns to Blanquart and particularly that reference's interconnect 321, pixel column bus 330, and circuit column bus 340-to overcome this deficiency. Office Action, P17-18. But even if the Office's position here is reasonable, which Applicant does not concede, one electrode of the "electrically conductive unit" of each recited "connection unit" is now required to be connected to a "signal line" "to which a ... signal based on an electrical charge converted by the ... photoelectric converting unit" is output. While Kim describes that each of its pixel columns 352 is associated with and electrically connected to one read bus 330, there is no description of those read buses 330 being connected to those pixel columns 352 by way of such a "signal line." See Kim,[01117]. Applicant accordingly submits that amended claim 27 is allowable over the applied combination of Kim and Blanquart.”
Examiner’s Response: Examiner respectfully disagrees. Blanquart is seen to disclose a connection unit that includes a first electrode electrically connected to the first signal line and a second electrode arranged such that the first electrode and the second electrode face each other in a third direction in which the first semiconductor chip and the second semiconductor chip are stacked.
The bus 330 of Blanquart is a signal line. As seen in Figures 3p and 3q of Blanquart, the connection unit is considered to be a pair of connecting interconnects 321 that are formed on both substrates. The interconnects may be “solder bumps or solder balls, vias or other forms of electrical communication” (Paragraph 0110). Therefore, the interconnects 321 are electrodes and face each other in a third direction in which the first semiconductor chip and the second semiconductor chip are stacked. Interconnect 321 of substrate 310 is connected to a respective signal line (bus 330).
Therefore, Blanquart is seen to teach the first connection unit. The second and third connection units have the same structure for respective signal lines.
Examiner notes applicant’s specification “plurality of bumps 109” (connection unit) of Applicant’s Figure 2 is never described as having a first electrode or a second electrode. Applicant’s specification does not appear to recite “electrode”.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a first signal converting unit”, “a second signal converting unit”, “a third signal converting unit”, “a first generating unit“, “a second generating unit“, “a third generating unit“ in claims 27-45.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 27-29 and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 6,937,279 B1) in view of Blanquart (US 2012/0307030 A1).
Regarding claim 27, Kim et al. (hereafter referred as Kim) teaches an image sensor (Kim, Fig. 4) comprising:
a semiconductor chip (Kim, Fig. 4, Column 2, Lines 35-40) that includes
a first region including a first photoelectric converting unit that converts light into electrical charges (Kim, Fig. 4, pixel array 50, Column 1, Lines 15-19, Column 2, Lines 41-52, A first region may be the upper right quadrant of pixel array 50. A first photoelectric converting unit may be an R pixel/photodiode in the first region.),
a second region including a second photoelectric converting unit that converts light into electrical charges, the second photoelectric converting unit being arranged side by side in a first direction with the first photoelectric converting unit (Kim, Fig. 4, pixel array 50, A second region may be the upper left quadrant of pixel array 50. A second photoelectric converting unit may be a G pixel/photodiode in the second region.), and
a third region including a third photoelectric converting unit that converts light into electrical charges, the third photoelectric converting unit being arranged side by side in a second direction with the first photoelectric converting unit, the second direction intersecting with the first direction (Kim, Fig. 4, pixel array 50, A third region may be the bottom right quadrant of pixel array 50. A third photoelectric converting unit may be a B pixel/photodiode in the third region.);
a wiring layer that includes
a first signal line, to which a first signal based on an electrical charge converted by the first photoelectric converting unit is output (Kim, Fig. 4, A first signal line is the pixel output line connecting the first photoelectric converting unit to its corresponding comparators 603A.),
a second signal line, to which a second signal based on an electrical charge converted by the second photoelectric converting unit is output (Kim, Fig. 4, A second signal line is the pixel output line connecting the second photoelectric converting unit to its corresponding comparators 603A or 603B.), and
a third signal line, to which a third signal based on an electrical charge converted by the third photoelectric converting unit is output (Kim, Fig. 4, A third signal line is the pixel output line connecting the third photoelectric converting unit to its corresponding comparators 603B.);
a first signal converting unit for converting, using a first ramp signal (Kim, Fig. 4, reference voltage generator 601C), the first signal output to the first signal line into a digital signal (Kim, Fig. 4, analog-to-digital conversion unit 60/comparators 603A, Column 2, Lines 53-67, Column 3, Lines 1-29, The first signal converting unit is the comparators 603A connected to the first photoelectric converting unit (red).),
a second signal converting unit for converting, using a second ramp signal (Kim, Fig. 4, reference voltage generator 601B), the second signal outputted to the second signal line into a digital signal the first ramp signal and the second ramp signal having different inclinations (Kim, Fig. 4, analog-to-digital conversion unit 60/comparators 603A/B, Column 2, Lines 53-67, Column 3, Lines 1-29, The second signal converting unit is the comparators 603A or 603B connected to the second photoelectric converting unit (green).), and
a third signal converting unit for converting, using a third ramp signal (Kim, Fig. 4, reference voltage generator 601A), the third signal outputted to the third signal line, the first ramp signal and the third ramp signal having different inclinations, the second semiconductor chip being stacked with the first semiconductor chip (Kim, Fig. 4, analog-to-digital conversion unit 60/comparators 603B, Column 2, Lines 53-67, Column 3, Lines 1-29, The third signal converting unit is the comparator 603B connected to the third photoelectric converting unit (blue).).
However, Kim does not teach a first semiconductor chip that includes the first region, the second region and the third region; a second semiconductor chip that includes the first signal converting unit, the second signal converting unit, and the third signal converting unit; a first connection unit, to which the first signal read out from the first region is output, that electrically connects the first semiconductor chip and the second semiconductor chip; a second connection unit, to which the second signal read out from the second region is output, that electrically connects the first semiconductor chip and the second semiconductor chip; and a third connection unit, to which the third signal read out from the third region is output, that electrically connects the first semiconductor chip and the second semiconductor chip, wherein the first connection unit has a first electrically conductive unit that includes a first electrode electrically connected to the first signal line and a second electrode arranged such that the first electrode and the second electrode face each other in a third direction in which the first semiconductor chip and the second semiconductor chip are stacked, the second connection unit has a second electrically conductive unit that includes a third electrode electrically connected to the second signal line and a fourth electrode arranged such that the third electrode and the fourth electrode face each other in the third direction, and the third connection unit has a third electrically conductive unit that includes a fifth electrode electrically connected to the third signal line and a sixth electrode arranged such that the fifth electrode and the sixth electrode face each other in the third direction.
In reference to Blanquart, Blanquart teaches a first semiconductor chip first substrate 310, Paragraphs 0024 and 0111 that includes
a first region including a first photoelectric converting unit (Blanquart, Fig. 3N , A first region may be the upper right quadrant of the pixel array.),
a second region including a second photoelectric converting unit (Blanquart, Fig. 3N , A second region may be the upper left quadrant of the pixel array.), and
a third region including a third photoelectric converting unit (Blanquart, Fig. 3N , A third region may be the bottom right quadrant of the pixel array. The third photoelectric converting unit may be a pixel in the third region on a different column from the first photoelectric converting unit.);
a wiring layer (Blanquart, Fig. 3n-3q, layer of buses 330, Paragraph 0114) that includes
a first signal line, to which a first signal based on an electrical charge converted by the first photoelectric converting unit is output (Blanquart, Fig. 3n-3q, Bus 330 of the first photoelectric converting unit.),
a second signal line, to which a second signal based on an electrical charge converted by the second photoelectric converting unit is output (Blanquart, Fig. 3n-3q, Bus 330 of the second photoelectric converting unit.), and
a third signal line, to which a third signal based on an electrical charge converted by the third photoelectric converting unit is output (Blanquart, Fig. 3n-3q, Bus 330 of the third photoelectric converting unit.);
a second semiconductor chip (Blanquart, Fig. 3n, second substrate 311, Paragraphs 0024, 0109 and 0116 and 0120-0121) that includes
a first signal converting unit for converting the first signal outputted to the first signal line into a digital signal (Blanquart, Fig. 3n, support circuit 370, Paragraph 0106, 0109 and 0116, “…supporting circuitry 370a, which may comprise an analog to digital converter 317a…”, A first signal converting unit is a support circuit 370 connected to the first photoelectric converting unit ),
a second signal converting unit for converting the second signal outputted to the second signal line into a digital signal (Blanquart, Fig. 3n, support circuit 370, A second signal converting unit is a support circuit 370 connected to the second photoelectric converting unit ), and
a third signal converting unit for converting a third signal outputted to the third signal line into a digital signal (Blanquart, Fig. 3n, support circuit 370, A third signal converting unit is a support circuit 370 connected to the third photoelectric converting unit ), the second semiconductor chip being stacked with the first semiconductor chip (Blanquart, Figs. 3n-3q);
a first connection unit, to which the first signal read out from the first region is output, that electrically connects the first semiconductor chip and the second semiconductor chip (Blanquart, Figs. 3n-3q, interconnect 321, Paragraphs 0110 and 0121, The first connection unit is the interconnect 321 of the first photoelectric converting unit and the first signal converting unit.);
a second connection unit, to which the second signal read out from the second region is output, that electrically connects the first semiconductor chip and the second semiconductor chip (Blanquart, Figs. 3n-3q, interconnect 321, Paragraph 0121, The second connection unit is the interconnect 321 of the second photoelectric converting unit and the second signal converting unit.); and
a third connection unit, to which the third signal read out from the third region is output, that electrically connects the first semiconductor chip and the second semiconductor chip (Blanquart, Figs. 3n-3q, interconnect 321, pixel column bus 330 and circuit column bus 340, Paragraph 0121, The third connection unit is the interconnect 321 of the third photoelectric converting unit and the third signal converting unit.), wherein
the first connection unit has a first electrically conductive unit that includes a first electrode (Blanquart, Fig. 3p-3q, interconnect 321 of substrate 310) electrically connected to the first signal line and a second electrode (Blanquart, Fig. 3p-3q, Interconnect 321 of substrate 311 corresponding to the first electrode.) arranged such that the first electrode and the second electrode face each other in a third direction in which the first semiconductor chip and the second semiconductor chip are stacked (Blanquart, Figs. 3n-3q, interconnect 321 of the first connection unit, Paragraph 0121),
the second connection unit has a second electrically conductive unit that includes a third electrode electrically connected to the second signal line and a fourth electrode arranged such that the third electrode and the fourth electrode face each other in the third direction (Blanquart, Figs. 3n-3q, interconnect 321 of the second connection unit includes third and fourth electrodes, Paragraph 0121), and
the third connection unit has a third electrically conductive unit that includes a fifth electrode electrically connected to the third signal line and a sixth electrode arranged such that the fifth electrode and the sixth electrode face each other in the third direction (Blanquart, Figs. 3n-3q, interconnect 321 of the third connection unit includes fifth and sixth electrodes, Paragraph 0121).
These arts are analogous since they are both related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Kim with the placement of conversion circuits on a separate stacked substrate as seen in Blanquart to reduce the footprint of the imaging device and keeping the pixel array size constant and optimized to the fullest extent possible (Blanquart, Paragraph 0102).
Regarding claim 28, the combination of Kim and Blanquart teaches the image sensor according to Claim 27 (see claim 27 analysis), wherein
at least one of the first and second electrodes is arranged between the first region and the first signal converting unit in the third direction (Blanquart, Figs. 3n-3q, interconnect 321 of the first connection unit, Paragraph 0121),
at least one of the third and fourth electrodes is arranged between the second region and the second signal converting unit in the third direction (Blanquart, Figs. 3n-3q, interconnect 321 of the second connection unit, Paragraph 0121), and
at least one of the fifth and sixth electrodes is arranged between the third region and the third signal converting unit in the third direction (Blanquart, Figs. 3n-3q, interconnect 321 of the third connection unit, Paragraph 0121).
Regarding claim 29, the combination of Kim and Blanquart teaches the image sensor according to Claim 28 (see claim 28 analysis), wherein
the first signal line is arranged between the first region and at least one of the first and second electrodes in the third direction (Blanquart, Figs. 3n-3q, Paragraph 0129, The CMOS image sensor chip is a back side illuminated substrate. Therefore, wiring layers are located on the frontside opposite the side of incident light. The first region is considered to be the upper region of substrate 310. Pixel column bus 330 is between the top surface and the interconnect 321.),
the second signal line is arranged between the second region and at least one of the third and fourth electrodes in the third direction (Blanquart, Figs. 3n-3q, The second region is considered to be the upper region of substrate 310. Pixel column bus 330 is between the top surface and the interconnect 321.), and
the third signal line is arranged between the third region and at least one of the fifth and sixth electrodes in the third direction (Blanquart, Figs. 3n-3q, The third region is considered to be the upper region of substrate 310. Pixel column bus 330 is between the top surface and the interconnect 321.).
Regarding claim 31, the combination of Kim and Blanquart teaches the image sensor according to Claim 27 (see claim 27 analysis), wherein
the second semiconductor chip includes a first generating unit that generates the first ramp signal, a second generating unit that generates the second ramp signal, and a third generating unit that generates the third ramp signal (Kim, Fig. 4, reference voltage generating units 601A, 601B and 601C, Blanquart, Fig. 3n-q, Support circuits are placed on the support substrate.).
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 6,937,279 B1) in view of Blanquart (US 2012/0307030 A1) in view of Yang (US 6809769 B1).
Regarding claim 30, the combination of Kim and Blanquart teaches the image sensor according to Claim 28 (see claim 28 analysis). However, the combination of Kim and Blanquart does not teach wherein each of the first, second, and third electrically conductive units is composed of copper.
In reference to Yang, Yang teaches electrically conductive units are composed of copper (Yang, Figs. 4-5, connections 405, conductive points 512-513, Column 5, Lines 50-54).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim and Blanquart with the teaching of copper connections as seen in Yang since it is a well-known conductive material and would provide similar and expected results for connecting the substrates.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 6,937,279 B1) in view of Blanquart (US 2012/0307030 A1) in view of Shizukuishi (US 2004/0021788 A1) in view of Kishi (US 2013/0033632 A1).
Regarding claim 32, the combination of Kim and Blanquart teaches the image sensor according to Claim 28 (see claim 28 analysis). However, the combination of Kim and Blanquart does not teach comprising: a third semiconductor chip configured to store a first digital signal that has been converted from the first signal in the first signal converting unit, store a second digital signal that has been converted from the second signal in the second signal converting unit, and store a third digital signal that has been converted from the third signal in the third signal converting unit, the third semiconductor chip being stacked with the first semiconductor chip.
In reference to Shizukuishi, Shizukuishi teaches storing a first digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038) that has been converted from a first signal in a first signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The first signal converting unit is a signal processing circuit for a first pixel.),
storing a second digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038) that has been converted from a second signal in a second signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The second signal converting unit is a signal processing circuit for a second pixel.), and
storing a third digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038) that has been converted from a third signal in a third signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The third signal converting unit is a signal processing circuit for a third pixel.).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim and Blanquart with the memory circuit as seen in Shizukuishi to allow the image sensor to store one or more frames of images (Shizukuishi, Paragraph 0039).
However, the combination of Kim, Blanquart and Shizukuishi does not the third semiconductor chip being stacked with the first semiconductor chip.
In reference to Kishi, Kishi teaches a first semiconductor chip that includes the plurality of photoelectric converting units (Kishi, Fig. 9, area 1 (first semiconductor substrate), Paragraphs 0058 and 0080);
a second semiconductor chip that includes the plurality of signal converting units (Kishi, Fig. 9, area 2 (second semiconductor substrate), Paragraph 0058 and 0080);
a third semiconductor chip that stores the signals that have been converted into digital signals by the signal converting units (Kishi, Fig. 9, column memory 104, Paragraphs 0056), the third semiconductor chip being stacked with the first semiconductor chip (Kishi, Fig. 9, area 3, Paragraph 0080).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim, Blanquart and Shizukuishi with the memory substrate as seen in Kishi to reduce the footprint of the image sensor by stacking the memory substrate.
Claim(s) 33-34, 36-37 and 39-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 6,937,279 B1) in view of Blanquart (US 2012/0307030 A1) in view of Hirota (US 2010/0141812 A1).
Regarding claim 33, the combination of Kim and Blanquart teaches the image sensor according to Claim 28 (see claim 28 analysis). However, the combination of Kim and Blanquart does not teach wherein the first region includes a fourth photoelectric converting unit that converts light into electrical charges, the fourth photoelectric converting unit being arranged next to the first photoelectric converting unit in the first direction, the second region includes a fifth photoelectric converting unit that converts light into electrical charges, the fifth photoelectric converting unit being arranged next to the second photoelectric converting unit in the first direction, the third region includes a sixth photoelectric converting unit that converts light into electrical charges, the sixth photoelectric converting unit being arranged next to the third photoelectric converting unit in the first direction, the first signal converting unit converts, using the first ramp signal, a fourth signal based on an electrical charge converted by the fourth photoelectric converting unit into a digital signal, the second signal converting unit converts, using the second ramp signal, a fifth signal based on an electrical charge converted by the fifth photoelectric converting unit into a digital signal, and the third signal converting unit converts, using the third ramp signal, a sixth signal based on an electrical charge converted by the sixth photoelectric converting unit into a digital signal.
In reference to Hirota, Hirota teaches wherein a first region (Hirota, Figs. 3 and 12, The first region is the top right quadrant of Figure 12) includes a fourth photoelectric converting unit that converts light into electrical charges, the fourth photoelectric converting unit being arranged next to a first photoelectric converting unit in the first direction (Hirota, Fig. 12, The first and fourth photoelectric converting unit are Red pixels horizontally adjacent in the first region.),
the second region (Hirota, Figs. 3 and 12, The second region is the top left quadrant of Figure 12) includes a fifth photoelectric converting unit that converts light into electrical charges, the fifth photoelectric converting unit being arranged next to the second photoelectric converting unit in the first direction (Hirota, Fig. 12, The second and fifth photoelectric converting unit are Green pixels horizontally adjacent in the second region.),
the third region (Hirota, Figs. 3 and 12, The third region is the bottom right quadrant of Figure 12) includes a sixth photoelectric converting unit that converts light into electrical charges, the sixth photoelectric converting unit being arranged next to the third photoelectric converting unit in the first direction (Hirota, Fig. 12, The third and sixth photoelectric converting unit are Blue pixels horizontally adjacent in the third region.),
a first signal converting unit (Hirota, Fig. 1, column processing unit 14, Paragraphs 0101-0102) converts a first and a fourth signal based on an electrical charge converted by the first and fourth photoelectric converting unit into a digital signal (Hirota, Figs. 1 and 3, The first signal converting unit is the column processing unit 14 connected to the first and fourth photoelectric converting unit through the corresponding vertical signal line 19.),
the second signal converting unit converts a second and a fifth signal based on an electrical charge converted by the second and the fifth photoelectric converting unit into a digital signal (Hirota, Figs. 1 and 3, The second signal converting unit is the column processing unit 14 connected to the second and fifth photoelectric converting unit through the corresponding vertical signal line 19.), and
the third signal converting unit converts a third and a sixth signal based on an electrical charge converted by the third and the sixth photoelectric converting unit into a digital signal (Hirota, Figs. 1 and 3, The third signal converting unit is the column processing unit 14 connected to the third and sixth photoelectric converting unit through the corresponding vertical signal line 19.).
These arts are analogous since they are since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim and Blanquart with the pixel sharing structure (Hirota, Fig. 3) and color filter (Hirota, Fig. 12) to allow for pixel addition of neighboring pixels to increase the frame rate (Hirota, Paragraphs 0121-0122). Further, the limitations “the first signal converting unit converts, using the first ramp signal, a fourth signal based on an electrical charge converted by the fourth photoelectric converting unit into a digital signal, the second signal converting unit converts, using the second ramp signal, a fifth signal based on an electrical charge converted by the fifth photoelectric converting unit into a digital signal, and the third signal converting unit converts, using the third ramp signal, a sixth signal based on an electrical charge converted by the sixth photoelectric converting unit into a digital signal” would be met since the first, second and third ramp signals are used for the red, green and blue pixels, respectively.
Regarding claim 34, the combination of Kim, Blanquart and Hirota teaches the image sensor according to Claim 33 (see claim 33 analysis), wherein
the fourth signal read out from the first region is output to the first electrically conductive unit (Blanquart, Figs. 3n-3q, interconnect 321, Hirota, Figs. 3 and 12, The first and fourth signals are read by the same vertical signal line and same interconnect 321.),
the fifth signal read out from the second region is output to the second electrically conductive unit (Blanquart, Figs. 3n-3q, interconnect 321, Hirota, Figs. 3 and 12, The second and fifth signals are read by the same vertical signal line and same interconnect 321.), and
the sixth signal read out from the third region is output to the third electrically conductive unit (Blanquart, Figs. 3n-3q, interconnect 321, Hirota, Figs. 3 and 12, The third and sixth signals are read by the same vertical signal line and same interconnect 321.).
Regarding claim 36, the combination of Kim, Blanquart and Hirota teaches the image sensor according to Claim 33 (see claim 33 analysis), wherein
the first region includes a seventh photoelectric converting unit that converts light into electrical charges, the seventh photoelectric converting unit being arranged next to the first photoelectric converting unit in the second direction (Hirota, Fig. 12, The seventh photoelectric converting unit is a Red pixel vertically adjacent to the first photoelectric converting unit in the first region.),
the second region includes an eighth photoelectric converting unit that converts light into electrical charges, the eighth photoelectric converting unit being arranged next to the second photoelectric converting unit in the second direction (Hirota, Fig. 12, The eighth photoelectric converting unit is a green pixel vertically adjacent to the second photoelectric converting unit in the second region.),
the third region includes a ninth photoelectric converting unit that converts light into electrical charges, the ninth photoelectric converting unit being arranged next to the third photoelectric converting unit in the second direction (Hirota, Fig. 12, The ninth photoelectric converting unit is a blue pixel vertically adjacent to the third photoelectric converting unit in the third region.),
the first signal converting unit converts, using the first ramp signal, a seventh signal based on an electrical charge converted by the seventh photoelectric converting unit into a digital signal (Kim, Fig. 4, Hirota, Figs. 3 and 12, The seventh photoelectric converting unit is connected to the first signal converting unit. The first ramp signal is used for red pixels.),
the second signal converting unit converts, using the second ramp signal, an eighth signal based on an electrical charge converted by the eighth photoelectric converting unit into a digital signal (Kim, Fig. 4, Hirota, Figs. 3 and 12, The eighth photoelectric converting unit is connected to the second signal converting unit. The second ramp signal is used for green pixels.), and
the third signal converting unit converts, using the third ramp signal, a ninth signal based on an electrical charge converted by the ninth photoelectric converting unit into a digital signal (Kim, Fig. 4, Hirota, Figs. 3 and 12, The ninth photoelectric converting unit is connected to the third signal converting unit. The third ramp signal is used for blue pixels.).
Regarding claim 37, the combination of Kim, Blanquart and Hirota teaches the image sensor according to Claim 36 (see claim 36 analysis), wherein
the seventh signal read out from the first region is output to the first electrically conductive unit (Blanquart, Figs. 3n-3q, interconnect 321, Hirota, Figs. 3 and 12, The first, fourth and seventh signals are read by the same vertical signal line and same interconnect 321.),
the eighth signal read out from the second region is output to the second electrically conductive unit (Blanquart, Figs. 3n-3q, interconnect 321, Hirota, Figs. 3 and 12, The second, fifth and eighth signals are read by the same vertical signal line and same interconnect 321.), and
the ninth signal read out from the third region is output to the third electrically conductive unit (Blanquart, Figs. 3n-3q, interconnect 321, Hirota, Figs. 3 and 12, The third, sixth and ninth signals are read by the same vertical signal line and same interconnect 321.).
Regarding claim 39, the combination of Kim and Blanquart teaches the image sensor according to Claim 28 (see claim 28 analysis). However, the combination of Kim and Blanquart does not teach wherein the first region includes a fourth photoelectric converting unit that converts light into electrical charges, the fourth photoelectric converting unit being arranged next to the first photoelectric converting unit in the second direction, the second region includes a fifth photoelectric converting unit that converts light into electrical charges, the fifth photoelectric converting unit being arranged next to the second photoelectric converting unit in the second direction, the third region includes a sixth photoelectric converting unit that converts light into electrical charges, the sixth photoelectric converting unit being arranged next to the third photoelectric converting unit in the second direction, the first signal converting unit converts, using the first ramp signal, a fourth signal based on an electrical charge converted by the fourth photoelectric converting unit into a digital signal, the second signal converting unit converts, using the second ramp signal, a fifth signal based on an electrical charge converted by the fifth photoelectric converting unit into a digital signal, and the third signal converting unit converts, using the third ramp signal, a sixth signal based on an electrical charge converted by the sixth photoelectric converting unit into a digital signal.
In reference to Hirota, Hirota teaches wherein a first region (Hirota, Figs. 3 and 12, The first region is the top right quadrant of Figure 12) includes a fourth photoelectric converting unit that converts light into electrical charges, the fourth photoelectric converting unit being arranged next to a first photoelectric converting unit in the first direction (Hirota, Fig. 12, The first and fourth photoelectric converting unit are Red pixels vertically adjacent in the first region.),
the second region (Hirota, Figs. 3 and 12, The second region is the top left quadrant of Figure 12) includes a fifth photoelectric converting unit that converts light into electrical charges, the fifth photoelectric converting unit being arranged next to the second photoelectric converting unit in the first direction (Hirota, Fig. 12, The second and fifth photoelectric converting unit are Green pixels vertically adjacent in the second region.),
the third region (Hirota, Figs. 3 and 12, The third region is the bottom right quadrant of Figure 12) includes a sixth photoelectric converting unit that converts light into electrical charges, the sixth photoelectric converting unit being arranged next to the third photoelectric converting unit in the first direction (Hirota, Fig. 12, The third and sixth photoelectric converting unit are Blue pixels vertically adjacent in the third region.),
a first signal converting unit (Hirota, Fig. 1, column processing unit 14, Paragraphs 0101-0102) converts a first and a fourth signal based on an electrical charge converted by the first and fourth photoelectric converting unit into a digital signal (Hirota, Figs. 1 and 3, The first signal converting unit is the column processing unit 14 connected to the first and fourth photoelectric converting unit through the corresponding vertical signal line 19.),
the second signal converting unit converts a second and a fifth signal based on an electrical charge converted by the second and the fifth photoelectric converting unit into a digital signal (Hirota, Figs. 1 and 3, The second signal converting unit is the column processing unit 14 connected to the second and fifth photoelectric converting unit through the corresponding vertical signal line 19.), and
the third signal converting unit converts a third and a sixth signal based on an electrical charge converted by the third and the sixth photoelectric converting unit into a digital signal (Hirota, Figs. 1 and 3, The third signal converting unit is the column processing unit 14 connected to the third and sixth photoelectric converting unit through the corresponding vertical signal line 19.).
These arts are analogous since they are since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim and Blanquart with the pixel sharing structure (Hirota, Fig. 3) and color filter (Hirota, Fig. 12) to allow for pixel addition of neighboring pixels to increase the frame rate (Hirota, Paragraphs 0121-0122). Further, the limitations “the first signal converting unit converts, using the first ramp signal, a fourth signal based on an electrical charge converted by the fourth photoelectric converting unit into a digital signal, the second signal converting unit converts, using the second ramp signal, a fifth signal based on an electrical charge converted by the fifth photoelectric converting unit into a digital signal, and the third signal converting unit converts, using the third ramp signal, a sixth signal based on an electrical charge converted by the sixth photoelectric converting unit into a digital signal” would be met since the first, second and third ramp signals are used for the red, green and blue pixels, respectively.
Regarding claim 40, the combination of Kim, Blanquart and Hirota teaches the image sensor according to Claim 39 (see claim 39 analysis), wherein
the fourth signal read out from the first region is output to the first electrically conductive unit (Blanquart, Figs. 3n-3q, interconnect 321, Hirota, Figs. 3 and 12, The first and fourth signals are read by the same vertical signal line and same interconnect 321.),
the fifth signal read out from the second region is output to the second electrically conductive unit (Blanquart, Figs. 3n-3q, interconnect 321, Hirota, Figs. 3 and 12, The second and fifth signals are read by the same vertical signal line and same interconnect 321.), and
the sixth signal read out from the third region is output to the third electrically conductive unit (Blanquart, Figs. 3n-3q, interconnect 321, Hirota, Figs. 3 and 12, The third and sixth signals are read by the same vertical signal line and same interconnect 321.).
Claim(s) 35, 38 and 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 6,937,279 B1) in view of Blanquart (US 2012/0307030 A1) in view of Hirota (US 2010/0141812 A1) in view of Shizukuishi (US 2004/0021788 A1) in view of Kishi (US 2013/0033632 A1).
Regarding claim 35, the combination of Kim, Blanquart and Hirota teaches the image sensor according to Claim 34 (see claim 34 analysis). However, the combination of Kim, Blanquart and Hirota does not teach comprising: a third semiconductor chip configured to store a first digital signal that has been converted from the first signal in the first signal converting unit, store a second digital signal that has been converted from the second signal in the second signal converting unit, store a third digital signal that has been converted from the third signal in the third signal converting unit, store a fourth digital signal that has been converted from the fourth signal in the first signal converting unit, store a fifth digital signal that has been converted from the fifth signal in the second signal converting unit, and store a sixth digital signal that has been converted from the sixth signal in the third signal converting unit, the third semiconductor chip being stacked with the first semiconductor chip.
In reference to Shizukuishi, Shizukuishi teaches storing a first digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a first digital pixel signal.) that has been converted from a first signal in a first signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The first signal converting unit is a signal processing circuit for a first pixel.),
storing a second digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a second digital pixel signal.) that has been converted from a second signal in a second signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The second signal converting unit is a signal processing circuit for a second pixel.),
storing a third digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a third digital pixel signal.) that has been converted from a third signal in a third signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The third signal converting unit is a signal processing circuit for a third pixel.).
storing a fourth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a fourth digital pixel signal.) that has been converted from a fourth signal in a first signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The fourth pixel is a pixel converted by the same signal processing circuit as the first pixel.),
storing a fifth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a fifth digital pixel signal.) that has been converted from a fifth signal in a second signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The fifth pixel is a pixel converted by the same signal processing circuit as the second pixel.), and
storing a sixth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a sixth digital pixel signal.) that has been converted from a sixth signal in a third signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The sixth pixel is a pixel converted by the same signal processing circuit as the third pixel.).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim, Blanquart and Hirota with the memory circuit as seen in Shizukuishi to allow the image sensor to store one or more frames of images (Shizukuishi, Paragraph 0039).
However, the combination of Kim, Blanquart, Hirota and Shizukuishi does not teach a third semiconductor chip being stacked with the first semiconductor chip.
In reference to Kishi, Kishi teaches a first semiconductor chip that includes the plurality of photoelectric converting units (Kishi, Fig. 9, area 1 (first semiconductor substrate), Paragraphs 0058 and 0080);
a second semiconductor chip that includes the plurality of signal converting units (Kishi, Fig. 9, area 2 (second semiconductor substrate), Paragraph 0058 and 0080);
a third semiconductor chip that stores the signals that have been converted into digital signals by the signal converting units (Kishi, Fig. 9, column memory 104, Paragraphs 0056), the third semiconductor chip being stacked with the first semiconductor chip (Kishi, Fig. 9, area 3, Paragraph 0080).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim, Blanquart, Hirota and Shizukuishi with the memory substrate as seen in Kishi to reduce the footprint of the image sensor by stacking the memory substrate.
Regarding claim 38, the combination of Kim, Blanquart and Hirota teaches the image sensor according to Claim 37 (see claim 37 analysis). However, the combination of Kim, Blanquart and Hirota does not teach comprising: a third semiconductor chip configured to store a first digital signal that has been converted from the first signal in the first signal converting unit, store a second digital signal that has been converted from the second signal in the second signal converting unit, store a third digital signal that has been converted from the third signal in the third signal converting unit, store a fourth digital signal that has been converted from the fourth signal in the first signal converting unit, store a fifth digital signal that has been converted from the fifth signal in the second signal converting unit, and store a sixth digital signal that has been converted from the sixth signal in the third signal converting unit, store a seventh digital signal that has been converted from the seventh signal in the first signal converting unit, store an eighth digital signal that has been converted from the eighth signal in the second signal converting unit, and store a ninth digital signal that has been converted from the ninth signal in the third signal converting unit, the third semiconductor chip being stacked with the first semiconductor chip.
In reference to Shizukuishi, Shizukuishi teaches storing a first digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a first digital pixel signal.) that has been converted from a first signal in a first signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The first signal converting unit is a signal processing circuit for a first pixel.),
storing a second digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a second digital pixel signal.) that has been converted from a second signal in a second signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The second signal converting unit is a signal processing circuit for a second pixel.),
storing a third digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a third digital pixel signal.) that has been converted from a third signal in a third signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The third signal converting unit is a signal processing circuit for a third pixel.).
storing a fourth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a fourth digital pixel signal.) that has been converted from a fourth signal in a first signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The fourth pixel is a pixel converted by the same signal processing circuit as the first pixel.),
storing a fifth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a fifth digital pixel signal.) that has been converted from a fifth signal in a second signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The fifth pixel is a pixel converted by the same signal processing circuit as the second pixel.),
storing a sixth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a sixth digital pixel signal.) that has been converted from a sixth signal in a third signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The sixth pixel is a pixel converted by the same signal processing circuit as the third pixel.),
storing a seventh digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a seventh digital pixel signal.) that has been converted from a seventh signal in a first signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The seventh pixel is a pixel converted by the same signal processing circuit as the first pixel.),
storing an eighth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores an eighth digital pixel signal.) that has been converted from an eighth signal in a second signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The eighth pixel is a pixel converted by the same signal processing circuit as the second pixel.), and
storing a ninth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a ninth digital pixel signal.) that has been converted from a ninth signal in a third signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The ninth pixel is a pixel converted by the same signal processing circuit as the third pixel.).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim, Blanquart and Hirota with the memory circuit as seen in Shizukuishi to allow the image sensor to store one or more frames of images (Shizukuishi, Paragraph 0039).
However, the combination of Kim, Blanquart, Hirota and Shizukuishi does not teach a third semiconductor chip being stacked with the first semiconductor chip.
In reference to Kishi, Kishi teaches a first semiconductor chip that includes the plurality of photoelectric converting units (Kishi, Fig. 9, area 1 (first semiconductor substrate), Paragraphs 0058 and 0080);
a second semiconductor chip that includes the plurality of signal converting units (Kishi, Fig. 9, area 2 (second semiconductor substrate), Paragraph 0058 and 0080);
a third semiconductor chip that stores the signals that have been converted into digital signals by the signal converting units (Kishi, Fig. 9, column memory 104, Paragraphs 0056), the third semiconductor chip being stacked with the first semiconductor chip (Kishi, Fig. 9, area 3, Paragraph 0080).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim, Blanquart, Hirota and Shizukuishi with the memory substrate as seen in Kishi to reduce the footprint of the image sensor by stacking the memory substrate.
Regarding claim 41, the combination of Kim, Blanquart and Hirota teaches the image sensor according to Claim 40 (see claim 40 analysis). However, the combination of Kim, Blanquart and Hirota does not teach comprising: a third semiconductor chip that configured to store a first digital signal that has been converted from the first signal in the first signal converting unit, store a second digital signal that has been converted from the second signal in the second signal converting unit, store a third digital signal that has been converted from the third signal in the third signal converting unit, store a fourth digital signal that has been converted from the fourth signal in the first signal converting unit, store a fifth digital signal that has been converted from the fifth signal in the second signal converting unit, and store a sixth digital signal that has been converted from the sixth signal in the third signal converting unit, the third semiconductor chip being stacked with the first semiconductor chip.
In reference to Shizukuishi, Shizukuishi teaches storing a first digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a first digital pixel signal.) that has been converted from a first signal in a first signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The first signal converting unit is a signal processing circuit for a first pixel.),
storing a second digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a second digital pixel signal.) that has been converted from a second signal in a second signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The second signal converting unit is a signal processing circuit for a second pixel.),
storing a third digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a third digital pixel signal.) that has been converted from a third signal in a third signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The third signal converting unit is a signal processing circuit for a third pixel.).
storing a fourth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a fourth digital pixel signal.) that has been converted from a fourth signal in a first signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The fourth pixel is a pixel converted by the same signal processing circuit as the first pixel.),
storing a fifth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a fifth digital pixel signal.) that has been converted from a fifth signal in a second signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The fifth pixel is a pixel converted by the same signal processing circuit as the second pixel.), and
storing a sixth digital signal (Shizukuishi, Fig. 1, non-volatile memory area 6, Paragraphs 0038-0038, The memory stores a sixth digital pixel signal.) that has been converted from a sixth signal in a third signal converting unit (Shizukuishi, Fig. 1, signal processing circuit 3, Paragraph 0034, The sixth pixel is a pixel converted by the same signal processing circuit as the third pixel.).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim, Blanquart and Hirota with the memory circuit as seen in Shizukuishi to allow the image sensor to store one or more frames of images (Shizukuishi, Paragraph 0039).
However, the combination of Kim, Blanquart, Hirota and Shizukuishi does not teach a third semiconductor chip being stacked with the first semiconductor chip.
In reference to Kishi, Kishi teaches a first semiconductor chip that includes the plurality of photoelectric converting units (Kishi, Fig. 9, area 1 (first semiconductor substrate), Paragraphs 0058 and 0080);
a second semiconductor chip that includes the plurality of signal converting units (Kishi, Fig. 9, area 2 (second semiconductor substrate), Paragraph 0058 and 0080);
a third semiconductor chip that stores the signals that have been converted into digital signals by the signal converting units (Kishi, Fig. 9, column memory 104, Paragraphs 0056), the third semiconductor chip being stacked with the first semiconductor chip (Kishi, Fig. 9, area 3, Paragraph 0080).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim, Blanquart, Hirota and Shizukuishi with the memory substrate as seen in Kishi to reduce the footprint of the image sensor by stacking the memory substrate.
Claim(s) 42-45 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 6,937,279 B1) in view of Blanquart (US 2012/0307030 A1) in view of Kanzaki et al. (US 2009/0153709 A1).
Regarding claim 42, the combination of Kim and Blanquart teaches the image sensor according to Claim 27 (see claim 27 analysis). However, the combination of Kim and Blanquart does not teach an imaging apparatus comprising the image sensor according to Claim 27.
In reference to Kanzaki et al. (hereafter referred as Kanzaki), Kanzaki teaches an imaging apparatus comprising an image sensor (Kanzaki, Figs. 1-2, Paragraphs 0023 and 0027).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Kim and Blanquart with the teaching of using the image sensor in an imaging apparatus as seen in Kanzaki to allow a user to use the image sensor.
Regarding claim 43, the combination of Kim, Blanquart and Kanzaki teaches the image sensor according to Claim 42 (see claim 42 analysis), comprising an image processing unit that performs an image processing to a first digital signal that has been converted from the first signal in the first signal converting unit (Kanzaki, Fig. 2, CPU 20, Paragraphs 0032-0033).
Regarding claim 44, the combination of Kim, Blanquart and Kanzaki teaches the image sensor according to Claim 42 (see claim 42 analysis), comprising an attaching unit to which an optical system that emits light to the image sensor is attached (Kanzaki, Fig. 1, lens 12, Paragraphs 0004-0005 and 0050).
Regarding claim 45, the combination of Kim, Blanquart and Kanzaki teaches the image sensor according to Claim 42 (see claim 42 analysis), comprising the optical system (Kanzaki, Fig. 2, lens 12, Paragraph 0029).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WESLEY JASON CHIU whose telephone number is (571)270-1312. The examiner can normally be reached Mon-Fri: 8am-4pm.
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/WESLEY J CHIU/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639