Detailed Final Action
Introduction
1. For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions.
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
2. This Office Action addresses U.S. Application No. 17/012,269 (hereinafter also referred to as ‘269 or the instant application), filed September 4, 2020, which is a reissue application of U.S. Patent No. 10,615,173 (hereinafter also referred to as ‘173 or the original patent), issued April 7, 2020 on U.S. Non-Provisional Patent Application No. 16/398,382 (hereinafter also referred to as ‘382 or the parent application), entitled “THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES”, filed April 30, 2019.1 The parent application is a continuation of U.S. Non-Provisional Patent Application No. 15/844,188 (hereinafter also referred to as ‘188 or the grandparent application), also entitled “THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES”, filed December 15, 2017, which claims the benefit of Korean Patent Application No. 10-2017-0044144, filed on April 5, 2017.
3. With regard to litigation involving ‘173, see Litigation Search Report of record. Also based upon the Examiner’s independent review of ‘173 itself and the prosecution history, the Examiner cannot locate any other previous reexaminations, supplemental examinations, or certificates of correction.
4. The ‘173 patent issued with claims 1-20 (hereinafter also referred to as the patent claims). A preliminary amendment filed concurrently with the application on September 4, 2020 was entered. This preliminary filing added claims 21-40 which were subsequently cancelled.
Most recently, pending claims 41-44, 47-48, 51, 53 and 58-59 were amended and claims 45, 57, 60 and 62-63 were cancelled.
5. As of the date of this Office Action, the status of the claims is:
Claims 41-44, 47-51, 53, 55, 58-59 and 61 are pending.
Claims 41-44, 47-51, 53, 55, 58-59 and 61 are examined.
Claims 41-44, 47-51, 53, 55, 58-59 and 61 are objected to and/or rejected as set forth infra.
Notice of Pre-AIA or AIA Status
6. Because the effective filing date of claims of the instant application is after March 16, 2013, see prior paragraph, the AIA First Inventor to File (“AIA -FITF”) provisions apply thereto. See also paragraph 1, supra.
Claim Objections
7. Claims 41-43, 61 are objected to because of the following informalities: On lines 7 and 11, “as approaching its top from its bottom” should be --from a lower end to an upper end--. This also applies to similar language in claim 44, line 10 and claim 59. On line 3 of claim 42, after “decoder,”, --and-- should be inserted. On line 5 of claim 61, after “on”, --respective ones of said-- should be inserted. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
8. Claims 41-44, 47-51, 53, 55, 58 and 61 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 41 now2 sets forth:
A three-dimensional semiconductor memory device comprising:
a cell region comprising: a lower electrode structure including a plurality of lower word lines that are vertically stacked,
a lower semiconductor pillar that penetrates the lower electrode structure and has a width that increases as approaching its top from its bottom,
an upper electrode structure including a plurality of upper word lines that are vertically stacked on the lower electrode structure, and
an upper semiconductor pillar that penetrates the upper electrode structure, has a width that increases as approaching its top from its bottom, and is connected to the lower semiconductor pillar; and
a peripheral circuit region comprising:
a first pass transistor disposed on a substrate and connecting a first one of the plurality of upper word lines to a row decoder,
a second pass transistor disposed on the substrate and connecting a second one of the plurality of upper word lines to the row decoder, and
a third pass transistor disposed on the substrate and connecting a first one of the plurality of lower word lines to the row decoder,
wherein the first pass transistor comprises at least two first sub-transistors connected in common to the first one of the plurality of upper word lines, [wherein the second pass transistor comprises at least two second sub-transistors connected in common to the second one of the plurality of upper word lines,] wherein the third pass transistor comprises at least two third sub-transistors connected in common to the first one of the plurality of lower word lines, and wherein [a gate width of a first sub-transistor, among the at least two first sub-transistors included in the first pass transistor, and a gate width of a second sub-transistor, among the at least two second sub-transistors included in the second pass transistor, are greater than a gate width of each of the at least two third sub-transistors] an effective gate width of the first pass transistor is greater than an effective gate width of the second pass transistor, and an effective gate width of the third pass transistor is greater than the effective gate width of the second pass transistor.
The response beginning on page 10 relies on Fig. 4, 6:45-50 and 8:19-30 for support. Fig. 4 does show transistors PT2 including at least two sub-transistors, i.e. first and third pass transistors, having a greater effective gate width than transistors PT1, i.e. second transistor. However, Figure 4 shows the transistor PT1 does not have sub-transistors which lack of sub-transistors is not claimed. See, e.g., 8:19-24 as well as 7:54-55 and 64-65. Furthermore, the response relying on Fig. 4 asserts “PT2 connected to WL63 (‘a first pass transistor connecting a first one of the plurality of upper word lines to a row decoder’), PT1 connected to WL33 (‘a second pass transistor connecting a second one of the plurality of upper word lines to the row decoder’), and PT2 connected to WL3 [sic] (‘a third pass transistor connecting a first one of the plurality of lower word lines to the row decoder’)” However, such a first pass transistor connected to the uppermost one of the upper word lines (“WL63”), third pass transistor connected to the uppermost one of the lower word lines (“WL3[1]”) and second pass transistor connected to the lowermost one of the upper word lines (“WL33”) is not claimed.
Claim 42-43 and 613 depend from claim 41. 3”
Claim 44 now4 sets forth:
wherein the first pass transistor consists of m (m being a natural number equal to or greater than 2)5 [one or more]first sub-transistors connected to the first one of the plurality of upper word lines, wherein each of the m first sub-transistors has a same gate length and a same gate width,
wherein the second pass transistor consists of n (n being a natural number equal to or greater than 2) second sub-transistors connected to the first one of the plurality of lower word lines, wherein [n is a natural number] each of the n second sub-transistors has a same gate length and a same gate width as those of each of the m [one or more] first sub-transistors, and n is less than m,
(Bold emphasis added.)
The response beginning on page 12 relies on Figs. 8-9 and col. 10, lines 23-26. While Fig. 8 does show a pass transistor PT3 consisting of 3 sub-transistors and a pass transistor PT2 consisting of 2 sub-transistors, as also discussed in paragraph 9 below, it does not describe a first pass transistor consisting of m equal to 2 first sub-transistors and a second pass transistor consisting of n equal to 2 second sub-transistors and wherein n is less than m. Furthermore the response relying on FIG. 8 asserts with regard to the “first pass transistor”, “FIG. 8, PT3 connected to WL63 includes three sub-transistors SPT” and with regard to the second pass transistor “FIG. 8, PT2 connected to WL31 includes two sub-transistors SPT.” However, such a first pass transistor connected to the uppermost one of the upper word lines (“WL63”) and a second pass transistor connected to the uppermost one of the lower word lines (“WL31”) is not claimed.
Claims 47-51, 53, 55, and 58 depend from claim 44.
Continuing, claim 51 also now recites “the third pass transistor consists of x sub-transistors connected to … one of the plurality of upper word lines, wherein x is different than m.” claim 44 describes the first sub-transistors as consisting of m (m being a natural number equal to or greater than 2) connected to an upper word line. 10:10-32 and Figure 8 (which are relied upon for support) describe pass transistors PT3 connected to uppermost word lines and pass transistors PT2 connected to middle word lines. However neither Fig. 8 nor 10:10-32 teach x number of third sub-transistors different from m number of first sub-transistors connected to any of the other upper word lines, e.g., m=2 first sub-transistors connected to an uppermost word line and x > than 2 third sub-transistors connected to any other of the plurality of upper word lines, as encompassed by claim 51.
Similarly, claim 53 now recites “the third pass transistor consists of one or more third sub-transistors connected to … second one of the plurality of lower word lines, a total number of the one or more third sub-transistors is different than n.” Claim 44 describes n (n being a natural number equal to or greater than 2) second sub-transistors connected to one of the plurality of lower word lines. 10:10-32 and Figure 8 (which are relied upon for support) describe pass transistors PT2 connected to uppermost lower word lines and pass transistors PT1 connected to lowermost lower word lines. However, neither Fig. 8 nor 10:10-32 teach “one or more number of third sub-transistors connected to … second one of the plurality of lower word lines” different from n number of second sub-transistors connected to any of the other lower word lines, e.g., n=3 second sub-transistors connected to an lowermost one of the lower word lines and 2 third sub-transistors connected to any other of the plurality of lower word lines, as encompassed by claim 53.
Finally, claim 55 now recites “the third pass transistor consists of one or more third sub-transistors connected to … first lowermost one of the plurality of upper word lines, a total number of the one or more third sub-transistors is different than n.” 10:10-32 and Figure 8 (which are relied upon for support) describe pass transistors PT3 connected to uppermost upper word lines and pass transistors PT2 connected to lower word lines. Claim 44 describes n (n being a natural number equal to or greater than 2) second sub-transistors connected to one of the plurality of lower word lines. Neither Fig. 8 nor 10:10-32 teach “one or more number of third sub-transistors connected to … first lowermost one of the plurality of upper word lines” different from n number of sub-transistors connected to any of the lower word lines, e.g., 2 third sub-transistors connected to an lowermost one of the upper word lines and 3 third sub-transistors connected to any of the plurality of lower word lines, as encompassed by claim 55.
9. Claims 44, 47-51, 53, 55 and 58 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 44, as discussed above now recites:
wherein the first pass transistor consists of m (m being a natural number equal to or greater than 2)6 first sub-transistors connected to the first one of the plurality of upper word lines, wherein each of the m first sub-transistors has a same gate length and a same gate width,
wherein the second pass transistor consists of n (n being a natural number equal to or greater than 2) second sub-transistors connected to the first one of the plurality of lower word lines, wherein each of the n second sub-transistors has a same gate length and a same gate width as those of each of the m first sub-transistors, and n is less than m,
(Emphasis added.)
However, the language “m…equal to…2” and “m…equal to…2” is inconsistent with “n is less than m”.
Claim 51 recites the limitation "the third pass transistor…connected to the first one of the plurality of upper word lines" in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. The first paragraph of claim 51 recites “a second one of the plurality of upper word lines”.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. See MPEP 2111. It is further noted it is improper to import claim limitations from the specification, i.e., a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment. See MPEP §2111.01(11). Therefore, unless Applicant for patent has provided a lexicographic definition for the term, see MPEP §211l.0l(IV), or 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked, Examiners will interpret the limitations of the pending and examined claims using the broadest reasonable interpretation.
When the claimed feature is written as a means-plus-function or a step-plus-function. See 35 U.S.C. §112(6th ¶) and MPEP §2181-2183. As noted in MPEP §2181, a three prong test is used to determine the scope of a means-plus-function or step-plus-function limitation in a claim:
The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claim 59 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0262669 to Kamata et al.7
Claim 59
The three-dimensional semiconductor memory device comprising:
a cell region comprising;
a substrate;
a lower electrode structure including a plurality of lower word lines that are vertically stacked on the substrate;
an upper electrode structure including a plurality of upper word lines that are vertically stacked on the lower electrode structure;
a semiconductor pillar that penetrates the lower electrode structure and the upper electrode structure, and has a width that increases as approaching its top from its bottom; and;
See the entirety of ‘669, e.g., Figs 1-4, elements 10,WL1-WLn, 25a-25c, 26, and [0001]-[0004], [0066], [0076], [0082]-[0086] and [0092]-[0095].
a peripheral circuit region comprising:
a plurality of first pass transistors respectively connected to corresponding upper word lines; and
a plurality of second pass transistors respectively connected to corresponding lower word lines,
[wherein each of the plurality of first pass transistors comprises a plurality of first sub-transistors commonly connected to a corresponding upper word line,
first source regions of the plurality of first sub-transistors, included in each first pass transistor, are commonly connected in common to each other;]
See the entirety of ‘669, e.g., Figs 1-4, 8-9, elements 11-1, 20, WL1-WLn, 50-1-50-n, and [0001]-[0004], [0011], [0066], [0076], [0082]-[0086], [0092]-[0095] and [0102]-[0106].
wherein the semiconductor pillar has a first portion with a maximum width, a second portion with a minimum width, and a third portion between the first portion and the second portion;
a first one of the plurality of upper word lines is adjacent to the first portion of the upper semiconductor pillar and is connected to a first pass transistor among the plurality of first pass transistors,
a second one of the plurality of upper word lines is adjacent to the third portion of the upper semiconductor pillar and is connected to a second pass transistor among the plurality of first pass transistors,
a first one of the plurality of lower word lines is adjacent to the second portion of the semiconductor pillar and is connected to a first pass transistor among the plurality of second pass transistors, and
See the entirety of ‘669, e.g., Figs 1-4, 8-9, elements 11-1, 20, WL1-WLn, 50-1-50-n (e.g. WL1/50-1, WL4/50-4, WLN/50-n), 25a-25c, 26 and [0001]-[0004], [0011], [0066], [0076], [0082]-[0086], [0092]-[0095] and [0102]-[0106].
the first pass transistor connected to the first one of the plurality of upper word lines has a first gate width, the second pass transistor connected to the second one of the plurality of upper word lines has a second gate width less than the first gate width, and the first pass transistor connected to the first one of the plurality of lower word lines has a third gate width less than the second gate width. [a total number of first sub-transistors commonly connected to the first one of the plurality of upper word lines is greater than a total number of first sub-transistors commonly connected to the second one of the plurality of upper word lines and
each of the first sub-transistors commonly connected to the first one of the plurality of upper word lines has a same gate length and a same gate width as those of each of the first sub-transistors commonly connected to the second one of the plurality of upper word lines.]
See the entirety of ‘669, e.g., Figs 8-9 and 19, elements 11-1, 20, WL1-WLn, 50-1-50-n (e.g. WL1/50-1, WL4/50-4, WLN/50-n), and [0001]-[0004], [0011], [0066], [0076], [0082]-[0086][0092]-[0095], [0102]-[0106] and [0167]-[0168].
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
11. Claims 41-42 and 61 are rejected under 35 U.S.C. 103 as being unpatentable over Yip et al (US Patent No. 9,589,978, hereinafter also referred to as ‘978) in view of Yoon et al (US Patent No. 8,559,235, hereinafter also referred to as ‘235), and Vali et al (US Patent Application No. 2016/0026565, hereinafter also referred to as ‘565).8
Claim 41
A three-dimensional semiconductor memory device comprising:
See ‘978 at, e.g., Figures 2A-2E and col. 1, lines 17-19, col. 3, lines 7-20, col. 4, lines 6-10, col. 1, line 60-col. 2, line 7, col. 6, lines 33-35, col. 3, line 64-col. 4, line 5, and col. 7, lines 19-42.
a cell region comprising:
a lower electrode structure including a plurality of lower word lines that are vertically stacked,
a lower semiconductor pillar that penetrates the lower electrode structure and has a width that increases as approaching its top from its bottom,
an upper electrode structure including a plurality of upper word lines that are vertically stacked on the lower electrode structure, and
an upper semiconductor pillar that penetrates the upper electrode structure, has a width that increases as approaching its top from its bottom, and is connected to the lower semiconductor pillar; and
See ‘978 at, e.g., Figure 2B, element 202, and col. 3, line 64-col. 4, line 11, col. 6, lines 54-64 and col. 9, lines 32-65, i.e. an upper stack of word lines 235-1 is vertically stacked on a lower stack of word lines 235-2 and pillars 125 penetrate such stacks. Therefore, while '978 teaches pillars associated with each of the stacks, it does not describe such as having an upper pillar and a lower pillar and widths thereof as claimed. However, see again '235 at Figs. 3-5 and col. 13, lines 19-23 (Note "may" also infers 'may not"), and Figures 32-33 and col. 32, lines 18-48 and col. 33, lines 1-3. Therefore, it would have been obvious to one of ordinary skill in the art to substitute a first upper sub-pillar of increasing width and second lower sub-pillar of increasing width as taught in '235 for the '978 upper and lower portions of each pillar for the predictable result of forming a memory cell string. In so doing, the upper stack of word lines/plates are penetrated by the upper sub-pillars of increasing widths and the lower stack of word lines/plates are penetrated by the lower sub-pillars of increasing widths as claimed.
a peripheral circuit region comprising:
a first pass transistor disposed on a substrate and connecting a first one of the plurality of upper word lines to a row decoder,
a second pass transistor disposed on a substrate and connecting a second one of the plurality of upper word lines to a row decoder, and
a third pass transistor disposed on the substrate and connecting a first one of the plurality lower word lines to the row decoder,
wherein the first pass transistor comprises at least two first sub-transistors connected in common to the first one of the plurality of upper word lines,
[wherein the second pass transistor comprises at least two second sub-transistors connected in common to the second one of the plurality of upper word lines,]
wherein the third pass transistor comprises at least two third sub-transistors connected in common to the first one of the plurality of lower word lines, and
See ‘978 at, e.g., col. 1, lines 17-19, col. 3, lines 7-20, col. 4, lines 6-10, Fig. 2B, elements 204 and 240, col. 6, line 39, col. 10, lines 22-44, col. 13, lines 21-57, col. 14, line 62-col. 15, line 61, claim 7 and col. 9, lines 50-54, e.g. each step/word line can be coupled to one pass transistor or more than one pass transistor, i.e. at least two. See also Figure 2A, and Figure 2E , element 292. Therefore, while ‘978 describes at least a first transistor connected between a global access line/access line driver and one of a plurality of upper word lines, at least a second transistor connected between a global access line/access line driver and one of a plurality of upper word lines and at least a third pass transistor connected between a global access line/access line driver and one of a plurality of lower word lines to the row decoder, it does not explicitly refer to “a row decoder”. See however ‘565 at, e.g., Figure 4 and paragraph 28 which describe individual access line drivers being part of a row decoder coupled via global access lines to planes of a memory array, i.e. of memory cells, in order to select rows of memory cells. Therefore, it would be obvious to one of ordinary skill in the art in view of ‘565 that the structure of ‘978, i.e. global access lines coupling, via the transistors, access/memory cell plates to individual access line drivers, also defines pass transistors connecting the words lines to a row decoder, i.e. the line drivers, in order to achieve the predictable result of row/address selection.
Continuing, see again ‘978 at, e.g., col. 10, lines 22-44, col. 13, lines 21-57, col. 14, line 62-col. 15, line 61, claim 7 and col. 9, lines 50-54, e.g. each step/word line, i.e. one of the upper word lines, one of the lower word lines, e.g. can be coupled to one pass transistor or more than one pass transistor. See also Figure 2A, and Figure 2E, element 292. Note also Fig. 4. Therefore, ‘978 describes first sub-transistors connected between a global access line/access line driver and one of the plurality of upper word lines and thereby, in common to the one of the plurality of upper word lines and third sub-transistors connected between a global access line/access line driver and an one of the plurality of lower word lines and thereby, in common to the one of the plurality of lower word lines. ‘978 thereby also describes first sub-transistors connected between a global access line/access line driver and an one of the upper word lines in parallel to each other and third sub-transistors connected between a global access line/access line driver and an one of the plurality of lower word lines in parallel to each other .
Therefore, the prior art obviously teaches or suggests first sub-transistors are connected in common to the first one of the plurality of upper word lines, and the third sub-transistors are connected in common to the first one of the lower word lines.
wherein [a gate width of a first sub-transistor, among the at least two first sub-transistors included in the first pass transistor, and a gate width of a second sub-transistor, among the at least two second sub-transistors included in the second pass transistor, are greater than a gate width of each of the at least two third sub-transistors] an effective gate width of the first pass transistor is greater than an effective gate width of the second pass transistor, and an effective gate width of the third pass transistor is greater than the effective gate width of the second pass transistor.
As set forth above in the cited portions of ‘978, ‘978 describes explicitly that each of the pass transistors 240 can be, e.g., one or more pass transistors connected to a single step and a single global access line. See also, e.g. Figures 2A-E, the representations of elements 240 of ‘978. Therefore, it is the initial position that ‘978 explicitly teaches this claim feature. Alternatively, to the extent ‘978 is deemed to be silent as to whether the number of transistors connected to each step is the “same”, “different” or both, since ‘978 still explicitly teaches that one or more pass transistors can be connected to each step a POSITA would have found it obvious that such explicit description encompasses a finite number of outcomes-namely the same number of transistors, e.g. c transistors, connected to each word line, or a different number of transistors, e.g. c,d,e,…transistors, connected to respective word lines, or both, e.g. c transistors connected to one or some word lines, d transistors connected to some or one word lines, etc., i.e. the number of each of the first, second and third transistors/sub-transistors is different, i.e. lesser or greater, than the other.
The prior art describes or obviously suggests the number of first and third transistors/sub-transistors having the same width being greater than the number of second pass transistors/sub-transistors having widths the same as that of the first and third transistors/sub-transistors, i.e. an effective gate width of the first pass transistor is greater than an effective gate width of the second pass transistor, and an effective gate width of the third pass transistor is greater than the effective gate width of the second pass transistor.. Again it is noted ‘978 does not require the step/word lines be connected to the same number of transistors.
Claim 42
The three-dimensional semiconductor memory device of claim 41,
wherein the first sub-transistors are connected in parallel to each other between the first [second] one of the upper word lines and the row decoder,
[the at least two second sub-transistors connected in parallel to each other between the second one of the upper word lines and the row decoder, and
the third sub-transistors connected in parallel to each other between the first one of the lower word lines and the row decoder.
See prior discussion of claim 41, e.g. col. 13, lines 21-57 and Figure 2A of ‘978 as well as '978 at, e.g., Figure 2E, element 292 and the paragraph bridging cols. 14-15. Note also Fig. 4. Therefore, '978 describes first sub-transistors connected between a global access line/access line driver and a uppermost one of the upper word lines in parallel to each other and third sub-transistors connected between a global access line/access line driver and a first one of the lower word lines in parallel to each other.
Claim 61
The three-dimensional semiconductor memory device of claim 41, further comprising:
a block select line connected to the first pass transistor, the second pass transistor, and the third pass transistor,
wherein gate electrodes of the at least two first sub-transistors are connected to the block select line, [gate electrodes of the at least two second sub-transistors are connected to the block select line,] and
gate electrodes of the at least two third sub-transistors are connected to the block select line.
See the discussion of claim 41. See also '978 at, e.g., Figs. 2B and 2E, element 299 and col. 14, lines 37-61. Therefore, the prior art obviously teaches or suggests the control gates, i.e. gate electrodes, of all the transistors/sub-transistors, i.e. first pass transistor/the at least two first sub-transistors, the second pass transistor, and the third pass transistor/the at least two third sub-transistors, of a block connected to a block select line.
12. Claims 43-44, 47-51, 53, 55 and 58 are rejected under 35 U.S.C. 103 as being unpatentable over Yip et al (US Patent No. 9,589,978, hereinafter also referred to as ‘978) in view of Yoon et al (US Patent No. 8,559,235, hereinafter also referred to as ‘235), Vali et al (US Patent Application No. 2016/0026565, hereinafter also referred to as ‘565), Kamata et al (US Patent Application No. 2015/0262669, hereinafter also referred to as ‘669), Lee et al (US Patent Application No. 2016/0086967, hereinafter also referred to as ‘967), and Oh et al (US Patent Application No. 2016/0260698, hereinafter also referred to as ‘698).
Claim 44
A three-dimensional semiconductor memory device comprising:
See ‘978 at, e.g., Figures 2A-2E and col. 1, lines 17-19, col. 3, lines 7-20, col. 4, lines 6-10, col. 1, line 60-col. 2, line 7, col. 6, lines 33-35, col. 3, line 64-col. 4, line 5, and col. 7, lines 19-42.
a cell region comprising:
a substrate,
a lower electrode structure including a plurality of lower word lines that are vertically stacked on the substrate,
an upper electrode structure including a plurality of upper word lines that are vertically stacked on the lower electrode structure, and
a semiconductor pillar that penetrates the lower electrode structure and the upper electrode structure, and has a width that increases as approaching its top from its bottom,; and
See ‘978 at, e.g., Figure 2B, element 202, and col. 3, line 64-col. 4, line 11, col. 6, lines 54-64 and col. 9, lines 32-65, i.e. an upper stack of word lines 235-1 is vertically stacked on a lower stack of word lines 235-2 and pillars 125 penetrate such stacks. Therefore, while ‘978 teaches pillars associated with each of the stacks, it does not describe such as having a width as claimed. However, see ‘235 at Figs. 3-5 and col. 13, lines 19-23 (Note “may” also infers ‘may not”). Therefore, it would have been obvious to one of ordinary skill in the art to substitute a tapered pillar as taught in ‘235 for ‘978’s cylindrical pillar for the predictable result of forming a memory cell string. In so doing, the upper and lower stacks of word lines/plates are penetrated by a semiconductor pillar having a width as claimed.
a peripheral circuit region comprising:
a first pass transistor disposed on the substrate and connecting a first one of the plurality of upper word lines to a row decoder, and
a second pass transistor disposed on the substrate and connecting a first one of the plurality lower word lines to the row decoder,
See ‘978 at, e.g., col. 1, lines 17-19, col. 3, lines 7-20, col. 4, lines 6-10, Fig. 2B, elements 204 and 240, col. 6, line 39, col. 10, lines 22-44, col. 13, lines 21-57, col. 14, line 62-col. 15, line 61, claim 7 and col. 9, lines 50-54, e.g. each step/word line can be coupled to one pass transistor or more than one pass transistor. See also Figure 2A, and Figure 2E , element 292. Therefore, while ‘978 describes at least a first transistor connected between a global access line/access line driver and one of a plurality of upper word lines, and at least a second pass transistor connected between a global access line/access line driver and one of a plurality of lower word lines to the row decoder, it does not explicitly refer to “a row decoder”. See however ‘565 at, e.g., Figure 4 and paragraph 28 which describe individual access line drivers being part of a row decoder coupled via global access lines to planes of a memory array, i.e. of memory cells, in order to select rows of memory cells. Therefore, it would be obvious to one of ordinary skill in the art in view of ‘565 that the structure of ‘978, i.e. global access lines coupling, via the transistors, access/memory cell plates to individual access line drivers, also defines pass transistors connecting the words lines to a row decoder, i.e. the line drivers, in order to achieve the predictable result of row/address selection.
wherein the first pass transistor consists of [one or more] m (m being a natural number equal to or greater than 2)9 first sub-transistors connected to the first one of the plurality of upper word lines,…
wherein the second pass transistor consists of n (n being a natural number equal to or greater than 2) second sub-transistors connected to the first one of the plurality of lower word lines, [wherein n is a natural number,]…
and n is less than m [different from a total number of the one or more first sub-transistors included in the first transistor],
In light of the discussion in paragraphs 8-9 above, these claim limitations are interpreted to either recite n and m to be a natural number equal to or greater than 2 or each pass transistor consisting of a plurality of sub-transistors wherein the number n of second sub-transistors being less than the number m of first sub-transistors. As set forth above in the cited portions of ‘978, ‘978 describes explicitly that each of the pass transistors 240 can be, e.g., one or more pass transistors connected to a single step and a single global access line. Therefore, it is the initial position that ‘978 explicitly teaches this claim feature, e.g. the number of each of the first and second sub-transistors is equal to or greater than 2. Alternatively, to the extent ‘978 is deemed to be silent as to whether the number of transistors connected to each step is the “same”, “different” or both, since ‘978 still explicitly teaches that one or more pass transistors can be connected to each step, a POSITA would have found it obvious that such explicit description encompasses a finite number of outcomes-namely the same number of transistors, e.g. c transistors, connected to each word line, e.g. equal to 2, or a different number of transistors, e.g. c,d,e,…transistors, connected to respective word lines, or both, e.g. c transistors connected to one or some word lines, d transistors connected to some or one word lines, etc., i.e. the number of each of the first and second sub-transistors is different, i.e. lesser or greater, than the other, e.g. n is less than m.
…wherein each of the n second sub-transistors has a same gate length and a same gate width… each of the n second sub-transistors has a same gate length and a same gate width as those of each of the one or more first sub-transistors,
See, e.g. Figures 2A-E, the representations of elements 240 of ‘978. Note also the ensuing discussion of this claim.
wherein each of the [one or more] m first sub-transistors has a first gate, a first source region, and a first drain region,
wherein each of the n second sub-transistors has a second gate, a second source region, and a second drain region,
wherein first source regions of the [one or more] m first sub-transistors are connected in common to the first uppermost one of the plurality upper word lines, and
wherein second source regions of the n second sub-transistors are connected in common to the first uppermost one of the plurality of lower word lines.
See, e.g., Figures 2A-2E and col. 1, lines 17-19, col. 3, lines 7-20, col. 4, lines 6-10 of ‘978. Therefore, ‘978 teaches the sub-transistors of the peripheral circuit region of a substrate/“semiconductor” being under a cell region. The representations of the sub-transistors are of the same size and show a single control gate. However, ‘978 does not explicitly describe the specifics of the layout of the transistors in the peripheral region, e.g. a first gate, a first source region and a first drain region . Therefore, see ‘669 at, e.g., Figs. 1-2, 8, 18 and paragraphs 56, 66 and 96-104 and 166, ‘967 at, e.g., paragraphs 56-57 and 62-64 and Figs. 4 and 6 and ‘698 at, e.g., Figs. 1-2 and paragraphs 36-38 and 41-42 which also teach a peripheral region under a cell region in a semiconductor structure having transistors. The transistors include a plurality of active regions, gate electrodes and source/drain regions formed in the peripheral circuit region. The prior art also describes the source/drain regions of the active regions of the transistors being connected to word lines. ‘669 also shows in Figure 8 that such layout has a representation similar to that of the sub-transistors of ‘978. Therefore, if not already, to also form transistors of the stacked memory semiconductor of ‘978 with an active region of the same size and length, a first gate, and source/drain regions would be obvious to one of ordinary skill in the art in view ‘669, ‘967 and ‘698 for the predictable result of providing pass transistors in a peripheral circuit region of a stacked memory semiconductor which is under the cell region as similarly taught/represented by ‘978. In so doing, the prior art combination teaches or suggests, each of the first and second sub-transistors has an similarly sized active region, a first gate, and source/drain regions and thereby, the substrate of the peripheral circuit region including a plurality of active regions having the same width and the same length, and each of the first and second sub-transistors provided on an active region. Accordingly, the prior art describes each of the transistors of the periphery circuit region of the substrate/”semiconductor” including a gate and source/drain regions, one of such source/drain regions connected to a word line.
Continuing, see again ‘978 at, e.g., col. 10, lines 22-44, col. 13, lines 21-57, col. 14, line 62-col. 15, line 61, claim 7 and col. 9, lines 50-54, e.g. each step/word line, i.e. first one of the upper word lines, first one of the lower word lines, e.g. can be coupled to one pass transistor or more than one pass transistor. See also Figure 2A, and Figure 2E, element 292. Note also Fig. 4. Therefore, ‘978 describes first sub-transistors connected between a global access line/access line driver and one of the plurality of upper word lines and thereby, in common to the uppermost one of the plurality of upper word lines and second sub-transistors connected between a global access line/access line driver and one of the plurality of lower word lines and thereby, in common to the uppermost one of the plurality of lower word lines. ‘978 thereby also describes first sub-transistors connected between a global access line/access line driver and an uppermost one of the upper word lines in parallel to each other and second sub-transistors connected between a global access line/access line driver and an uppermost one of the plurality of lower word lines in parallel to each other.
Therefore, the prior art also obviously teaches or suggests each of the sub-transistors having gate, a source region, and a drain region and source regions of the first sub-transistors are connected in common to the first one of the plurality of upper word lines, and the second source regions of the second sub-transistors are connected in common to the first one of the lower word lines.
Claim 47
The three-dimensional semiconductor memory device of claim 44,
wherein first drain regions of the [one or more] m first sub-transistors are connected in common to a first driving signal line connected to the row decoder, and
wherein second drain regions of the n second sub-transistors are connected in common to a second driving signal line connected to the row decoder.
See the prior discussion of claim 44. See ‘978 at, e.g., col. 10, lines 22-44, col. 13, lines 21-57, and claims 7-8. Therefore, ‘978 describes first sub-transistors connected between a global access line/access line driver and a one of the upper word lines and thereby, in common to the global access line/access line driver connected to the row decoder and second sub-transistors connected between a global access line/access line driver and a first one of the lower word lines and thereby, in common to the global access line/access line driver connected to the row decoder. Furthermore, the prior art obviously teaches or suggests each of the sub-transistors having gate and source/drain regions, and source/drain regions of the first sub-transistors are connected in common to the first one of the upper word lines, and the second source/drain regions of the second sub-transistors are connected in common to the first one of the lower word lines.
Claim 48
The three-dimensional semiconductor memory device of claim 44,
wherein first gates of the [one or more] m first sub-transistors and second gates of the n second sub-transistors are connected in common to a selection line.
See discussion of 44 above, e.g., ‘978, Fig. 2E, element 99, ‘698 at, e.g., Fig. 1, elements 210 and 270, ‘669, element Fig. 8, TG. Therefore, the prior art teaches or suggests gates of the sub-transistors are connected in common to a selection line.
Claim 49
The three-dimensional semiconductor memory device of claim 44,
wherein the substrate of the peripheral circuit region includes a plurality of active regions,
wherein the first gate, the first source region, and the first drain region of one first transistor are provided on a first one of the plurality of active regions, and
wherein the second gate, the second source region, and the second drain region of one second sub-transistor are provided on a second one of the plurality of active regions.
See discussion of claim 44 above.
Claim 50
The three-dimensional semiconductor memory device of claim 49,
wherein the plurality of active regions are spaced apart from each other in a first direction, and
wherein the first gate of the one first sub-transistor crosses the first one of the plurality of active regions in the first direction.
See discussion of claim 44 above, e.g., ‘978, Figs. 2A-2B, elements 240 and gates thereof, ‘698, Fig. 1, 210, ‘669, Figs. 8 and 19-20, and ‘967, Fig. 6.
Claim 51
The three-dimensional semiconductor memory device of claim 44, further comprising a third pass transistor connecting a [first] second one of the plurality of upper word lines to the row decoder,
wherein the third pass transistor consists of x third sub-transistors connected to the first one of the plurality of upper word lines, wherein x is different than m [the number of the one or more first sub-transistors].
In light of the discussion in paragraph 9 above, these claim limitations are interpreted to include the third pass transistor consisting of x third sub-transistors connected to another one of the plurality of upper word lines, wherein x is different than m. See discussion of first and second pass transistors/sub-transistors of claim 44 above. See also again, e.g., col. 10, lines 22-44, col. 13, lines 21-57, col. 14, line 62-col. 15, line 61, claim 7, and col. 9, lines 50-54, e.g. each step/word line can be coupled to one pass transistor or more than one pass transistor, e.g. “x third sub-transistors” with respect to another of the upper word lines. As discussed above, to the extent ‘978 is deemed to be silent as to whether the number of transistors connected to each step is the “same”, “different” or both since ‘978 still explicitly teaches that one or more pass transistors can be connected to each step, a POSITA would have found it obvious that such explicit description encompasses a finite number of outcomes-namely the same number of transistors, e.g. c transistors, connected to each word line, or a different number of transistors, e.g. c,d,e,…transistors, connected to respective word lines, or both, e.g. c transistors connected to one or some word lines, d transistors connected to some or one word lines, etc., i.e. the number of each of the first and third sub-transistors is different, i.e. lesser or greater, than the other, e.g. x is different than m.
The prior art describes or obviously suggests, i.e. a step/word line has x sub-transistors, e.g. two, while another step/upper word line, has “equal to or greater than two first sub-transistors”, e.g. greater than two. Again it is noted ‘978 does not require the step/word lines be connected to the same number of transistors.
Claim 53
The three-dimensional semiconductor memory device of claim 44, further comprising:
a third pass transistor connecting a [first] second one of the plurality of lower word lines to the row decoder,
wherein the third pass transistor consists of [y] one or more third sub-transistors connected to the [first] second one of the plurality of lower word lines, a total number of the one or more third sub-transistors being different from n [wherein n and y are different natural numbers from each other].
See discussion of first and second pass transistors of claim 44 above. See also again, e.g., col. 10, lines 22-44, col. 13, lines 21-57, col. 14, line 62-col. 15, line 61, claim 7, and col. 9, lines 50-54, e.g. each step/word line can be coupled to one pass transistor or more than one pass transistor, e.g. “one or more third sub-transistors” with respect to “a second one” of the lower word lines. As discussed above, to the extent ‘978 is deemed to be silent as to whether the number of transistors connected to each step is the “same”, “different” or both, since ‘978 still explicitly teaches that one or more pass transistors can be connected to each step, a POSITA would have found it obvious that such explicit description encompasses a finite number of outcomes-namely the same number of transistors, e.g. c transistors, connected to each word line, or a different number of transistors, e.g. c,d,e,…transistors, connected to respective word lines, or both, e.g. c transistors connected to one or some word lines, d transistors connected to some or one word lines, etc., i.e. the number of each of the second and third sub-transistors is different, i.e. lesser or greater, than the other, e.g. number of third sub-transistors is different than m.
The prior art describes or obviously suggests, i.e. a step/word line has one or more sub-transistors, e.g. one, while another step/lower word line, has “n second sub-transistors”, e.g. two. Again it is noted ‘978 does not require the step/word lines be connected to the same number of transistors.
Claim 55
The three-dimensional semiconductor memory device of claim 44, further comprising a third pass transistor connecting a first lowermost one of the plurality of upper word lines to the row decoder,
wherein the third pass transistor consists of [z] one or more third sub-transistors connected to the first lowermost one of the plurality of upper word lines, wherein a total number of the one or more third sub-transistors being different from n [z and n are different natural numbers from each other].
See discussion of first and second pass transistors of claim 44 above. See also again, e.g., col. 10, lines 22-44, col. 13, lines 21-57, col. 14, line 62-col. 15, line 61, claim 7, and col. 9, lines 50-54, e.g. each step/word line can be coupled to one pass transistor or more than one pass transistor, e.g. “one or more third sub-transistors” with respect to “the first lowermost one of the plurality of upper word lines”. As discussed above, to the extent ‘978 is deemed to be silent as to whether the number of transistors connected to each step is the “same”, “different” or both, since ‘978 still explicitly teaches that one or more pass transistors can be connected to each step, a POSITA would have found it obvious that such explicit description encompasses a finite number of outcomes-namely the same number of transistors, e.g. c transistors, connected to each word line, or a different number of transistors, e.g. c,d,e,…transistors, connected to respective word lines, or both, e.g. c transistors connected to one or some word lines, d transistors connected to some or one word lines, etc., i.e. the number of each of the third and second sub-transistors is different, i.e. lesser or greater, than the other, e.g. number of third sub-transistors is different than n.
The prior art describes or obviously suggests, i.e. a step/word line has x sub-transistors, e.g. two, while another step/upper word line, has “equal to or greater than two first sub-transistors”, e.g. greater than two. Again it is noted ‘978 does not require the step/word lines be connected to the same number of transistors.
Therefore, the prior art describes or obviously suggests, i.e. a lowermost upper step/word line has one or more sub-transistors, e.g. three, while another upper step/word line , has “n second sub-transistors”, e.g. two. It is noted ‘978 does not require the step/word lines be connected to the same number of transistors.
Claim 58
The three-dimensional semiconductor memory device of claim 44,
wherein the [one or more] m first sub-transistors are connected in parallel to each other between the first one of the plurality of upper word lines and the row decoder, and
wherein the second sub-transistors are connected in parallel to each other between the first one of the plurality of lower word lines and the row decoder.
See discussion of claim 44 above.
Claim 43
The three-dimensional semiconductor memory device of claim 41,
wherein the substrate of the peripheral circuit region includes a plurality of active regions, and
wherein the at least two first sub-transistors and the at least two third sub-transistors are provided on active regions.
See the discussion of claims 44 and 49-50 above.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
13. Claims 44 and 51 are provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claims 21 and 30-31 of co-pending Application No. 17/878,352 in view of Yoon et al (US Patent No. 8,559,235, hereinafter also referred to as ‘235), Yip et al (US Patent No. 9,589,978, hereinafter also referred to as ‘978) and Vali et al (US Patent Application No. 2016/0026565, hereinafter also referred to as ‘565) alone.
This is a provisional non-statutory double patenting rejection.
17/868,352
‘269
Claim 21:
A three-dimensional semiconductor memory device comprising:
a cell region comprising:
a substrate,
a lower stack including a plurality of lower word lines that are vertically stacked on the substrate; and
an upper stack including a plurality of upper word lines that are vertically stacked on the lower stack; and
Claim 30:
…device of claim 21, further comprising: a lower semiconductor pillar that penetrates the lower stack; and an upper semiconductor pillar that penetrates the upper stack and is connected to the lower semiconductor pillar.
Claim 31:
….device of claim 30,
wherein each of the lower semiconductor pillar and the upper semiconductor pillar has a width that increases from bottom to top.
(see below)
a peripheral circuit region comprising:
a plurality of first pass transistors disposed on the substrate, each of the plurality of first pass transistors being connected to a corresponding lower word line of the plurality of lower word lines, and
a plurality of second pass transistors disposed on the substrate, each of the plurality of second pass transistors being connected to a corresponding upper word line of the plurality of upper word lines,
Claim 44:
A three-dimensional semiconductor memory device comprising:
a cell region comprising:
a substrate,
a lower electrode structure including a plurality of lower word lines that are vertically stacked on the substrate,
an upper electrode structure including a plurality of upper word lines that are vertically stacked on the lower electrode structure, and
a semiconductor pillar that penetrates the lower electrode structure and the upper electrode structure, and has a width that increases as approaching its top from its bottom
a peripheral circuit region comprising
a second pass transistor disposed on the substrate and connecting a first one of the plurality of lower word lines…
a first pass transistor disposed on the substrate and connecting a first one of the plurality of upper word lines …and
the n sub-transistors being connected in parallel to each other between a first row decoder and a first one of the plurality of upper word lines,
the m sub-transistors being connected in parallel to each other between a first row decoder and a second one of the plurality of upper word lines,
…to the row decoder, …
wherein at least one of the plurality of first pass transistor comprises at least two first sub-transistors
wherein a first one of the plurality of second pass transistors comprises n sub-transistors of at least two second sub- transistors,
wherein a second one of the plurality of second pass transistors comprises m sub-transistors of at least two second sub- transistors
wherein n and m are different natural numbers,
wherein the second pass transistor consists of n (n being a natural number equal to or greater than 2) second sub-transistors connected to the first one of the plurality of lower word lines,..
wherein the first pass transistor consists of m (m being a natural number equal to or greater than 2) first sub-transistors connected to the first one of the plurality of upper word lines,
Claim 51:
…device of claim 44, further comprising a third pass transistor connecting a second one of the plurality of upper word lines to the row decoder, wherein the third pass transistor consists of x third sub-transistors connected to the first [sic] one of the plurality of upper word lines,
wherein x is different than m.
See below.
and n is less than m
wherein each of the at least two first sub-transistors has a first gate, a first source region, and a first drain region,
wherein each of the at least two second sub-transistors has a second gate, a second source region, and a second drain region,
wherein each of the n second sub-transistors has a second gate, a second source region, and a second drain region
wherein each of the m first sub-transistors has a first gate, a first source region and a first drain region,
wherein the first source regions of the at least two first sub-transistors are connected in common to a corresponding one of plurality of the lower word lines and
wherein the second source regions of the at least two second sub-transistors are connected in common to a corresponding one of plurality of the upper word lines,
wherein second source regions of the n second sub-transistors are connected in common to the first one of the plurality lower word lines.
wherein first source regions of the m first sub-transistors are connected in common to the first one of the plurality of upper word lines,
wherein the at least two first sub-transistors have a same gate width and a same gate
wherein the at least two second sub-transistors have the same gate width and the same gate length.
each of the n second sub-transistors has a same gate length and a same gate width as those of each of the m first sub-transistors,
wherein each of the m first sub-transistors have a same gate length and a same gate width.
Therefore, while claim 21 teaches upper and lower sub-pillars associated with each of the stacks, it does not explicitly describe a pillar as claimed in claim 44. However, see again ‘235 at Figs. 3-5 and col. 13, lines 19-23 (note “may” also infers ‘may not”), and Figures 32-33 and col. 32, lines 18-48 and col. 33, lines 1-3. Therefore, it would have been obvious to one of ordinary skill in the art to substitute a single tapered semiconductor pillar as taught by ‘235 for the first upper sub-pillar and second lower sub-pillar as taught in claim 21 for the predictable result of forming a memory cell string.
To the extent claim 21 does not explicitly claim each of a plurality of pass transistors connected to corresponding upper word lines also comprising similar structure, i.e. a gate, a source region, and a first region, a drain regions and the source regions connected in common to a corresponding one of the upper word lines, see the cited portions of ‘978 and ‘565 discussed above with regard to claims 44-45, 47-51, 53, 55, 57-60 and 62. These references teach similar pass transistors connected in parallel to each other between a global access line/access line driver and respective stacked word lines/planes of a memory array and individual access line drivers being part of a row decoder coupled via global access lines to planes of a memory array, i.e. of memory cells, in order to select rows of memory cells. Therefore, it would be obvious to one of ordinary skill in the art in view of ‘978 and ‘565 to similarly structure/connect all word lines of the cell region in order to achieve the predictable result of row/address selection.
Claim 21 teaches a plurality of transistors connected to corresponding upper word lines and corresponding lower word lines. To the extent claim 21 does not teach the number of the sub-transistors connected to one of the upper word lines is greater than the number of sub-transistors connected a one of the lower word lines, see again, e.g., col. 10, lines 22-44, col. 13, lines 21-57, col. 14, line 62-col. 15, line 61, claim 7, and col. 9, lines 50-54 of ‘978, e.g. each step/word line of the stack can be coupled to one pass transistor or more than one pass transistor. Therefore, the prior art describes or obviously suggests the number of transistors connected to a word line is interchangeable, i.e. any step/word line has n sub-transistors, i.e. one or more than one, e.g. two, while any other step/word line has m sub-transistors, i.e. one or more than one, e.g. more than two. It is noted ‘978 does not require the step/word lines be connected to the same number of transistors. Accordingly, it is taught or obviously suggests one of the upper word lines can have more transistors connected thereto than are connected to any lower one of the upper word lines.10
To the extent claim 21 includes specifics regarding the a second one of the plurality of second pass transistors and claim 44 does not, it is well settled that omission of an element and its function in a combination is an obvious expedient if the remaining elements perform the same functions as before. In re Karlson, 136 USPQ 184.
Response to Arguments
15. The remarks on pages 9-23 filed February 13, 2026 have been considered in their entirety.
The remarks with regard to status and support on pages 12-18, the substance of interview on pages 18-19, the objections to the drawings on page 19, the 112 rejections on page 19 and the double patenting rejection on page 22 have been considered. See the discussion in paragraphs 8-9 and 13 with regard to currently pending issues.
The remarks with regard to the prior art rejections on pages 19-22 have been considered.
With regard to remarks with respect to independent claim 44, see the discussion in paragraphs 8-9 with regard to the additional limitations of claim 44 as well as the prior art rejection in paragraph 11. Specifically, referring to the portion of the last Office Action cited on page 20 of the response, the specific configuration of a varying number and size of the sub-transistors depending on the level or height of the corresponding word line/width of the corresponding portion of the electrode structure connected thereto critical to the loading is not claimed in claim 44.
With regard to claim 59, attention is invited to paragraph 10 above. Accordingly, the remarks are considered not persuasive.
Conclusion
Finality
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Amendments
Applicant is notified that any subsequent amendment to the specification and/or claims must comply with 37 CFR 1.173(b). In addition, for reissue applications filed before September 16, 2012, when any substantive amendment is filed in the reissue application, which amendment otherwise places the reissue application in condition for allowance, a supplemental oath/declaration will be required. See MPEP § 1414.01.
Prior or Concurrent Proceedings
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceed-ing in which Patent No. 10,615,173 is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely appraise the Office of any information which is mate-rial to patentability of the claims under consideration in this reissue appli-cation.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Inquiries:
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Karin M Reichle whose telephone number is (571)272-4936. The examiner can normally be reached on 6:00-6:00 M-Th.
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/Karin Reichle/Primary Examiner, Art Unit 3992
Conferees:
/Cameron Saadat/Primary Examiner, Art Unit 3992
/ALEXANDER J KOSOWSKI/Supervisory Patent Examiner, Art Unit 3992
1 The term of the patent was extended or adjusted by 0 days.
2 The language added is shown underlined and the language that was deleted is shown in bracketing.
3 Claim 61 also depends from claim 41. The response at page 16 relies upon “Fig 11, line 66-col. 9, line 5 [sic]” for support. Fig. 11, i.e. element BS, appears to show such a claimed block select line. However, see also “BS” in Figs. 4 and 7.
4 See footnote 2.
5 The terminology "consists of..equal to or greater" is equivalent to " …comprising equal to or greater" since "or greater" is open- ended.
6 The terminology "consists of..equal to or greater" is equivalent to " …comprising equal to or greater" since "or greater" is open- ended.
7 2/13/26 amendments shown by underlining and bracketing.
8 2/13/2026 amendments shown by underlining and bracketing.
9 The terminology "consists of..equal to or greater" is equivalent to " …comprising equal to or greater" since "or greater" is open- ended.
10 Note also ‘699, e.g., Figs. 26-27.