Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Based on the Applicant’s Interview on 09/12/25 regarding the rejection/objection of claims 5 and 14 and the amendment filed on 02/26/25 Applicant's request for reconsideration of the finality of the rejection of the last Office action is persuasive and, therefore, the finality of that action is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 10-13, and 21,22, 24-26, and 28, are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al., (US 2005/0251609) previously sited and in further view of Chou et al., (US 10,101,764) further in view of Jreji et al., previously sited in IDS by Applicant.
It has been noted that, a claimed invention is unpatentable if the differences between it and the prior art are "such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art." 35 U.S.C. § 103(a) (2000); KSRInt'lr. Teleflex Inc., 127 S.Ct. 1727, 1734 (2007); Graham v.John Deere Co., 383 U.S. 1, 13-14 (1966).
In Graham, the Court held that that the obviousness analysis is bottomed on several basic factual inquiries: "[(1)] the scope and content of the prior art are to be determined; [(2)] differences between the prior art and the claims at issue are to be ascertained; and [(3)] the level of ordinary skill in the pertinent art resolved." 383 U.S. at 17. See also KSR, 127 S.Ct. at 1734. "The combination of familiar elements according to known methods is likely to be obvious when it does no more; than yield predictable results." KSR, at 1739.
"When a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or in a different one. If a person of ordinary skill in the art can implement a predictable variation, § 103 likely bars its patentability." Id. at 1740.
"For the same reason, if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill." Id.
"Under the correct analysis, any need or problem known in the field of endeavor at the time of invention and addressed by the patent can provide a reason for combining the elements in the manner claimed." Id. 11742.
As per claim 1 and 21,22, 24-26, and 28, Chou’609 a first device (multi-mode device system 600, through an ExpressCard plug is a type of storage device configured to operate in a first mode and second mode), comprising: an interface to directly (Figs. 6a-10) connect to a second device (Host system, 630, Fig. 6a/6b) via a connector (ExpressCard receptable, 690); and a mode component (Fig. 14, [0070-0071]) to receive from the second device a signal (Chou teaches wherein the storage device is configured to operate in a mode that is based on a status of a signal at a pin received from the host device, 630), the second device configured to send the signal (host system, 630 may send an enable PCI Express Mode command to ascertain presence of the PCI Express mode, [0077], Fig. 14. Further, this action occurs after determining the presence of a first mode (USB) in step 1430 that is for host plug functionality – particularly with PCI – a PCI RST# signal can be asserted or deasserted, [0065]), wherein the first device is configured to change from a first mode of operation to a second mode of operation based at least in part on the signal ([0047, 0071]).
Chou’609 is silent in respect to the first mode of operation associated with a first speed of operation and the second mode of operation associated with a second speed of operation, the first speed of operation being faster than the second speed of operation.
Chou’764 teaches a mode selection device for supporting SRIS (Separate Reference Independent Spread) or a separate reference clock with independent SSC (Spread Spectrum Clocking). (col. 3, lines 4-11) The host (second device) is connected to a (first) device (either a SSD, HDD, or any other type of peripheral storage device, col. 2, lines 65-67) via a connector (Fig. 2, 210) and is configured to receive a first reference clock signal (local clock signal, 228 for a first GPIO, 214 that indicates whether the host supports SRIS mode) or a second reference clock signal (from a second GPIO, 216 is used to further indicate whether the host supports SSC mode) from the host. A mode selection circuit (via a signal from the host) is supplied through the connector that triggers the device to transmit and enter into either the SRIS clock signal mode or SSC clock signal mode. (col. 2, lines 54-col. 5, lines 1-14, col. 6, lines 45-col. 7, lines 1-3)
In terms of data transfer rate, it is well known in the art before the effective filling date that SRIS (Separate Reference Independent Spread) clocking in PCIe systems is generally considered to be slightly better than SSC (Spread Spectrum Clocking) in scenarios where higher link speeds, clock signal quality, and tighter clock tolerances are required. (Chou’764 -col. 1, lines 39-62) Therein, official notice is taken that if the primary concern is improving clock signal quality and thereby maximizing data transfer rates, SRIS may offer a slight advantage.
It would have been obvious to one of ordinary skill before the effective filing date to modify the system of Chou’609 to further adapt; any of the other types of connection modes that include different transfer rates (speeds) of Chou’764 for the desirable purpose of providing latest standard available at the time of the invention and to allow the system to take advantage of the many benefits provided by the “ExpressCard interface” of Chou’609 such as higher transfer speeds thereby making the system more versatile and marketable by allowing for self-customizing systems.
However, Chou ‘764 nor Chou’609 an interface to directly connect to a second device via a connector of the first device; and a mode component to receive from the second device a signal.
Nonetheless, Jreji discloses circuitry via the configured to (“CPU 101 is coupled to service processor 102”, [0021], see Fig. 1) select a first mode of operation {“ monitor the state [MODE] of an IHS”, [0019]} based at least in part on a first signal from a component {“ solid state hybrid drives (SSHD) combine the features of SSDs and HDDs”, [0018]}, the first signal received via the connector of the first device (signals via connector as claimed “via several interface and to an array of PCIe SSDs 105”, see Fig. 1, [0021]};a second mode of operation based {“determine the source of NVMe power management”, see Fig. 2 [0027]} at least in part on a second signal from the component {“ polling and/or receiving events about PCIe SSD 105 usage, see Fig. 2 [0028] }, the second signal received via the connector {“ metrics data received from other sources within an IHS”, see Fig. 2 [0028]};
configure the device to use the first mode of operation {‘ any change from PCIe/CPU/Memory usage data or statistics”, [0029]} based at least in part on selection of the first mode of operation by the circuit {“whether there has been any change from an application profile monitoring from the ISM, or whether any adjustments are needed”, [0029]};configure the device to use the second mode of operation {a mathematical calculation may be performed to assign weights to the various performance and metrics data received by service processor 102”, block 206 [0030] see Fig. 2} based mode based at least in part on selection of the second mode of operation by the circuit {‘“the result may be mapped to a power control value [in the respective first or second mode] or limit either directly or via a look-up table”, [0028]}.
Both Chous’ and Jreji are analogous because they are from the same field of endeavor, managing peripheral devices. At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Chous’ and Jreji before him or her, to modify incorporating Jreji’s “managing power to NVMe devices 105” (see Fig. 2, [0028]).
The suggestion/motivation for doing so would have been to incorporate developed systems and methods for smartly managing the power provided to PCIe SSDs for achieving the bigger goal of optimizing an IHS' power consumption by dynamically regulating power to these devices depending upon input/output (1/0) workload (Jreji [0004]).
As per claim 10, the claim is directed to a method of receiving a signal at a first device from a second device over an interface directly wherein the second device sends the signal or configure a change mode of a first device that corresponds to the computer-implement system recited in claim 1, respectively see the rejection of Chou’609 and Chou’764 and Jer in regards to claim 1.
As per claim 2 and 11, Chou’764 discloses wherein the first device includes at least one Solid State Drive (SSD). (Chou’764, either a SSD, HDD, or any other type of peripheral storage device, col. 2, lines 65-67)
As per claim 3 and 12, Chou’609 and Chou’764 discloses wherein the first device according to claim 2, wherein the mode component includes a controller device to communicate with the second device using the connector. (Chou’609, the multi-personality device system 600, through an ExpressCard plug, is capable of PCie and USB (Fig. 6a) The host system may send an enable PCI Express Mode command to ascertain presence of the PCl Express mode ( [0077]; Fig. 14, Chou’764 col. 2, lines 54-col. 5, lines 1-14, col. 6, lines 45-col. 7, lines 1-3)
As per claim 4 and 13, Chou’609 and Chou’764 discloses the first device according to claim 1, wherein the connector includes at least one pin to receive the signal from the second device. (Chou’609 -host system, 630 may send an enable PCI Express Mode command to ascertain presence of the PCI Express mode, [0077], Fig. 14. Further, this action occurs after determining the presence of a first mode (USB) in step 1430 that is for host plug functionality – particularly with PCI – a PCI RST# signal can be asserted or deasserted, [0065]) Chou’764 - a first GPIO, 214 or second GPIO, 216)
As per claim 5 and 14, Chou’609 and Chou’764 discloses the first device according to claim 1, wherein the connector includes at least one General Purpose Input/Output (GPIO) pin to receive the signal from the second device, the at least one GPIO pin latched after receiving the signal from the second device. (Chou’764 - a first GPIO, 214 or second GPIO, 216)
Claims 23 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al., (US 2005/0251609) previously sited and in further view of Chou et al., (US 10,101,764) and Kotzur, previously sited.
As to claim 23 and 27, Kotzur discloses wherein the multi-protocol connector comprises U.2 connector (col. 2, lines 45-48, SFF-8639 standard is a U.2 specification).
Kotzur discloses network interface interconnect system having a first device (Fig. 6C, controller 600), with a network interface having a first network interface (Fig. 6C, crossbar 628), wherein the first device is to receive an interconnect signal from a second device (Fig. 6C, medium 602), and finally the second device comprises a second network interface (Fig. 6C, medium 602 side of SAS/PCIe connector 300, col. 8, lines 4-30).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify to implement Kotzur’s teaching having a mode changing signal sent from a connected second device to a connected first device because doing so would offer high performance and expand the flexibility of Chou and Chou. (Kotzur, col. 7, lines 47-col.8, lines 1-30)
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMARA R PEYTON whose telephone number is (571)272-4157. The examiner can normally be reached on 9am-5pm, EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http: / / www .uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax/phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAMMARA R PEYTON/
Primary Examiner, Art Unit 2184
October 24, 2025