DETAILED ACTION
1. This office action is in response to the Application No. 17039559 filed on 03/26/2026. Claims 1, 3-16 and 21-25 are presented for examination and are currently pending. Applicant’s arguments have been carefully and respectfully considered.
Response to Arguments
2. The claim amendments of 03/26/2026 has not overcome the 102 rejection of the previous rejection. However, the rejection has been remapped to account for the newly added limitation “a system interconnect device”.
The claim amendments has not overcome the 112 rejection in the previous office action. As a result, the 112 rejection in maintained.
However, a new 112(b) rejection has been issued.
On page 10 of the remarks, the Applicant argued that “Figure 9 and associated paragraphs [0069-70 and 0087] clearly disclose that the neural inference engine 901 (i.e. neural network processor system) comprises the activation memory(a- mem), instruction memory (i-mem), and at least one control register. Figure 9 also discloses a system interconnect 902 (i.e. interface) and host 903 that are separate from the neural inference engine 901. Furthermore, paragraphs [0068 and 0087] disclose that the system interconnect 902 (i.e. interface) has a memory map comprising regions corresponding to each of the activation memory, instruction memory, and at least one control register. At least the above cited paragraphs of the instant specification provide clear support for the claim language "a system interconnect comprising: a memory map comprising at least one region corresponding to the activation memory, at least one region corresponding to the instruction memory, and at least one region corresponding to the at least one control register" of claims 1 and 21, such that one skilled in the art at the time of the invention would reasonably conclude that the inventor had possession of the claimed invention. In view of at least the foregoing, it is readily apparent that independent claims 1 and 21 (and associated dependent claims 3-16 and 22-25) comply with the requirements of 35 U.S.C. § 112(a) and 35 U.S.C. § 112 (pre-ATA) first paragraph. Accordingly, withdrawal of this rejection is respectfully requested”.
The above argument is not persuasive because paragraphs [0068] of the instant specification only states that inference engine 901 is connected to system interconnect 902 and host 903 is connected to system interconnect 902. In paragraph [0087] of the instant specification, there is no mention of “system interconnect device” in the paragraph. As a result, the instant specification do not provide support for “a system interconnect device comprising: a memory map comprising at least one region corresponding to the activation memory, at least one region corresponding to the instruction memory, and at least one region corresponding to the at least one control register” and the 112(a) rejection is maintained.
On page15 of the remarks, the Applicant argued that “As noted in the rejection, elements 314 and 316 which the Office Action attempts to equate to the memory map of the subject claim are part of the hardware data processor 306 of Kaplan, and not part of the interconnect 310 which provides the interface between the host 302 and the hardware data processor 306 of Kaplan”.
Also, on page 15, the Applicant argued that “Therefore, Kaplan fails to disclose "a system interconnect comprising: a memory map comprising at least one region corresponding to the activation memory, at least one region corresponding to the instruction memory, and at least one region corresponding to the at least one control register, a communication bus, and at least one interface operatively connecting the neural network processor chip to the communication bus, and connecting the host processor chip to the communication bus, wherein the at least one interface exposes the memory map to the neural network processor chip and the host processor chip for communication therebetween, wherein the communication comprises: receiving, via the at least one region of the memory map corresponding to the activation memory, input data at the activation memory of the neural network processor chip from the host processor chip, receiving, via the at least one region of the memory map corresponding to the instruction memory, a neural network description at the instruction memory of the neural network processor chip, and providing, from the neural network processor chip at the activation memory, output data to the host processor chip via the at least one region of the memory map corresponding to the activation memory" as recited in claim 1”.
The arguments above are not persuasive because as shown below in Fig. 3A of Kaplan, the system interconnect device comprises the memory map (Hardware data processor 306 which includes memory 314 and memory 316)
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However, the argument that Kaplan does not teach “a system interconnect device comprising: a memory map comprising ... activation memory ... instruction memory ... control register, ... output data to the host processor chip via the at least one region of the memory map corresponding to the activation memory” is not persuasive.
Kaplan teaches a system interconnect device comprising (Fig. 3A above):, a memory map (Hardware data processor 306 also includes a local memory, which includes a local on-chip memory 314 (on the same chip as computing engine 312) and a local off-chip memory 316 (col. 16, lines 7-10).The Examiner notes memory 314 and memory 316 is the memory map) comprising at least one region (static random access memory (SRAM) (col. 16, line 12)) corresponding to the activation memory (Local on-chip memory 314 may include different types of on-chip memory such as, for example, static random access memory (SRAM) (col. 16, lines 10-12)), at least one region (dynamic random access memory (DRAM) (col. 16, line 12)) corresponding to the instruction memory (Local on-chip memory 316 may include different types of off-chip memory such as, for example, dynamic random access memory (DRAM) (col. 16, lines 13-15)), and
at least one region (registers (col. 16, lines 12-13)) corresponding to the at least one control register (Local on-chip memory 314 may include different types of on-chip memory such as … registers, col. 16, lines 10-13), a communication bus (Bidirectional arrows connected to Interconnect 310 is a communication bus in Fig. 3A; The term “PCI” or “PCI-based” may be used to describe any protocol in the PCI family of bus protocols, including the original PCI standard, PCI-X, Accelerated Graphics Port (AGP), and PCI-Express(PCIe) (col. 31, lines 21-24). The Examiner notes instant specification discloses “In various embodiments, system interconnect 902 is a Peripheral Component Interconnect Express (PCIe) bus or other PCI bus” [0069]. Furthermore, bus 110 in Fig. 1 of the instant specification are bidirectional arrows) and at least one interface (As shown in FIG. 3B, interconnect 310 includes multiple ports such as, for example, an input port 340, an input port 342, and an output port 344 (col. 17, lines 43-46); In some examples, hardware data processor 306 can be directly connected to a second hardware data processor via a peer-to-peer interconnect (e.g., a peer-to-peer PCIE interconnect), and the data transfer techniques described in FIG. 5A can be used to improve data transfer over the peer-to-peer interconnect (col. 22, lines 35-40); In some examples, the PCI-based device can include single-root I/O virtualization (SR-IOV) … Thus, a PCI-based device providing a certain functionality (e.g., a network interface controller) (col. 31, lines 52-59). Instant specification discloses “Exemplary interfaces include PCIe gen4/5” [0086]) operatively connecting the neural network processor chip to the communication bus (One bidirectional arrow as communication bus connected is connected to data processor 306, Fig. 3A), and
connecting the host processor chip to the communication bus (Two bidirectional arrows as communication bus connected is connected to host 302, Fig. 3A),
wherein the at least one interface exposes the memory map to the neural network processor chip and the host processor chip for communication therebetween (As described above, interconnect 310 can provide connectivity among host 302, network adapter 308, and hardware data processor 306 (col. 17, lines 41-43); Host processor 303, host memory 304, hardware data processor 306, and network adapter 308 can be interconnected via an interconnect 310, such as a PCIE interconnect implemented as a root complex switch (col. 15, lines 63-66)), wherein the communication comprises: receiving, via the at least one region of the memory map (static random access memory (SRAM) (col. 16, line 12)) corresponding to the activation memory (Local on-chip memory 314 may include different types of on-chip memory such as, for example, static random access memory (SRAM) (col. 16, lines 10-13)), input data at the activation memory of the neural network processor chip (The data can then be moved to local on-chip memory 314 when the data is needed by computation engine 312 (col. 17, lines 28-30)) from the host processor chip (Computation engine 312 can receive an instruction from host 302 (col. 18, lines 29-30)), receiving, via the at least one region (dynamic random access memory (DRAM) (col. 16, line 12)) of the memory map corresponding to the instruction memory (Local off-chip memory 316 can also store other data that are to be fetched to other components within server computer 300 (col. 16, lines 33-35)), a neural network description at the instruction memory of the neural network processor chip (Controller 318 can fetch the descriptors from the access queue and perform read/write operations to off-chip memory 316 based on the descriptors (col. 16, lines 44-46)), and providing, from the neural network processor chip (Hardware data processor 306 is a neural network processor chip, Fig. 3A) at the activation memory (Local on-chip memory 314 may include different types of on-chip memory such as, for example, static random access memory (SRAM) (col. 16, lines 10-13)), output data to the host processor chip (bidirectional arrow from memory 314 is connected to host 302 Fig. 3A) via the at least one region of the memory map (static random access memory (SRAM) (col. 16, line 12)) corresponding to the activation memory (Local on-chip memory 314 may include different types of on-chip memory such as, for example, static random access memory (SRAM) (col. 16, lines 10-13)).
On pages 16-17 of the remarks, the Applicant argued that “It is respectfully submitted that this rejection should be withdrawn for at least the following reasons. Kaplan and Aarts, alone or in combination, do not disclose, teach or suggest each and every element of the subject claims ... Aarts fails to disclose, teach or suggest the elements of independent claims 1 and 21 (alone or in combination with the other cited references). In view of at least the foregoing discussion, assignee's representative respectfully submits that Kaplan and Aarts, alone or in combination, do not disclose or suggest all elements as recited in independent claims 1 and 21 (and claims 3, 5-9, 12, 13, 22, 24 and 25 that depend therefrom), and thus the rejection fails to establish a prima facie case of obviousness with respect to the subject claims. Accordingly, withdrawal of this rejection is respectfully requested”.
The argument above is not persuasive because as noted earlier in the above response, Kaplan’s teachings, using the broadest reasonable interpretation reads on the limitations of independent claim 1 and 21.
Furthermore, Kaplan in view of Aarts in the broadest reasonable interpretation discloses the limitation of the dependent claims 3, 5-9, 12, 13, 22, 24 and 25. The Applicant has not provided any reason why Aarts does not disclose the dependent claims or why Kaplan in view of Aarts fails to establish a prima facie case of obviousness with respect to the dependent claims.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
3. Claims 1, 3-16 and 21-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “a system interconnect device comprising: a memory map comprising at least one region corresponding to the activation memory, at least one region corresponding to the instruction memory, and at least one region corresponding to the at least one control register”.
It appears that the system interconnect device 902 in Fig. 9 of the instant specification does not comprise a memory map comprising regions. Furthermore, the instant specification discloses “the neural network processor system comprising at least one neural network processing core, an activation memory, an instruction memory, and at least one control register” [0003]. This indicates that it is the neural network processor system that comprises an activation memory, an instruction memory and control register rather than the system interconnect as claimed.
Claim 21 is similar to claim 1, so the same rationale applies.
Claims 3-16 and 22-25 that are not specifically mentioned are rejected due to dependency.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 21-25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites “wherein the system interconnect device comprises ...” which lacks antecedent basis. It is not clear which system interconnect device “the system interconnect device” is referring to because claim 21 line 2 recites “communication, by a neural network processor chip, via a system interconnect”.
Claims 22-25 that are not specifically mention because they are rejected due to dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 4, 10, 11, 14-16, 21 and 23 are rejected under 35 U.S.C
102(a)(2) as being anticipated by Kaplan et al. (US11467992 filed 09/24/2020).
Regarding claim 1, Kaplan teaches a system (FIG. 3A and FIG. 3B illustrate an example of a server computer 300, col. 15, lines 58-59)
comprising: a neural network processor chip (a hardware data processor 306 (col. 15, line 62); The hardware data processor includes a computation engine, a controller including a DMA engine, an on-chip local memory (col. 5, lines 64-65). The Examiner notes hardware data processor 306 is a neural network processor chip),
comprising: at least one neural network processing core (The hardware data processor includes a computation engine (col. 5, lines 64-65).The Examiner notes the computation engine is a neural network processing core),
wherein the at least one neural network processing core is adapted to implement neural network computation (For example, in a case where computation engine 312 implements a neural network (col. 16, lines 23-24)),
control and communication primitives (a controller including a DMA engine (col. 5, lines 65-66); hardware data processor 306 also includes a controller 318 to manage the operations of data processor 306. Controller 318 further includes a DMA engine 320 (col. 16, line 38)),
an activation memory (Local on-chip memory 314 can provide temporary storage for inputs and outputs of the computation engine. Local on-chip memory 314 may include different types of on-chip memory such as, for example, static random access memory (SRAM) (col. 24, lines 20-24). The Examiner notes memory 314 within Hardware data processor 306 in Fig. 3A comprises SRAM for storage for inputs and outputs as activation data),
an instruction memory (a memory controller of hardware data processor 306 b (not shown in the figures) can write the partial weight gradients to its local off-chip memory 316 according to the memory write instructions (col. 23, lines 9-13). The Examiner notes memory 316 within Hardware data processor 306 in Fig. 3A is an instruction memory), and
at least one control register (Hardware data processor 306 also includes a local memory, which includes a local on-chip memory 314 (col. 16, lines 7-9); Local on-chip memory 314 may include different types of on-chip memory such as … registers (col. 16, lines 10-13).The Examiner notes memory 314 within Hardware data processor 306 in Fig. 3A comprises registers),
a host processor chip (a host 302, which includes a host processor 303 and a host memory 304 (col. 15, lines 60-62); Host memory 304 can include an on-chip or an off-chip memory (col. 16, lines 64-65). The Examiner notes host 302 is a host processor chip); and
a system interconnect device (See Fig. 3A below) comprising:
a memory map (Hardware data processor 306 also includes a local memory, which includes a local on-chip memory 314 (on the same chip as computing engine 312) and a local off-chip memory 316 (col. 16, lines 7-10).The Examiner notes memory 314 and memory 316 is the memory map) comprising at least one region (static random access memory (SRAM) (col. 16, line 12)) corresponding to the activation memory (Local on-chip memory 314 may include different types of on-chip memory such as, for example, static random access memory (SRAM) (col. 16, lines 10-12)),
at least one region (dynamic random access memory (DRAM) (col. 16, line 12)) corresponding to the instruction memory (Local on-chip memory 316 may include different types of off-chip memory such as, for example, dynamic random access memory (DRAM) (col. 16, lines 13-15)), and
at least one region (registers (col. 16, lines 12-13)) corresponding to the at least one control register (Local on-chip memory 314 may include different types of on-chip memory such as … registers, col. 16, lines 10-13),
a communication bus (Bidirectional arrows connected to Interconnect 310 is a communication bus in Fig. 3A; The term “PCI” or “PCI-based” may be used to describe any protocol in the PCI family of bus protocols, including the original PCI standard, PCI-X, Accelerated Graphics Port (AGP), and PCI-Express(PCIe) (col. 31, lines 21-24). The Examiner notes instant specification discloses “In various embodiments, system interconnect 902 is a Peripheral Component Interconnect Express (PCIe) bus or other PCI bus” [0069]. Furthermore, bus 110 in Fig. 1 of the instant specification are bidirectional arrows) and
at least one interface (As shown in FIG. 3B, interconnect 310 includes multiple ports such as, for example, an input port 340, an input port 342, and an output port 344 (col. 17, lines 43-46); In some examples, hardware data processor 306 can be directly connected to a second hardware data processor via a peer-to-peer interconnect (e.g., a peer-to-peer PCIE interconnect), and the data transfer techniques described in FIG. 5A can be used to improve data transfer over the peer-to-peer interconnect (col. 22, lines 35-40); In some examples, the PCI-based device can include single-root I/O virtualization (SR-IOV) … Thus, a PCI-based device providing a certain functionality (e.g., a network interface controller) (col. 31, lines 52-59). Instant specification discloses “Exemplary interfaces include PCIe gen4/5” [0086]) operatively connecting the neural network processor chip to the communication bus (One bidirectional arrow as communication bus connected is connected to data processor 306, Fig. 3A), and
connecting the host processor chip to the communication bus (Two bidirectional arrows as communication bus connected is connected to host 302, Fig. 3A),
wherein the at least one interface exposes the memory map to the neural network processor chip and the host processor chip for communication therebetween (As described above, interconnect 310 can provide connectivity among host 302, network adapter 308, and hardware data processor 306 (col. 17, lines 41-43); Host processor 303, host memory 304, hardware data processor 306, and network adapter 308 can be interconnected via an interconnect 310, such as a PCIE interconnect implemented as a root complex switch (col. 15, lines 63-66)),
wherein the communication comprises: receiving, via the at least one region of the memory map (static random access memory (SRAM) (col. 16, line 12)) corresponding to the activation memory (Local on-chip memory 314 may include different types of on-chip memory such as, for example, static random access memory (SRAM) (col. 16, lines 10-13)),
input data at the activation memory of the neural network processor chip (The data can then be moved to local on-chip memory 314 when the data is needed by computation engine 312 (col. 17, lines 28-30)) from the host processor chip (Computation engine 312 can receive an instruction from host 302 (col. 18, lines 29-30)),
receiving, via the at least one region (dynamic random access memory (DRAM) (col. 16, line 12)) of the memory map corresponding to the instruction memory (Local off-chip memory 316 can also store other data that are to be fetched to other components within server computer 300 (col. 16, lines 33-35)),
a neural network description at the instruction memory of the neural network processor chip (Controller 318 can fetch the descriptors from the access queue and perform read/write operations to off-chip memory 316 based on the descriptors (col. 16, lines 44-46)), and
providing, from the neural network processor chip (Hardware data processor 306 is a neural network processor chip, Fig. 3A) at the activation memory (Local on-chip memory 314 may include different types of on-chip memory such as, for example, static random access memory (SRAM) (col. 16, lines 10-13)), output data to the host processor chip (bidirectional arrow from memory 314 is connected to host 302 Fig. 3A) via the at least one region of the memory map (static random access memory (SRAM) (col. 16, line 12)) corresponding to the activation memory (Local on-chip memory 314 may include different types of on-chip memory such as, for example, static random access memory (SRAM) (col. 16, lines 10-13)).
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Regarding claim 4, Kaplan teaches the system of claim 1, Kaplan teaches wherein the at least one interface comprises an Advanced eXtensible Interface (AXI), Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), Ethernet, or Firewire interface (In some examples, hardware data processor 306 can be directly connected to a second hardware data processor via a peer-to-peer interconnect (e.g., a peer-to-peer PCIE interconnect), and the data transfer techniques described in FIG. 5A can be used to improve data transfer over the peer-to-peer interconnect (col. 22, lines 35-40); In some examples, the PCI-based device can include single-root I/O virtualization (SR-IOV) … Thus, a PCI-based device providing a certain functionality (e.g., a network interface controller) (col. 31, lines 52-59))
Regarding claim 10, Kaplan the system of claim 1, Kaplan teaches wherein the neural network processor chip comprises non-volatile memory (Hardware data processor 306 also includes a local memory, which includes a local on-chip memory 314 … Local on-chip memory 314 may include different types of on-chip memory such as, for example, … non-volatile memory, such as storage class memory (SCM) and flash memory, col. 16, lines 7-17).
Regarding claim 11, Kaplan teaches the system of claim 10, Kaplan teaches wherein the neural network processor system is configured to store configuration or operating parameters, or program state (To fetch weight gradients pwgrad2, network adapter 308 can transmit one or more read descriptors, having source address based on the base address of local off-chip memory 316, and transmit the read descriptors to data processor 306 (col. 19, lines 2-5); In addition, as network adapter 308 fetches weight gradients pwgrad2 from hardware data processor 306 after receiving notification 404 from host 302, col. 19, lines 36-38).
Regarding claim 14, Kaplan teaches a networked system comprising a plurality of the system of claim 1, interconnected by a network (FIG. 1A illustrates an example of a computing cluster 100, col. 7, lines 40-41).
Regarding claim 15, Kaplan teaches a networked system comprising a plurality of the system according to claim 1 a plurality of computing nodes, interconnected by a network (The example computing cluster 100 illustrated in FIG. 1A includes multiple nodes 102 a-h, col. 7, lines 45-46).
Regarding claim 16, Kaplan teaches the networked system of claim 15, Kaplan teaches further comprising a plurality of disjoint memory maps, each corresponding to one of the plurality of the system according to claim 1 (where multiple server computers 300 can be interconnected to form computing cluster 100 of FIG. 1A, col. 15, line 67 to col. 16, lines 1-2).
Regarding claim 21, claim 21 is similar to claim 1. It is rejected in the same manner and reasoning applying. Further, Kaplan teaches communicating, by a neural network processor chip (a hardware data processor 306 (col. 15, line 62); The hardware data processor includes a computation engine, a controller including a DMA engine, an on-chip local memory (col. 5, lines 64-65). The Examiner notes hardware data processor 306 is a neural network processor chip), via a system interconnect (hardware data processor 306, and network adapter 308 can be interconnected via an interconnect 310, col. 15, lines 63-65), with a host processor chip (a host 302, which includes a host processor 303 and a host memory 304 (col. 15, lines 60-62); Host memory 304 can include an on-chip or an off-chip memory (col. 16, lines 64-65). The Examiner notes host 302 is a host processor chip),
Regarding claim 23, claim 23 is similar to claim 4. It is rejected in the same manner and reasoning applying.
6. Claims 3, 5-9, 12, 13, 22, 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kaplan et al. (US11467992 filed 09/24/2020) in view of Aarts et al. (US20210192314 filed 12/18/2019)
Regarding claim 3, Kaplan teaches the system of claim 1, Kaplan does not explicitly teach wherein the neural network processor chip exposes an Application Programming Interface (API) via the at least one interface, the API comprising methods for receiving the neural network description via the at least one interface, receiving the input data via the at least one interface, and providing the output data via the at least one interface.
Aarts teaches wherein the neural network processor chip exposes an Application Programming Interface (API) via the at least one interface (In at least one embodiment, GPU(s) 1208 may use compute application programming interface(s) (API(s) [0177]),
the API comprising methods for receiving the neural network description via the at least one interface (In at least one embodiment, an application programming interface, if performed by one or more processors, causes the one or more processors to execute a ragged recurrent neural network [0116]),
receiving the input data via the at least one interface, and providing the output data via the at least one interface (In at least one embodiment, computer system 1500 comprises, without limitation, at least one central processing unit (“CPU”) 1502 that is connected to a communication bus 1510 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), peripheral component interconnect express (“PCI-Express”) [0275]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kaplan to incorporate the teachings of Aarts for the benefit of an interface which may provide for separate phases and separate channels for transmitting control signals/addresses/data, as well as burst-type communications for continuous data transfer (Aarts [0192])
Regarding claim 5, Kaplan teaches the system of claim 1, Kaplan do not explicitly teach further comprising a redundant neural network processing core, the redundant neural network processing core configured to compute a neural network model in parallel to the at least one neural network processing core.
Aarts teaches further comprising a redundant neural network processing core (… one or more of processing engines may be idle during cycles in which that thread group is being processed [0376]),
the redundant neural network processing core configured to compute a neural network model in parallel to the at least one neural network processing core (In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group [0376]; a parallel processing system 1512 [0276]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kaplan to incorporate the teachings of Aarts for the benefit of an interface which may provide for separate phases and separate channels for transmitting control signals/addresses/data, as well as burst-type communications for continuous data transfer (Aarts [0192])
Regarding claim 6, Kaplan teaches the system of claim 1, Kaplan does not explicitly teach where the neural network processor chip is configured to provide redundant computation of a neural network model.
Aarts teaches where the neural network processor chip is configured to provide redundant computation of a neural network model (In at least one embodiment, GPU(s) 1220 may provide additional artificial intelligence functionality, such as by executing redundant … neural networks [0215]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kaplan to incorporate the teachings of Aarts for the benefit of an interface which may provide for separate phases and separate channels for transmitting control signals/addresses/data, as well as burst-type communications for continuous data transfer (Aarts [0192])
Regarding claim 7, Kaplan teaches the system of claim 1, Kaplan does not explicitly teach where the neural network processor chip is configured to provide at least one of hardware, software, and model-level redundancy.
Aarts teaches where the neural network processor chip is configured to provide at least one of hardware, software, and model-level redundancy (… one or more of processing engines may be idle during cycles in which that thread group is being processed [0376]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kaplan to incorporate the teachings of Aarts for the benefit of an interface which may provide for separate phases and separate channels for transmitting control signals/addresses/data, as well as burst-type communications for continuous data transfer (Aarts [0192])
Regarding claim 8, Kaplan teaches the system of claim 1, Kaplan does not explicitly teach wherein the neural network processor chip comprises programmable firmware, the programmable firmware configurable to process the input data and the output data.
Aarts teaches wherein the neural network processor chip comprises programmable firmware, the programmable firmware configurable to process the input data and the output data (In at least one embodiment, scheduler 2210 is implemented via firmware logic executing on a microcontroller [0360]; training and/or inferencing techniques described herein may use one or more of ALUs embodied in a 3D pipeline, graphics microcontroller 3238 [0468]; inference and/or training logic 915 may include, without limitation, code and/or data storage 901 to store forward and/or output weight and/or input/output data [0120]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kaplan to incorporate the teachings of Aarts for the benefit of an interface which may provide for separate phases and separate channels for transmitting control signals/addresses/data, as well as burst-type communications for continuous data transfer (Aarts [0192])
Regarding claim 9, Kaplan and Aarts teaches the system of claim 8, Aarts teaches wherein said processing comprises buffering (In at least one embodiment, intermediate data produced by one or more of clusters 2214A-2214N may be stored in buffers to allow intermediate data to be transmitted between clusters 2214A-2214N for further processing [0364]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kaplan to incorporate the teachings of Aarts for the benefit of an interface which may provide for separate phases and separate channels for transmitting control signals/addresses/data, as well as burst-type communications for continuous data transfer (Aarts [0192])
Regarding claim 12, Kaplan teaches the system of claim 1, Kaplan does not explicitly teach wherein the at least one interface is configured for real time or faster than real time operation.
Aarts teaches wherein the at least one interface is configured for real time or faster than real time operation (In at least one embodiment, on-premise installation may allow for high-bandwidth uses (via, for example, higher throughput local communication interfaces [0581]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kaplan to incorporate the teachings of Aarts for the benefit of an interface which may provide for separate phases and separate channels for transmitting control signals/addresses/data, as well as burst-type communications for continuous data transfer (Aarts [0192])
Regarding claim 13, Kaplan teaches the system of claim 1, Kaplan does not explicitly teach wherein the at least one interface is communicatively coupled to at least one sensor or camera.
Aarts teaches wherein the at least one interface is communicatively coupled to at least one sensor or camera (vehicle 1200 may further include network interface 1224 [0216]; vehicle 1200 may include GPU(s) 1220 … GPU(s) 1220 may provide additional artificial intelligence functionality … and may be used to train and/or update neural networks based at least in part on input (e.g., sensor data) from sensors of a vehicle 1200 [0215]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kaplan to incorporate the teachings of Aarts for the benefit of an interface which may provide for separate phases and separate channels for transmitting control signals/addresses/data, as well as burst-type communications for continuous data transfer (Aarts [0192])
Regarding claim 22, claim 22 is similar to claim 3. It is rejected in the same manner and reasoning applying.
Regarding claim 24, claim 24 is similar to claim 7. It is rejected in the same manner and reasoning applying.
Regarding claim 25, claim 25 is similar to claim 7. It is rejected in the same manner and reasoning applying.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/M.G./Examiner, Art Unit 2148
/MICHELLE T BECHTOLD/ Supervisory Patent Examiner, Art Unit 2148
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