Prosecution Insights
Last updated: August 18, 2026
Application No. 17/077,759

SYMBOLIC VALIDATION OF NEUROMORPHIC HARDWARE

Final Rejection §103
Filed
Oct 22, 2020
Examiner
GERMICK, JOHNATHAN R
Art Unit
2122
Tech Center
2100 — Computer Architecture & Software
Assignee
International Business Machines Corporation
OA Round
6 (Final)
46%
Grant Probability
Moderate
7-8
OA Rounds
0m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 46% of resolved cases
46%
Career Allowance Rate
46 granted / 101 resolved
-9.5% vs TC avg
Strong +30% interview lift
Without
With
+30.1%
Interview Lift
resolved cases with interview
Typical timeline
4y 7m
Avg Prosecution
28 currently pending
Career history
124
Total Applications
across all art units

Statute-Specific Performance

§101
28.5%
-11.5% vs TC avg
§103
39.2%
-0.8% vs TC avg
§102
17.1%
-22.9% vs TC avg
§112
14.3%
-25.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 101 resolved cases

Office Action

§103
ETAILED ACTION This action is responsive to communications filed on 04/28/2026. Claims 1, 3-7, 9-10, 12-16, 18-20 are pending in the case. Claims 1, 10 and 19 are independent claims. Claims 1, 10 and 19 are amended. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, 04/28/2026, with respect to the rejection under 35 U.S.C 101 have been fully considered and are persuasive. The Claim rejection under 35 U.S.C 101 of Claims 1, 3-7, 9, 10, 12-16, 18-20 has been withdrawn. Applicant's arguments filed 04/28/2026 with respect to 35 U.S.C. 103 have been fully considered but they are not persuasive. With respect to claim rejections under prior art: Applicant argues that Baudart does not teach or suggest the representations are used to schedule operations prior to runtime. Further, Xiao does teach or suggest prescheduling as claimed. Applicant notes the other cited references do not resolve the stated deficiencies. Examiner highlights that the claim does not require scheduling of operations prior to runtime. Specifically, the claim recites the execution of the validated network is prescheduled. That is to say scheduling may be understood to be performed at runtime, but before execution as claimed. Nevertheless, the previously cited art does not teach the prescheduling as claimed in the amendment. Examiner notes any deficiencies have been addressed in the updated rejection in view of Baudart/Beran further in view of John Brady US Document ID US 20200272515 A1. Claim Rejections - 35 U.S.C. § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3-4, 6-7, 9-10, 12-13 and 14-16, 18-19 are rejected under 35 U.S.C. § 103 as being unpatentable over Baudart et al. “Lale: Consistent Automated Machine Learning”, further in view of Beran et al. “ViNNSL - The Vienna Neural Network Specification Language”, further in view of Xiao “NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators”, further in view of John Brady US Document ID US 20200272515 A1. Regarding Claim 1/10/19 Baudart teaches, A method of validating an artificial neural network system, the method comprising: A computer program product for validating an artificial neural network system, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method… A system comprising: a computing node comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor of the computing node to cause the processor to perform a method comprising… and comparing the symbolic representation to a predetermined symbolic representation, thereby validating the artificial neural network system (pg 1 “This paper introduces Lale, a library of high-level Python interfaces that simplifies and unifies automated machine learning in a consistent way” pg 3 “p4: Check for invalid configurations early and prune them out of search spaces… This section shows Lale’s abstractions for consistent AutoML, addressing the problem statements P1 ∧ P2 ∧ P3 ∧ P4 from Section 2.” Pg 7 “This section highlights some of the trickier parts of the Lale implementation, which is entirely in Python… The Lale implementation adds Python 3 type hints so users can get additional help from tools such as MyPy, PyCharm, or VSCode…. This is demonstrated by Lale’s operators from PyTorch (BERT, ResNet50), Weka (J48), and R (ARulesCBA)” Lale is a system for validation on computers via Python, its use on a computer is demonstrated in Table 1) reading a description of the artificial neural network containing no data- dependent branching, wherein the artificial neural network is a deep artificial neural network; based on the description of the artificial neural network, constructing a symbolic representation of an output of the artificial neural network, (pg 8 “We used the CIFAR-10 computer vision dataset. We picked the ResNet50 deep-learning model, since it has been shown to do well on CIFAR-10. Our experiments kept the architecture of ResNet50 fixed and tuned learning-procedure hyperparameter” Section 6.3 pg 8 “Lale’s search space compiler takes rich hyperparameter schemas including side constraints and translates them into semantically equivalent search spaces for different AutoML tools” pg 4 “Mathematically, Lale views a pipeline as a function of the form PNG media_image1.png 27 371 media_image1.png Greyscale …This uses currying just like individual operators, plus an additional θtopology at the start to capture the steps and edges. A pipeline is trainable if both θtopology and θhyperparams are given” Lale takes a description of a deep neural network without data dependent branching as input then translates or constructs a new representation. The pipeline is a symbolic representation of the output or the neural network.) wherein the symbolic representation is a string of symbols (pg 4 “The combined schema of an operator specifies the valid values along with search guidance for its latent arguments… For didactic purposes, this section discusses only a representative subset. Figure 7 shows the JSON Schema [18] specification of that subset. The open-source Lale library includes JSON schemas for many operators PNG media_image2.png 226 434 media_image2.png Greyscale ” as shown in Figure 7, the schema for the operator within the pipeline contain string of symbols.) the symbols are defined by an architecture-specific context-free grammar the string conforms to the architecture-specific context-free grammar (pg 5 “A higher-order operator is an operator that takes another operator as an argument. Scikit-learn includes several higher-order operators including RFE, AdaBoostClassifier, and BaggingClassifier…. Lale searches both jointly, helping solve problem P3 from Section 2… A pipeline grammar is a context-free grammar that describes a possibly unbounded set of pipeline topologies” the pipeline describes the topology or architecture specific to the neural network using a context free grammar of symbols.) the symbols are independent of values included in input data such that the symbol for the at least one input activation does not reference any particular values of the at least one input activation; (pg 1 “A machine learning pipeline consists of one or more operators that take the input data through a series of transformations to finally generate predictions” pg 4 Figure 7 PNG media_image3.png 506 437 media_image3.png Greyscale none of the symbols reference particular values of the input and as such are understood to be independent of the values claimed. ) and validating, at compile time, the artificial neural network by comparing the symbolic representation to a ground truth symbolic representation, wherein validating the artificial neural network is performed independent of the input data (pg 3 “Check for invalid configurations early and prune them out of search spaces. Even if the search for each hyperparameter uses a valid range in isolation, their combination can violate side constraints… It is possible (with varying levels of difficulty) to incorporate these side constraints with the search space specification schemes… Custom validators would need to be written for each tool” pg 4 “The combined schema of an operator specifies the valid values along with search guidance for its latent arguments. It addresses problem P4 from Section 2, supporting automated search with a pruned search space and early error checking all from the same single source of truth” pg 8 Section 6.3 “Lale’s search space compiler takes rich hyperparameter schemas including side constraints” error checking from a single source of truth amounts to comparing or validating the pipeline/operator discovered to a single source of truth, i.e ground truth. Lale describes a system for compiling with constraints, thus validation happens at compile time. The hyperparameters themselves are constrained this is independent of “the input data”, where the claimed input data is at least a set of input data which is not needed for validation. ) and inferring, during run time, the validated artificial neural network using an inference processing unit (IPU)… the IPU being configured to perform neural network inference … wherein the IPU executes the validated artificial neural network, (Section 6.2 pg 8 “This section demonstrates Lale’s versatility on three datasets from different modalities. Table 2 summarizes the results” the Lale validation system is used on data sets thus used to infer using a processor corresponding to the IPU claimed.) Baudart does not explicitly teach, the symbolic representation comprises a symbol for at least one input activation… such that the symbol for the at least one input activation does not reference any particular values of the at least one input activation;…[the IPU] comprising multiple computation cores interconnected by a network-on-chip… through parallel execution across the multiple computation cores and communication through the network-on-chip. … the execution of the validated artificial neural network is prescheduled based on the symbolic representation Beran however when addressing a schema-based definition of a neural network architecture teaches, the symbolic representation comprises a symbol for at least one input activation … such that the symbol for the at least one input activation does not reference any particular values of the at least one input activation; (pg 3 “The definition schema shown in Fig. 3 is user driven and represents an XML based formal specification of a newly created neural network that has to be trained.” Pg 4 “The corresponding definition and data document are presented in Listing 1 and 2” pg 5 PNG media_image4.png 331 487 media_image4.png Greyscale the neural network definition is a symbolic representation of the structure of the neural network and includes strings for the input activation by defining the activation function as a sigmoid. The symbol does not reference any particular values.) Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the neural network declaration of Baudart with the neural network specification definition described by Beran. One would have been motivated to make such a combination because Baudart and Beran describe the benefits of universal neural network object specification. Beran notes “Based on the Grid infrastructure N2Grid allows to build up a virtual community enabling arbitrary users to exchange knowledge (neural network resources, such as neural network objects and neural network paradigms) and to exploit the available computing resources for neural network specific tasks, leading to a Grid based, world-wide distributed, neural network knowledge and simulation system” (Beran abstract). Further Baudart notes “A unified syntax would make these tools more consistent, easier to learn, and easier to switch.” (pg 3 Baudart) Baudart/Beran does not explicitly teach, [the IPU] comprising multiple computation cores interconnected by a network-on-chip… through parallel execution across the multiple computation cores and communication through the network-on-chip… the execution of the validated artificial neural network is prescheduled based on the symbolic representation Xiao however, when addressing neural network inference teaches, [the IPU] comprising multiple computation cores interconnected by a network-on-chip… and communication through the network-on-chip. (abstract “Large-scale neural network (NN) accelerators typically consist of several processing nodes, which could be implemented as a multi- or many-core chip and organized via a network-on-chip (NoC)… we propose a lightweight and NoC-aware chip-to-chip interconnection scheme, enabling efficient interconnection for NoC-based NN chips. In addition, we evaluate the proposed techniques on a four connected NoC-based deep neural network (DNN) chips with four field programmable gate arrays (FPGAs)” pg 2 “the proposed interchip and intrachip interconnection techniques, we propose a DNN accelerator with four NoC based chips organized in a 2-D mesh” pg 7 “Our architecture is targeted on DNN inference” the above describes multi core multi NOC chips interconnected for Deep neural network inference) through parallel execution across the multiple computation cores (pg 1 “NoC decouples DNN operations into data movement and computation. NoCs offer parallelism as multiple neuron processing units can communicate with each other and operate simultaneously…” pg 2 “we propose a set of virtual-channel (VC) router optimization methods…and route computation parallelization”) Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the neural network system of Baudart/Beran with the multi core neural network hardware described by Xiao. One would have been motivated to make such a combination because Baudart/Beran and Xiao describe neural network inference of deep models. In particular Xiao notes “experimental results show that the proposed interconnection network can efficiently manage the data traffic inside DNNs with high-throughput and low-overhead against state-of-the-art interconnects” (Xiao abstract) Baudart/Beran/Xiao does not explicitly teach, the execution of the validated artificial neural network is prescheduled based on the symbolic representation Brady when addressing scheduling neural network operations teaches, the execution of the validated artificial neural network is prescheduled based on the symbolic representation (para 0023 “components described herein may provide specific and particular manners of generating optimal FIFO task schedules that can leverage the representation of synchronization tasks in the compiler intermediate representation (IR) [symbolic representation]… enable dynamic scheduling, provide run-time SW with required synchronization data, and/or enable the use of HW barriers…. For example, the function allowed may include generating an execution schedule that no more than target number of HW barriers will be required to perform the execution schedule” para. 0157 “wherein the execution schedule is configured to run on a heterogeneous processor.” The execution schedule is a prescheduling based on an intermediate representation of the operations, which when combined with Baudart/Baran/Xiao/Brady describes a symbolic representation as claimed. Finally, the generated schedule, i.e preschedule, is executed by the processor.) Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the neural network declaration of Baudart/Baran/Xiao with the neural network operation prescheduling describes by Brady. One would have been motivated to make such a combination because Baudart/Baran/Xiao describe the benefit of efficient data and neural network throughput and overhead. Further, Brady notes. Brady notes “components described here may identify methods to generate execution schedules that adapt to available compute resources, increase efficiency, decrease performance costs, decrease computational cost, and/or reduce resource requirements, in an accurate, reactive, efficient, dynamic, and scalable manner, resulting in several technical effects and advantages over conventional computer technology, including increased capabilities and improved adaptability” (para 0022 Brady) Claims 10 and 19 recite essentially equivalent limitations which are rejected for the reasons provided with respect to the limitations of claim 1. Regarding Claim 3/12 Baudart/Baran/Xiao/Brady teaches claim 1/10 Baran teaches, wherein the symbolic representation has configurable granularity. (pg 2 “Our ViNNSL approach, seen as a semantic language standard… By using these schemata it is possible to describe the service capabilities, semantics, functions and parameters in a client interpretable way. We call this approach Dynamic Service Evolution (DSE) because a resource can change its semantics dynamically with respect to a defined schema” the schema of symbolic representation is changed dynamically and is therefore has configurable granularity.) Regarding Claim 4/13 Baudart/Baran/Xiao/Brady teaches claim 3/12 Baudart teaches, wherein the symbolic representation comprises at least one numeric value. (pg 4 figure 7 PNG media_image5.png 514 439 media_image5.png Greyscale the symbolic representation has numerical values.) Regarding Claim 6/15 Baudart/Baran/Xiao/Brady teaches claim 1/10 Baudart teaches, evaluating the symbolic representation using input data to determine an output of the artificial neural network. ( pg 6 “This section evaluates Lale on OpenML classification tasks and on different data modalities. It also experimentally demonstrates the importance of side constraints for the optimization process. For each experiment, we specified a Lale search space and then used auto_configure to run hyperopt on it” pg 7 “Table 1 presents the results of our experiments. For each experiment, we report the test accuracy of the best pipeline found averaged over 5 runs” the pipeline which is a symbolic representation is evaluated using input date to determine output which is a measure of accuracy.) Regarding Claim 7/16 Baudart/Baran/Xiao/Brady teaches claim 1/10 Baudart teaches, comparing the symbolic representation to a ground truth string, to validate an output of the artificial neural network system (pg 3 “Check for invalid configurations early and prune them out of search spaces. Even if the search for each hyperparameter uses a valid range in isolation, their combination can violate side constraints… It is possible (with varying levels of difficulty) to incorporate these side constraints with the search space specification schemes… Custom validators would need to be written for each tool” pg 4 “The combined schema of an operator specifies the valid values along with search guidance for its latent arguments. It addresses problem P4 from Section 2, supporting automated search with a pruned search space and early error checking all from the same single source of truth” error checking from a single source of truth amounts to comparing or validating the pipeline/operator discovered to a single source of truth, i.e ground truth) Regarding Claim 9/18 Baudart/Baran/Xiao/Brady teaches claim 1/10 Baudart teaches, wherein the symbolic representation is a directed acyclic graph ( pg 3 “A pipeline is a directed acyclic graph (DAG) of operators and a pipeline is itself also an operator. Since a pipeline contains operators and is an operator, it is highly composable” as previously noted the pipeline description and it operates is the claimed symbolic representation.) Claim(s) 5, 14 and 20 are rejected under 35 U.S.C. § 103 as being unpatentable over Baudart/Baran/Xiao/Brady, further in view of Wang “Deep Neural Network Approximation for Custom Hardware: Where We’ve Been, Where We’re Going” Regarding Claim 5/14/20 Baudart/Baran/Xiao/Brady teaches claim 1/10/19 Baudart/Baran/Xiao/Brady does not explicitly teach, determining, from a number of operations in the symbolic representation, a number of cycles required for computation of the artificial neural network. Wang teaches, determining, from a number of operations in the symbolic representation, a number of cycles required for computation of the artificial neural network. (pg 12 “On GPUs, 32 one-bit activations and weights can be packed into each word to perform bit-wise XNORs. On a Titan X Pascal GPU, 32 32-bit popcounts can be issued per cycle per streaming multiprocessor (SM). Thus, up to 512 binary MAC operations can be performed per cycle per SM” a number of MAC operations in the neural network specification, i.e symbolic representation, indicates the number of cycles required in the multiprocessor for computing the neural network.) Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the neural network system described by Baudart/Baran/Xiao/Brady to determine the number of cycles required for neural network computations, as described by Wang. Wang notes that a given number of operations can be performed in a GPU per cycle. One would have been motivated to make this combination because as noted by Beran, the simulation environment, enabled by integration of a unified neural network specification, allows “Grid computing resources to harness free processing cycles for the ”power-hungry“ neural network simulations.” (Beran pg 1) Conclusion Prior Art: Taha et al “Symbolic Interpretation of Artificial Neural Networks” describes extracting fuzzy rules, which are strings, from an existing MLP model THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHNATHAN R GERMICK whose telephone number is (571)272-8363. The examiner can normally be reached M-F 7:30-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kakali Chaki can be reached on 571-272-3719. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.R.G./ Examiner, Art Unit 2122 /KAKALI CHAKI/Supervisory Patent Examiner, Art Unit 2122
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Prosecution Timeline

Show 16 earlier events
Oct 10, 2025
Examiner Interview Summary
Oct 10, 2025
Applicant Interview (Telephonic)
Oct 31, 2025
Response after Non-Final Action
Dec 03, 2025
Request for Continued Examination
Dec 10, 2025
Response after Non-Final Action
Jan 30, 2026
Non-Final Rejection mailed — §103
Apr 28, 2026
Response Filed
May 26, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

7-8
Expected OA Rounds
46%
Grant Probability
76%
With Interview (+30.1%)
4y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 101 resolved cases by this examiner. Grant probability derived from career allowance rate.

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