Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
This Office Action is responsive to Applicants' Amendment filed on January 21, 2026, in which claims 1-3, 5, 6, 9, 11, 13, 19-21 and 24-26 are currently amended. Claims 1-26 are currently pending.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on October 16, 2025 and December 4, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to rejection of claims 1-26 under 35 U.S.C. 103 based on amendment have been considered and are persuasive.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, “the memory elements” lacks antecedent basis. Claim 1 introduces both “a first assembly of memory elements” and “respective memory elements” such that it is unclear which memory element “the memory elements” refers to. In the interest of further examination the limitation is interpreted as “each of the memory elements in the first assembly of memory elements”.
Regarding claim 1, “the output connection” lacks antecedent basis. Claim 1 introduces “at least one output connection” such that it would be unclear to one of ordinary skill in the art which output connection was “the output connection”. “The at least one output connection” is recommended.
Regarding claims 19, 24, and 26, “the output electric current” lacks antecedent basis. Claim 19 introduces “output electric currents” plural, such that it would be unclear which of the output electric currents was “the output electric current”. “An output electric current” is recommended.
The remaining claims are rejected with respect to their dependence on the rejected claims.
Allowable Subject Matter
Below are the closest cited references, each of which disclose various aspects of the claimed invention:
Deng (“Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation”, 2020)
Diehl (“Conversion of Artificial Recurrent Neural Networks to Spiking Neural Networks for Low-power Neuromorphic Hardware”, 2016)
Ma (US20180075344A1)
However, none of the prior art references of record, alone or in combination, disclose or suggest the combined features recited in the independent claims, including specifically (for claim 1):
the first neuromorphic neuron apparatus is switchable in a first mode and in a second mode, the first neuromorphic neuron apparatus comprises an input, an accumulation block having a state variable, and a first assembly of memory elements in a crossbar array, the first assembly of memory elements comprises input connections for applying corresponding voltages to generate single electric currents in respective memory elements and at least one output connection for outputting an output electric current to one or more neural networks, and the memory elements are connected to each other such that the output electric current is a sum of the single electric currents, the output connection of the first assembly is coupled to the input, and an analog digital converter converts the output electric current into a current input signal of the first neuromorphic neuron apparatus
While the primary reference of Deng discloses a neuromorphic circuit capable of operating in both an SNN and ANN mode, Deng does not explicitly disclose "the memory elements are connected to each other such that the output electric current is a sum of the single electric currents, the output connection of the first assembly is coupled to the input, and an analog digital converter converts the output electric current into a current input signal of the first neuromorphic neuron apparatus" or "wherein the second mode requires a larger time step size associated with the one or more neural networks than the first mode". While Diehl in the same field of endeavor provides motivation for having different step sizes associated with each mode, Diehl does not explicitly disclose "the memory elements are connected to each other such that the output electric current is a sum of the single electric currents, the output connection of the first assembly is coupled to the input, and an analog digital converter converts the output electric current into a current input signal of the first neuromorphic neuron apparatus". While Ma teaches a neuromorphic apparatus comprising an ADC that can operate in different modes including ANN, RNN, and SNN modes, Ma does not disclose "the memory elements are connected to each other such that the output electric current is a sum of the single electric currents, the output connection of the first assembly is coupled to the input, and an analog digital converter converts the output electric current into a current input signal of the first neuromorphic neuron apparatus" nor would it have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Deng, Diehl, and Ma to arrive at the claimed invention.
Claims 1-26 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kang (CN-107273972-A) is directed towards a multimodal hybrid analog/digital neuromorphic circuit.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDNEY VINCENT BOSTWICK whose telephone number is (571)272-4720. The examiner can normally be reached M-F 7:30am-5:00pm EST.
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/SIDNEY VINCENT BOSTWICK/Examiner, Art Unit 2124
/MIRANDA M HUANG/Supervisory Patent Examiner, Art Unit 2124
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