DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 12/30/2025 has been entered.
Allowable Subject Matter
The indicated allowability of claim(s) 1-10 and 19-23 is withdrawn in view of the newly discovered reference(s) Chung et al. (US publication 2022/0059662 A1). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-3, 6-7, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Khayat et al. (US publication 2018/0219533 A1), hereinafter referred to as Khayat533, in view of Chung et al. (US publication 2022/0059662 A1), hereinafter referred to as Chung662.
Regarding claim 1, Khayat533 teaches a semiconductor device (fig. 3 and related text), comprising: an epitaxial layer (114, [0031]) over a semiconductor substrate (116, [0031]), the epitaxial layer including a body region (106, [0030]) having a first conductivity type (p-type) and a drain drift region (110, [0031]) having a second, opposite, conductivity type (n-type); a gate dielectric layer (118, [0032]) over the body region and extending over a junction between the body region and the drain drift region (fig. 3); a gate electrode (120, [0032]) over the gate dielectric layer; a drain region (108, [0030]) having the second conductivity type in the drain drift region (fig. 3), the drain region having an average dopant density greater than an average dopant density of the drain drift region (fig. 3); a field relief dielectric layer (152, [0039]) over the drain drift region, the field relief dielectric layer extending from the gate dielectric layer toward the drain region and having a thickness greater than the gate dielectric layer (fig. 3); and a field plate (154, [0039]) located over the field relief dielectric layer and between the gate electrode and the drain region (fig. 3).
Khayat533 does not explicitly teach the field plate conductively connected to the drain region.
Chung662 teaches the field plate (118a, [0035]) conductively connected to the drain region (122, [0035], fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Khayat533 with that of You186 so that the field plate conductively connected to the drain region so that reliability, lifetime, and overall performance of the device may be improved ([0036]).
Regarding claim 2, Khayat533 teaches wherein the field plate follows a path that has rounded corners with radii greater than a thickness of the field plate (fig. 3).
Regarding claim 3, Khayat533 teaches wherein the field plate runs about parallel to the drain region (fig. 3).
Regarding claim 6, Khayat533 teaches wherein the first conductivity type is p-type and the second conductivity type is n-type (fig. 3).
Regarding claim 7, Khayat533 teaches wherein the field plate includes polycrystalline silicon ([0032], fig. 3).
Regarding claim 9, Khayat533 teaches wherein the field plate extends between the drain region and the gate by a distance that is at least twice the thickness of the field relief dielectric layer (fig. 3).
Regarding claim 10, Khayat533 teaches wherein the field plate extends over a tapered edge of the field relief dielectric layer (fig. 3).
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US publication 2022/0059662 A1), hereinafter referred to as Chung662, in view of Khayat et al. (US publication 2018/0219533 A1), hereinafter referred to as Khayat533.
Regarding claim 1, Chung662 teaches a semiconductor device (fig. 3 and related text), comprising: a semiconductor layer (112/114, [0015], fig. 3) over a semiconductor substrate (110, [0015], fig. 3), the semiconductor layer including a body region (114) having a first conductivity type (p-type, [0018]) and a drain drift region (112) having a second, opposite, conductivity type (n-type, [0018]); a gate dielectric layer (120a, [0022]) over the body region and extending over a junction between the body region and the drain drift region (fig. 3); a gate electrode (120b, [0022]) over the gate dielectric layer; a drain region (122, [0015]) having the second conductivity type in the drain drift region ([0025], fig. 3); a field relief dielectric layer (116, [0015]) over the drain drift region, the field relief dielectric layer extending from the gate dielectric layer toward the drain region and having a thickness greater than the gate dielectric layer (fig. 3); and a field plate (118, [0015]) located over the field relief dielectric layer and between the gate electrode and the drain region (fig. 3).
Chung662 does not explicitly teach an epitaxial layer over a semiconductor substrate, the epitaxial layer including a body region and a drain drift region, the drain region having an average dopant density greater than an average dopant density of the drain drift region.
Khayat533 teaches an epitaxial layer (114, [0031], fig. 3]) over a semiconductor substrate (116, [0031]), the epitaxial layer including a body region (106, [0030]) and a drain drift region (110, [0031]), the drain region (108, [0030]) having an average dopant density greater than an average dopant density of the drain drift region (fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chung662 with that of Khayat533 so that an epitaxial layer over a semiconductor substrate, the epitaxial layer including a body region and a drain drift region, the drain region having an average dopant density greater than an average dopant density of the drain drift region for reducing switching power losses, thus improving efficiency of switch mode power converters, including DC-to-DC converters ([0016]).
Claim 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Khayat533 in view of Chung662, as applied to claim 1 above, in view of You et al. (US publication 2019/0363186 A1), hereinafter referred to as You186.
Regarding claim 4, Khayat533 and Chung662 disclose all the limitations of claim 1 as discussed above on which this claim depends.
Khayat533 also teaches wherein the field relief dielectric layer includes a local oxidation of silicon (LOCOS) layer of silicon dioxide ([0039]).
Khayat533 and Chung662 do not explicitly teach and the field plate is located over a point at which the LOCOS layer ends at a top surface of the epitaxial layer.
You186 teaches and the field plate is located over a point at which the LOCOS layer ends at a top surface of the epitaxial layer (fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Khayat533 and Chung662 with that of You186 so that and the field plate is located over a point at which the LOCOS layer ends at a top surface of the epitaxial layer for increasing the voltage withstanding performance of the structure ([0024]).
Regarding claim 5, Khayat533 and Chung662 disclose all the limitations of claim 1 as discussed above on which this claim depends.
Khayat533 also teaches wherein the gate electrode is spaced apart from the field plate by a silicide blocking layer (gate electrode and field plate are spaced apart by sidewall spacers, fig. 3).
Khayat533 and Chung662 do not explicitly teach wherein the gate electrode extends over the field relief dielectric layer.
You186 teaches wherein the gate electrode extends over the field relief dielectric layer (Gate extends over Oxide, fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Khayat533 and Chung662 with that of You186 so that wherein the gate electrode extends over the field relief dielectric layer thereby the gate charge of the semiconductor structure may be decreased ([0027]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Khayat533 in view of Chung662, as applied to claim 1 above, and further in view of Chen et al. (US publication 2015/0123199 A1), hereinafter referred to as Chen199.
Regarding claim 8, Khayat533 and Chung662 disclose all the limitations of claim 1 as discussed above on which this claim depends.
Khayat533 and Chung662 do not explicitly teach wherein the gate electrode and the field plate have a closed-loop configuration.
Chen199 teaches wherein the gate electrode and the field plate have a closed-loop configuration ([0031], fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Khayat533 and Chung662 with that of Chen199 so that wherein the gate electrode and the field plate have a closed-loop configuration so that the device can endure sufficient high breakdown voltage, low on-resistance characteristic can be provided, and energy consumption of the device can be reduced ([0032]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Khayat533 in view of Chung662, as applied to claim 1 above, and further in view of Kim et al. (US publication 2019/0386134 A1), hereinafter referred to as Kim134.
Regarding claim 19, Khayat533 and Chung662 discloses all the limitations of claim 1 as discussed above on which this claim depends.
Khayat533 and Chung662 do not explicitly wherein a sidewall spacer on a sidewall of the field plate extends to the drain region.
Kim134 teaches wherein a sidewall spacer (258, [0067]) on a sidewall of the field plate extends to the drain region (fig. 17d).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Khayat533 and Chung662 with that of Kim134 so that wherein a sidewall spacer on a sidewall of the field plate extends to the drain region for optimization of the breakdown voltage and the on-resistance characteristic ([0003]).
Claim 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Khayat et al. (US publication 2018/0219533 A1), hereinafter referred to as Khayat533, in view of Chung et al. (US publication 2022/0059662 A1), hereinafter referred to as Chung662, and further in view of You et al. (US publication 2019/0363186 A1), hereinafter referred to as You186.
Regarding claim 20, Khayat533 teaches a semiconductor device (fig. 3 and related text), comprising: an epitaxial layer (114, [0031]) over a semiconductor substrate (116, [0031]), the epitaxial layer including a body region (106, [0030]) having a first conductivity type (p-type) and a drain drift region (110, [0031]) having a second, opposite, conductivity type (n-type); a gate dielectric layer (118, [0032]) over the body region and extending over a junction between the body region and the drain drift region (fig. 3); a gate electrode (120, [0032]) over the gate dielectric layer; a drain region (108, [0030]) having the second conductivity type in the drain drift region (fig. 3), the drain region having an average dopant density greater than an average dopant density of the drain drift region (fig. 3); a field relief dielectric layer (152, [0039]) over the drain drift region, the field relief dielectric layer extending from the gate dielectric layer toward the drain region and having a thickness greater than the gate dielectric layer (fig. 3); and a field plate (154, [0039]) located over the field relief dielectric layer and between the gate electrode and the drain region (fig. 3), wherein the gate electrode is spaced apart from the field plate by a silicide blocking layer (gate electrode and field plate are spaced apart by sidewall spacers, fig. 3).
Khayat533 does not explicitly teach the field plate conductively connected to the drain region.
Chung662 teaches the field plate (118a, [0035]) conductively connected to the drain region (122, [0035], fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Khayat533 with that of Chung662 so that the field plate conductively connected to the drain region so that reliability, lifetime, and overall performance of the device may be improved ([0036]).
Khayat533 and Chung662 do not explicitly teach wherein the gate electrode extends over the field relief dielectric layer.
You186 teaches wherein the gate electrode extends over the field relief dielectric layer (Gate extends over Oxide, fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Khayat533 and Chung662 with that of You186 so that wherein the gate electrode extends over the field relief dielectric layer thereby the gate charge of the semiconductor structure may be decreased ([0027]).
Regarding claim 21, Khayat533 teaches wherein the first conductivity type is p-type and the second conductivity type is n-type (fig. 3).
Regarding claim 22, Khayat533 teaches wherein the field plate extends between the drain region and the gate by a distance that is at least twice the thickness of the field relief dielectric layer (fig. 3).
Regarding claim 23, Khayat533 teaches wherein the field plate extends over a tapered edge of the field relief dielectric layer (fig. 3).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 29-31 and 33 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung et al. (US publication 2022/0059662 A1), hereinafter referred to as Chung662.
Regarding claim 29, Chung662 teaches a semiconductor device (fig. 4 and related text), comprising: a first doped region (124, [0025]) having a first conductivity type (conductivity type of 124a (n-type or p-type) or 124b (p-type or n-type), [0025]) within a semiconductor layer (112/114, [0018-0019]); a second doped region (122, [0015]) having the first conductivity type (n-type or p-type, [0018-0019 and 0025]) within the semiconductor layer (fig. 4), the second doped region being laterally spaced apart from the first doped region along a top surface of the semiconductor layer (fig. 4); a first electrode (118b, [0021 and 0030]) extending over the top surface between the first doped region and the second doped region (fig. 4); a second electrode (118a, [0021 and 0030]) laterally spaced apart from the first electrode and extending over the top surface between the first electrode and the second doped region (fig. 4); and a conductive connection (128/142, [0033]) between the second electrode and the second doped region (fig. 4).
Regarding claim 29, Chung662 teaches a semiconductor device (fig. 4 and related text), comprising: a first doped region (124, [0025]) having a first conductivity type (conductivity type of 124a (n-type or p-type) or 124b (p-type or n-type), [0025]) within a semiconductor layer (112/114, [0018-0019]); a second doped region (122, [0015]) having the first conductivity type (n-type or p-type, [0018-0019 and 0025]) within the semiconductor layer (fig. 4), the second doped region being laterally spaced apart from the first doped region along a top surface of the semiconductor layer (fig. 4); a first electrode (120b, [0022]) extending over the top surface between the first doped region and the second doped region (fig. 4); a second electrode (118b, [0021 and 0030]) laterally spaced apart from the first electrode and extending over the top surface between the first electrode and the second doped region (fig. 4); and a conductive connection (128/142, [0033]) between the second electrode and the second doped region (fig. 4).
Regarding claim 30, Chung662 teaches wherein the first and second electrodes extend over a local oxidation of silicon (LOCOS) structure (116, [0020], fig. 4).
Regarding claim 31, Chung662 teaches wherein the first and second doped regions are respectively a source region (124, [0025]) and a drain region (122, [0015]) of a field-effect transistor (fig. 4).
Regarding claim 33, Chung662 teaches wherein the conductive connection includes vertical (142) and horizontal interconnects (128) within a dielectric layer (140, [0027]) over the top surface (fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Chung662, as applied to claim 29 above, in view of Khayat et al. (US publication 2018/0219533 A1), hereinafter referred to as Khayat533.
Regarding claim 32, Chung662 discloses all the limitations of claim 29 as discussed above on which this claim depends.
Chung662 does not explicitly teach wherein the second electrode is spaced apart from the second doped region by a dielectric spacer connected to a sidewall of the second electrode.
Khayat533 teaches wherein the second electrode (154, [0039], fig. 3) is spaced apart from the second doped region (NPLUS) by a dielectric spacer (sidewall of 154, fig. 3) connected to a sidewall of the second electrode (fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chung662 with that of Khayat533 so that wherein the second electrode is spaced apart from the second doped region by a dielectric spacer connected to a sidewall of the second electrode for reducing switching power losses, thus improving efficiency of switch mode power converters, including DC-to-DC converters ([0016]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897