DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-5, 12-13, 20 and 23-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3, 4, 12-13 and 20 recite the limitation “ostensibly good quality,” but the limitation “ostensibly good quality” is a subjective term, and as such, indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 7, 9-11 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Asbag et al., US-PGPUB 2019/0333208 (hereinafter Asbag) in view of Niewczas et al., US-PGPUB 2020/0272865 (hereinafter Niewczas) and Trumbauer et al., US-PGPUB 2018/0047149 (hereinafter Trumbauer)
Regarding Claims 1, 10 and 16-17. Asbag discloses
electrically testing a semiconductor wafer (Paragraphs [0004]-[0007]),
failed die clustering (Fig. 3, each square in the wafer is a die; Paragraph [0010], defect clusters; Paragraph [0003], Paragraphs [0043]-[0044], scanning at an entire die), comprising:
extracting a data set of failed die on the semiconductor wafer from a wafer map for the wafer (Fig. 2, 202; Paragraph [0010], obtain one more defect clusters; Paragraph [0046], can include false alarms or [0004], false positives; Paragraphs [0002]-[0003], semiconductor wafer); determining a density parameter for clustering the failed die (Paragraph [0010], spatial density; [0052]; [0062]; [0065]); removing false failures from the data set of failed die to generate a reduced data set of failed die (Paragraph [0082], nuisance defects are filtered out; where nuisance defects include false/alarms (Paragraphs [0048]-[0050]), removing failed die in low failure regions of the wafer from the reduced data set (Fig. 2, 203, defect filtration for the non-clustered defect), locating clusters of failed die in the reduced data set after removing the failed die in the low failure density regions (Fig. 2, 208; Paragraph [0034], Fig. 5 illustrating the DOI identified on a defect map; Paragraphs [0032]; [0035]; Paragraphs [0054]; [0062]-[0068])
Asbag does not disclose locating clusters of failed die in the reduced data set by executing a density-based spatial clustering of applications with noise (DBSCAN) algorithm with the density parameter, and applying a guard band to each located cluster.
Niewczas discloses classifying and locating the identified defects using DBSCAN (Paragraphs [0024], classification based on different features, Figs. 2A, B; [0026]-[0028])
Trumbauer discloses applying guard banding to located cluster (Fig. 10B; Paragraph [0034]; [0068]; [0072]; [0005])
At the time of the invention filed, it would have been obvious to a person of ordinary skill in the art to use the teaching of Niewczas and Trumbauer in Asbag and accurately locate clusters of failed die in the reduced data set, after removing the failed die in the low failure density regions by executing a density-based spatial clustering of applications with noise (DBSCAN) algorithm with the density parameter, and apply a guard band to each located cluster, so as to improve reliability.
Regarding Claims 2, 11 and 18. Asbag discloses a failed die is in a low failure density region when the die has less than three failed die neighbors within a radius of three die from the failed die (Paragraphs [0071]-[0072], filtering the non-clustered defects; Fig. 3, such as 307, 308)
Regarding Claim 7. Trumbauer discloses using a user specified width for the guard band (Figs. 8 and 9; Paragraphs [0021]-[0022])
Regarding Claims 9 and 15. Asbag discloses the wafer map is generated by electrical probe testing of the wafer (Paragraph [0046]; [0049])
6. Claims 3, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Asbag, US-PGPUB 2019/033208 in view of Niewczas, US-PGPUB 2020/0272865 and Trumbauer, US-PGPUB 2018/0047149 as applied to Claim 1 above, and further in view of Moreno-Lizaranzu et al., “Improving Electronic Sensor reliability by robust outlier screening,” Sensors (2013) (hereinafter Moreno) (cited by the Applicant)
Regarding Claim 3. Asbag discloses failed die clustering (Fig. 3, each square in the wafer is a die; Paragraph [0010], defect clusters; Paragraph [0003], Paragraphs [0043]-[0044], scanning at an entire die), comprising:
connecting a semiconductor wafer to a testing system (Paragraphs [0004]-[0007]),
extracting a data set of failed die on the semiconductor wafer from a wafer map for the semiconductor wafer (Fig. 2, 202; Paragraph [0010], obtain one more defect clusters; Paragraph [0046], can include false alarms or [0004], false positives); determining a density parameter for clustering the failed die (Paragraph [0010], spatial density; [0052]; [0062]; [0065]); removing false failures from the data set of failed die to generate a reduced data set of failed die (Paragraph [0082], nuisance defects are filtered out; where nuisance defects include false/alarms (Paragraphs [0048]-[0050]), removing failed die in low failure regions of the wafer from the reduced data set (Fig. 2, 203, defect filtration for the non-clustered defect), locating clusters of failed die in the reduced data set after removing the failed die in the low failure density regions (Paragraph [0034], Fig. 5 illustrating the DOI identified on a defect map; Paragraphs [0032]; [0035]; Paragraphs [0054]; [0062]-[0068])
Asbag does not disclose locating clusters of failed die in the reduced data set by executing a density-based spatial clustering of applications with noise (DBSCAN) algorithm with the density parameter, and applying a guard band to each located cluster.
Niewczas discloses classifying and locating the identified defects using DBSCAN (Paragraphs [0024]; [0026]-[0028])
Trumbauer discloses applying guard banding to located cluster (Fig. 10B; Paragraph [0034]; [0068]; [0072]; [0005])
At the time of the invention filed, it would have been obvious to a person of ordinary skill in the art to use the teaching of Niewczas and Trumbauer in Asbag and accurately locate clusters of failed die in the reduced data set after removing the failed die in the low failure density regions by executing a density-based spatial clustering of applications with noise (DBSCAN) algorithm with the density parameter, and apply a guard band to each located cluster, so as to improve reliability.
Asbag further discloses locating clusters of trapped good die (Fig. 3, 303). The modified Asbag does not explicitly disclose indicating that the trapped die are of ostensibly good quality.
Moreno discloses locating clusters of trapped good die and indicating that the trapped die are of ostensibly good quality (Section 3.1; Fig. 5; Introduction)
At the time of the invention filed, it would have been obvious to a person of ordinary skill in the art to use the teaching of Moreno in the modified Asbag and locate clusters of trapped good die and indicate that the trapped die are of ostensibly good quality, so as to improve reliability.
Regarding Claims 12 and 20. Asbag discloses locating clusters of trapped good die (Fig. 3, 303). The modified Asbag does not explicitly disclose indicating that the trapped die are of ostensibly good quality.
Moreno discloses locating clusters of trapped good die and indicating that the trapped die are of ostensibly good quality (Section 3.1; Fig. 5; Introduction)
At the time of the invention filed, it would have been obvious to a person of ordinary skill in the art to use the teaching of Moreno in the modified Asbag and locate clusters of trapped good die and indicate that the trapped die are of ostensibly good quality, so as to improve reliability.
7. Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Asbag et al., US-PGPUB 2019/0333208 in views of Niewczas et al., US-PGPUB 2020/0272865 and Trumbauer et al., US-PGPUB 2018/0047149 as applied to Claim 1, and further in view of Balog, US-PGPUB 2007/0233629 (hereinafter Balog)
Regarding Claims 21-22. The modified Asbag does not further disclose including evaluating results of the testing versus statistical yield and bin limits, and further releasing the semiconductor wafer for further processing when the evaluated results meet or exceed the statistical yield and bin limits
Balog disclose including evaluating results of the testing versus statistical yield and bin limits, and further releasing the semiconductor wafer for further processing when the evaluated results meet or exceed the statistical yield and bin limits (Paragraph [0095])
Statistical bin limit is a benchmark for quality control in semiconductor industry. As such, at the time of the invention filed, it would have been obvious to a person of ordinary skill in the art to use the teaching of Balog in the modified Asbag and evaluate results of the testing versus statistical yield and bin limits, and further release the semiconductor wafer for further processing when the evaluated results meet or exceed the statistical yield and bin limits, so as to improve product reliability.
8. Claims 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Asbag, US-PGPUB 2019/033208 in views of Niewczas, US-PGPUB 2020/0272865, Trumbauer, US-PGPUB 2018/0047149 and Moreno-Lizaranzu et al., “Improving Electronic Sensor reliability by robust outlier screening,” Sensors (2013) as applied to Claim 3 above, and further in view of Balog, US-PGPUB 2007/0233629.
Regarding Claims 23 and 25. The modified Asbag does not further disclose including evaluating results of the testing versus statistical yield and bin limits, and further releasing the semiconductor wafer for further processing when the evaluated results meet or exceed the statistical yield and bin limits
Balog disclose including evaluating results of the testing versus statistical yield and bin limits, and further releasing the semiconductor wafer for further processing when the evaluated results meet or exceed the statistical yield and bin limits (Paragraph [0095])
Statistical bin limit is a benchmark for quality control in semiconductor industry. As such, at the time of the invention filed, it would have been obvious to a person of ordinary skill in the art to use the teaching of Balog in the modified Asbag and evaluate results of the testing versus statistical yield and bin limits, and further release the semiconductor wafer for further processing when the evaluated results meet or exceed the statistical yield and bin limits, so as to improve product reliability.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims (6, 25-26) and (14, 29-30) are allowed. The reasons for allowance is given in the previous Office Action, sent on 10/29/2025.
Response to Arguments
Applicant's arguments filed 04/27/2026 have been fully considered but they are not persuasive.
Applicant argues the following:
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678
876
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186
874
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830
782
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354
754
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594
860
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584
882
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604
894
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472
888
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416
916
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176
900
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420
746
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388
870
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344
868
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422
750
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392
748
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424
756
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340
876
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298
886
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688
890
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In Response, the Examiner respectfully disagrees. Asbag discloses electrically testing a semiconductor wafer (Paragraphs [0004]-[0007]), and extracting a data set of failed die on the semiconductor wafer from a wafer map for the wafer (Fig. 2, 202; Paragraph [0010], obtain one more defect clusters; Paragraph [0046], can include false alarms or [0004], false positives; Paragraphs [0002]-[0003], semiconductor wafer); determining a density parameter for clustering the failed die (Paragraph [0010], spatial density; [0052]; [0062]; [0065]); removing false failures from the data set of failed die to generate a reduced data set of failed die (Paragraph [0082], nuisance defects are filtered out; where nuisance defects include false/alarms (Paragraphs [0048]-[0050]), removing failed die in low failure regions of the wafer from the reduced data set (Fig. 2, 203, defect filtration for the non-clustered defect), locating clusters of failed die in the reduced data set after removing the failed die in the low failure density regions (Fig. 2, 208; Paragraph [0034], Fig. 5 illustrating the DOI identified on a defect map; Paragraphs [0032]; [0035]; Paragraphs [0054]; [0062]-[0068])
Asbag further discloses removing failed die in low failure regions of the wafer from the reduced data set (Fig. 2, 203, defect filtration for the non-clustered defect), locating clusters of failed die in the reduced data set after removing the failed die in the low failure density regions (Fig. 2, 208). Meanwhile, Niewczas discloses classifying and locating the identified defects using DBSCAN (Paragraph [0028]) where the clusters are classified according to having similar features, as shown in Figs. 2A and 2B (Paragraph [0024]). Note that DBSCAN is a known method in semiconductor industry. Thus, the combination of Asbag and Niewczas would allow the locating and classification between the data set of failed die in low failure density region (or non-clustered defect) and data set of failed die in higher failure density region using DBSCAN (since different density regions have different features). The above Examiner’s response also applies to other independent claims.
Applicant further argues the following:
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250
882
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758
746
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410
860
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In Response, the Examiner respectfully disagrees, and state that Asbag discloses a failed die is in a low failure density region when the die has less than three failed die neighbors within a radius of three die from the failed die (Paragraphs [0071]-[0072], filtering the non-clustered defects; Fig. 3, such as 307, 308)
Applicant argues the following:
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116
888
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656
920
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In Response, the Examiner respectfully disagrees. Asbag discloses failed die clustering (Fig. 3, each square in the wafer is a die; Paragraph [0010], defect clusters; Paragraph [0003], Paragraphs [0043]-[0044], scanning at an entire die), comprising:
connecting a semiconductor wafer to a testing system (Paragraphs [0004]-[0007]),
extracting a data set of failed die on the semiconductor wafer from a wafer map for the semiconductor wafer (Fig. 2, 202; Paragraph [0010], obtain one more defect clusters; Paragraph [0046], can include false alarms or [0004], false positives); determining a density parameter for clustering the failed die (Paragraph [0010], spatial density; [0052]; [0062]; [0065]); removing false failures from the data set of failed die to generate a reduced data set of failed die (Paragraph [0082], nuisance defects are filtered out; where nuisance defects include false/alarms (Paragraphs [0048]-[0050]), removing failed die in low failure regions of the wafer from the reduced data set (Fig. 2, 203, defect filtration for the non-clustered defect), locating clusters of failed die in the reduced data set after removing the failed die in the low failure density regions (Paragraph [0034], Fig. 5 illustrating the DOI identified on a defect map; Paragraphs [0032]; [0035]; Paragraphs [0054]; [0062]-[0068]), Niewczas discloses classifying and locating the identified defects using DBSCAN (Paragraphs [0024]; [0026]-[0028]), Trumbauer discloses applying guard banding to located cluster (Fig. 10B; Paragraph [0034]; [0068]; [0072]; [0005]). Asbag further discloses locating clusters of trapped good die (Fig. 3, 303). Moreno discloses locating clusters of trapped good die and indicating that the trapped die are of ostensibly quality (Section 3.1; Fig. 5; Introduction)
Applicant argues the following:
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256
892
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In Response, the Examiner respectfully disagrees and states that Moreno discloses locating clusters of trapped good die and indicating that the trapped die are of ostensibly good quality (Section 3.1; Fig. 5; Introduction)
Applicant argues the following:
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258
890
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In Response, the Examiner respectfully disagrees. Moreno discloses locating clusters of trapped good die and indicating that the trapped die are of ostensibly good quality (Section 3.1; Fig. 5; Introduction)
Applicant argues the following:
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144
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In Response, the Examiner respectfully disagrees and state that Balog disclose including evaluating results of the testing versus statistical yield and bin limits, and further releasing the semiconductor wafer for further processing when the evaluated results meet or exceed the statistical yield and bin limits (Paragraph [0095])
Applicant argues the following:
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326
854
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In Response, the Examiner respectfully disagrees and states that Balog disclose including evaluating results of the testing versus statistical yield and bin limits, and further releasing the semiconductor wafer for further processing when the evaluated results meet or exceed the statistical yield and bin limits (Paragraph [0095])
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HYUN D PARK whose telephone number is (571)270-7922. The examiner can normally be reached 11-4.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arleen Vazquez can be reached at 571-272-2619. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HYUN D PARK/Primary Examiner, Art Unit 2857
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