Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-2, 4-10, 12-18 and 20-23 are currently pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-10, 12 and 14-18, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Vohra et al. (U.S. Patent No. 8522241 B1) in view of Liao et al. (U.S. Pub. No. 20080049031 A1), further in view of Nagarajan et al. (U.S. Pub. No. 20170031622 A1), and further in view of Bailey et al. (U.S. Pub. No. 20200004575 A1).
Vohra, Liao and Nagarajan were cited in a previous Office Action.
As per claim 1, Vohra teaches the invention substantially as claimed including system for resource allocation for different stages of a data pipeline, the system comprising:
one or more computer processors; and a memory containing a buffer monitor of a program configured to manage workload execution in the data pipeline, the data pipeline comprising a first data pipeline, the program comprising a plurality of components including the buffer monitor and a resource manager (col. 6, lines 42-45 The monitoring computer 125 may likewise have a memory and one or more processors that execute computer-executable instructions from the memory; col. 7, lines 17-20 each processing computer 105a-n may include a respective plurality of processing stages arranged in one or more sequential orders, as described herein (see, e.g., FIG. 2). The memory 128 of a processing computer 105a-n may also include a monitoring & resource allocation module 141), the buffer monitor executable by the one or more computer processors to perform an operation comprising:
measuring, in real time, a level of utilization of an inter-stage buffer comprising a buffer between two sequential stages of a plurality of stages of the data pipeline, the buffer configured to store data output by a first stage of the two sequential stages, the data being stored in the buffer for subsequent use as input data of a second stage of the two sequential stages (col. 7, lines 25-33 the monitoring & resource allocation module 141 may be configured to monitor the processing power or hardware resource utilization (e.g., queue length, processor utilization, and/or memory utilization) of one or more of the processing stages of a processing computer 105a-n. Based at least in part on the monitored processing power or hardware resource utilization, the monitoring & resource allocation module 141 may determine whether a processing stage is under-utilized or over-utilized. That is, the monitoring & resource allocation module is configure to monitor/measure current memory utilization of processing stages and determine whether a processing stage overutilized/underutilized based on the utilization levels monitored; col. 9, lines 35-38 the synchronous communication channel 265 may provide an output queue [equiv. to inter-stage buffer] for one or more processing stages 206a-n to receive a result of the processing of the corresponding processing stage 206a-n; Col. 9, Lines 36-44 “Optionally, the synchronous communication channel 265 may provide an output queue for one or more processing stages 206 a-n to receive a result of the processing of the corresponding processing stage 206 a-n. If output queues are utilized, then the asynchronous communications channel 265 may obtain results of processing from an output queue of a processing stage 206 a-n and deliver the results to a request queue of a subsequent processing stage 206 a-n),
comparing the measurement to a first threshold and a second threshold, wherein the first threshold indicates a high utilization of the [resources], and wherein the second threshold indicates a low utilization of the [resources] (col. 3, lines 53-55 The monitoring of the processing stages may include comparing the hardware resource utilization … of a processing stage to one or more thresholds; col. 12, lines 34-37 the monitoring & resource allocation module 141 may determine whether one or more criteria for auto-balancing processing stages may be met. Example criteria may include any of the following: (i) whether at least one processing stage has a hardware resource utilization … that is below a lower rebalancing threshold [second threshold] while at least one other processing stage has a hardware resource utilization above the lower rebalancing threshold or (ii) whether at least one processing stage has hardware resource utilization … that is above a higher rebalancing threshold [first threshold] while at least one other processing stage has a hardware resource utilization below the higher rebalancing threshold. If the example criteria (i) is satisfied, then those processing stages having respective hardware resource utilizations that are below the lower rebalancing threshold may be identified as under-utilized (or underloaded) processing stages … On the other hand, if criteria (ii) is satisfied, then those process stages having respective hardware resource utilizations),
generating a signal based on the comparison of the measurement to the first threshold, and outputting the signal, wherein the signal causes the resource manager to adjust an amount of compute resources allocated to the first stage by deallocating one or more compute resources from the first stage … (col. 4, lines 4-16, To provide for auto-balancing of the throughput … allocations of hardware resources can be adjusted for under-utilized or over-utilized processing stages. For example, the processing power or allocation of hardware resources can be decreased for an under-utilized processing stage, such as by reducing the number of processing threads or processing instances provided for the under-utilized processing stage. On the other hand, the processing power or allocation of hardware resources can be increased for an under-utilized processing stage, such as by increasing the number of processing threads or processing instances provided for the under-utilized processing stage).
However, Liao teaches: measuring, in real time, a level of utilization of an inter-stage buffer (par. 0034 The FIFO buffers corresponding to the multiple processing stages are polled to determine their utilization levels in block 242).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Vohra by incorporating the technique of determining utilization levels of FIFO buffers of corresponding processing stages as set forth by Liao because it would provide optimizing the utilization of memory resources while improving performance of such data processing system.
Vohra and Liao do not expressly teach: … deallocating one or more compute resources from the first stage and releasing the one or more deallocated compute resources to a pool of available resources, wherein the one or more deallocated compute resources are at least in part reallocated to a third stage, the third stage being of the first data pipeline or of a second data pipeline, and wherein processing in the third stage is performed based at least in part on the one or more reallocated resources.
However, Nagarajan teaches: deallocating one or more compute resources from the first stage and releasing the one or more deallocated compute resources to a pool of available resources, wherein the one or more deallocated compute resources are at least in part reallocated to a third stage, the third stage being of the first data pipeline or of a second data pipeline, and wherein processing in the third stage is performed based at least in part on the one or more reallocated resources (par. 0053 In step 414, the storage cluster computing apparatus 12 updates the hardware resource pool 32 and the hardware allocation table 34 to release hardware resources of one or more types of hardware resources from the one of the storage virtual machines 38(1)-38(n), as described and illustrated in more detail earlier with reference to step 310 of FIG. 3 and step 408, for example. Accordingly, in iterations in which the storage cluster computing apparatus 12 determines an under-utilization is detected, the storage cluster computing apparatus 12 updates the hardware resource pool 32 to reflect the releasing of a portion of the previously allocated hardware resources for the one of the hardware resource types back to the hardware resource pool 32 from the one of the storage virtual machines … and updates the hardware allocation table 34 to deallocate the amount of hardware resources for the one of the hardware resource types from the one of the storage virtual machines; par. 0059 Over time, and based on monitoring by the storage node computing devices 14(1) and 14(2) of the hardware resource utilization of the storage virtual machines, dynamic and/or static reallocation policies are applied and the hardware resource pool 32 and hardware allocation table 34 are updated. The monitoring of the storage virtual machines 38(1)-38(4) and maintenance of the hardware resource pool 32 and hardware allocation table 34 facilitates more effective utilization of the hardware resources).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Vohra and Liao by incorporating the method of deallocation and releasing hardware resources as set forth by Nagarajan because the ability to deallocate and release overallocated resources would allow the resource to be used by other virtual machines thereby optimizing resource utilization and increasing performance of such system.
Vohra, Liao and Nagarajan do not expressly describe: wherein each of the two sequential stages including is associated with a respective container of a plurality of containers, the respective container representing a processing unit assigned to the respective stage of the data pipeline and having access to the inter-stage buffer via a file system.
However, analogous prior art, Bailey teaches: wherein each of the two sequential stages including is associated with a respective container of a plurality of containers, the respective container representing a processing unit assigned to the respective stage of the data pipeline and having access to the inter-stage buffer via a file system (par. 0056 and Fig. 2A describe virtualized execution environments executing a plurality of engines as containers, wherein for example, engine 202 is couple to an input stream1 and an output stream1 [output buffer], while engine 216 is coupled to an input stream 2 and an output stream 2 [output buffer]; further describes, par. 0282] For filestreams, it is efficient to manage container input and output by linking a directory on the host machine to the engine container).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Vohra, Liao and Nagarajan with the teaching of Bailey because they are directed pipeline data processing. This would provided for sharing the advantages of containerized environments such as the Docker ecosystem, scaling, cloud ecosystems, and flexibility (par. 0032).
As per claim 2, Vohra teaches: wherein the first stage receives data, processes or transforms the data, and transfers the processed or transformed data to the storage element, and wherein a second stage receives data from the storage element, processes or transforms the data, and transfers the processed or transformed data to another storage element or to a resource manager (col. 9, lines 21-24 The processing stages 206a-n may be arranged in one or more sequential orders such that later processing stage performs processing based upon a result of processing from an earlier stage; col.7, lines 6-9 memory 128 of the service provider system 104 may also include one or more queues, including input queues to receive requests for processing and output queues providing results of processed requests; col. 9, lines 24-33: “An asynchronous communication channel 265 may be utilized to control, direct, synchronize the flow of events or requests through the plurality of processing stages 206 a-n. In this regard, the asynchronous communication channel 265 may provide a respective request queue for each processing stage. As such, a processing stage 206 a-n can retrieve the next transaction request or event for processing from its request queue, and deliver its result of processing the request to the request queue of the next processing stage 206 a-n).
As per claim 4, Vohra teaches: wherein the signal indicates to increase the amount of compute resources allocated to the first stage when the utilization of the storage element exceeds the first threshold, and the signal indicates to decrease the amount of compute resources allocated to the first stage when the utilization of the storage element does not exceed the second threshold (col. 4, lines 7-16, For example, the processing power or allocation of hardware resources can be decreased for an under-utilized processing stage, such as by reducing the number of processing threads or processing instances provided for the under-utilized processing stage. On the other hand, the processing power or allocation of hardware resources can be increased for an under-utilized processing stage, such as by increasing the number of processing threads or processing instances provided for the under-utilized processing stage).
As per claim 6, Vohra teaches: wherein the first stage comprises a process or task included in at least one of: an application, a cloud instance, a container, and a virtual machine (Fig. 2, discloses processing stages comprising processes included in processing computer 105; col. 9, Lines 4-6: “Due to network connectivity, various methodologies as described herein may be practiced in the context of distributed computing environments (i.e., cloud instances).
As per claim 7, Vohra teaches: wherein the storage element comprises at least one of: a buffer, computer file, database, file system, memory block, memory device, optical media, storage device, and virtual storage (col. 6, lines 47-67 and Fig. 1C, describes a processing computer that includes … at least one memory 128; col. 15, lines 31-35, It will be appreciated that each of the memories and data storage devices described herein can store data and information for subsequent retrieval. The memories and databases can be in communication with each other and/or other databases, such as a centralized database, or other types of data storage devices).
As per claim 8, Vohra further teaches wherein the compute resources comprise at least one of: a cloud instance parameter, central processing unit (CPU) cycle, graphics processing unit (GPU) cycle, CPU or GPU processing priority, memory or storage access or allotment, network bandwidth, and network traffic priority (col. 6, lines 47-67 and Fig. 1C, describes a processing computer that includes a Core Processing Unit 127 having one or more processors 126, and at least one memory 128).
As per claim 9, it is a method having similar limitations as claim 1. Thus, claim 9 is rejected for the same rationale as applied to claim 1.
As per claim 10, it is a method having similar limitations as claim 2. Thus, claim 10 is rejected for the same rationale as applied to claim 2.
As per claim 12, it is a method having similar limitations as claim 4. Thus, claim 12 is rejected for the same rationale as applied to claim 4.
As per claim 14, it is a method having similar limitations as claim 6. Thus, claim 14 is rejected for the same rationale as applied to claim 6.
As per claim 15, it is a method having similar limitations as claim 7. Thus, claim 15 is rejected for the same rationale as applied to claim 7.
As per claim 16, it is a method having similar limitations as claim 8. Thus, claim 16 is rejected for the same rationale as applied to claim 8.
As per claim 17, it is a computer-readable storage medium having similar limitations as claim 1. Thus, claim 16 is rejected for the same rationale as applied to claim 1.
As per clam 18, Nagarajan further teaches: wherein the operation further comprises: upon determining to increase the amount of compute resources allocated to the first stage, determining that a pool of available resources does not include any compute resources available to allocate to the first stage; deallocating compute resources from a second stage of the data pipeline and releasing the deallocated compute resources from the second stage to the pool; and reallocating the compute resources in the pool to the first stage (par. 0044 In step 402, the storage cluster computing apparatus 12 determines whether a maximum threshold level of hardware utilization has been exceeded for at least one type of hardware resource for one of the storage virtual machines; par. 0048 In step 406, the storage cluster computing apparatus 12 determines whether sufficient hardware resources are available in the hardware resource pool 32 for allocation to the one of the storage virtual machines; par. 0053 In step 414, the storage cluster computing apparatus 12 updates the hardware resource pool 32 and the hardware allocation table 34 to release hardware resources of one or more types of hardware resources from the one of the storage virtual machines. [after 2nd loop] par. 0050 if the storage cluster computing apparatus 12 determines that sufficient hardware resources are available in the hardware resource pool 32 for allocation to the one of the storage virtual machines … In step 408, the storage cluster computing apparatus 12 updates the hardware resource pool 32 and the hardware allocation table 34 to allocate additional hardware resources of one or more types of hardware resources to the one of the storage virtual machines).
As per claim 21, Vohra further teaches wherein the amount of compute resources is adjusted in order to reduce an incidence of the data pipeline having reduced throughput due to one or more earlier stages of the plurality of stages constituting a processing bottleneck for one or more later stages in the plurality of stages (col. 1, lines 16-21 Due to different processing requirements of various stages, which may change over time, there may be mismatches in processing capabilities or throughput across the various stages. As such, the "weak link" phenomenon kicks in, and the throughput of the entire system can fall to the throughput of the slowest stage; col. 1, lines 50-53 By increasing the processing power by allocating more processing threads to a slower processing stage, or by creating more instances of the slower processing stage, the system throughput may be increased).
Claims 5, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Vohra in view of Liao, Nagarajan and Bailey as applied to claims 1, 9 and 17, and further in view of Mulchandani et al. (U.S. Pub. No. 20160357961 A1).
Mulchandani was cited in a previous Office Action.
As per claim 5, Vohra, Liao, Nagarajan and Bailey teach the limitations of claim 1. Vohra, Liao, Nagarajan and Bailey do not expressly teach: determine that the signal includes a ranking or indication of priority associated with the first stage; receive a predefined amount of signals; and upon receiving the signals, adjust, based on the ranking or indication of priority, one or more amounts of compute resources allocated to stages associated with the signals.
However, Mulchandani teaches: determine that the signal includes a ranking or indication of priority associated with the first stage; receive a predefined amount of signals; and upon receiving the signals, adjust, based on the ranking or indication of priority, one or more amounts of compute resources allocated to stages associated with the signals. (par. 0040 The resource allocation prioritizer 120 may determine the resource allocation priority based on ranking the processes by risk score, and then determining the priority for allocation resources to the processes based on the ranking of the processes. For example, the resource allocation prioritizer 120 may rank “Process A” with a 0% risk score higher than “Process B” with a 10% risk score, and accordingly, determine “Process A” should have a higher priority for resource allocation than “Process B.”).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed inventio to modify the teaching of Vohra, Liao, Nagarajan and Bailey by incorporating the method of allocation of resources to processes as set forth by Mulchandani because it would provide for allocating resources to processing stages based on obtained rankings for the processing stages so as to ensure that data gets to the relatively important intermediate stages more quickly. This would have resulted in increasing the throughput of such system.
As per claim 13, it is a method having similar limitations as claim 5. Thus, claim 13 is rejected for the same rationale as applied to claim 5.
As per claim 20, it is a computer-readable storage medium having similar limitations as claim 5. Thus, claim 20 is rejected for the same rationale as applied to claim 5.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Vohra in view of Liao, Nagarajan and Bailey as applied to claims 1, 9 and 17, and further in view of Honjo et al. (U.S. Pub. No 20210092319 A1).
Honjo was cited in a previous office action.
As per claim 22, Vohra further teaches: wherein the first stage receives data, processes or transforms the data, and transfers the processed or transformed data to the inter-stage buffer, and wherein a second stage receives data from the inter-stage buffer, processes or transforms the data (col. 9, lines 21-24 The processing stages 206a-n may be arranged in one or more sequential orders such that later processing stage performs processing based upon a result of processing from an earlier stage; col.7, lines 6-9 memory 128 of the service provider system 104 may also include one or more queues, including input queues to receive requests for processing and output queues providing results of processed requests; col. 7, lines 37-39 monitoring & resource allocation module 141 may decrease the processing power or allocation of hardware resources for an under-utilized processing stage);
Vohra, Liao, Nagarajan and Bailey do not expressly describe: and transfers the processed or transformed data to the resource manager.
However, Honjo teaches: and transfers the processed or transformed data to the resource manager (par. 0024 … image received from the image processing unit 202 and has undergone processing … will be transferred to the distribution unit .... In addition, data of the processing result will be transferred to, for example, the distribution unit 204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Vohra, Liao, Nagarajan and Bailey by incorporating the feature of transferring processing data to a distribution unit as set forth by Honjo because providing the function for transferring processed data and results to management module such as the “resource allocation unit” would facilitate for adjusting resource amounts allocated to processing nodes, thereby optimized the utilize the utilization of resources and improve performance of such system.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Vohra in view Liao, Nagarajan and Bailey, and further in view of Kwon al. (U.S. Pub. No. 20190158892 A1).
Kwon was cited in a previous office action.
As per claim 23, Vohra further teaches: wherein the computer program code is of a program (col. 15, lines 6-7 a computer-readable program code or program instructions embodied therein), the program comprising a storage element monitor (col. 7, lines 37-39 monitoring & resource allocation), wherein each stage comprises a respective process … wherein each storage element comprises a respective buffer, and … wherein the signal indicates to increase the amount of compute resources allocated to the first stage when the utilization of the storage element exceeds the first threshold, and wherein the signal indicates to decrease the amount of compute resources allocated to the first stage when the utilization of the storage element does not exceed the second threshold, wherein the level of utilization is measured via the operating system (col. 4, lines 4-16, To provide for auto-balancing of the throughput … allocations of hardware resources can be adjusted for under-utilized or over-utilized processing stages. For example, the processing power or allocation of hardware resources can be decreased for an under-utilized processing stage, such as by reducing the number of processing threads or processing instances provided for the under-utilized processing stage. On the other hand, the processing power or allocation of hardware resources can be increased for an under-utilized processing stage. That is, is reducing the number of threads/instances reduces amount of processor/memory. Similarly increasing the number of threads increases amount of processor/memory resources).
Nagarajan further teaches: wherein each stage comprises a respective process included in a respective virtual machine, wherein adjusting the amount of compute resources comprises adjusting the amount of compute resources allocated to the virtual machine that the process … is included in (par. 0053 Accordingly, in iterations in which the storage cluster computing apparatus 12 determines an under-utilization is detected, the storage cluster computing apparatus 12 updates the hardware resource pool 32 to reflect the releasing of a portion of the previously allocated hardware resources for the one of the hardware resource types back to the hardware resource pool 32 from the one of the storage virtual machines).
wherein the program is included in a memory of a computer, … (col. 14, lines 64-65 These computer program instructions may also be stored in a computer-readable memory).
Bailey further teaches: wherein the memory includes an operating system and a container runtime engine, wherein the container runtime engine is configured to execute a respective library in each container, wherein the one or more computer processors are of the computer, wherein access to the file system is shared by the plurality of containers, and wherein the operation further comprises, by the resource manager (par. 0080 A containerized engine (276) is used to provide the operating-system level virtualization of each container; par. 0042 Dynamic configuration of an engine includes changing a stream, an analytic model, an included library, and/or a cloud execution environment; par. 0081 Similarly, a core filesystem stack (282) may be used and other core packages, libraries, and/or dependencies (284) may be installed in the host OS).
Vohra, Liao, Nagarajan and Bailey do not expressly disclose: wherein the compute resources comprise a cycle selected from a central processing unit (CPU) cycle and a graphics processing unit (GPU) cycle.
However, Kwon teaches: wherein the compute resources comprise a cycle selected from a central processing unit (CPU) cycle and a graphics processing unit (GPU) cycle (par. 0049 having the capability to dynamically select which hardware resources (e.g., CPU 140 or GPU 142) to utilize for processing application data).
It would have been obvious to one of ordinary skill in the art to modify the teaching of Vohra, Liao, Nagarajan and Bailey to incorporate the technique selecting resources from one of CPU and GPU cycles as set forth by Kwon because it would provide for selecting between faster and slow processing units so as to enhance the performance a processing stage.
Response to Arguments
Applicant's arguments with respect to claims 1, 9 and 17 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Pub. No. 20210132600 A1 automating construction and deployment of predictive models for industrial plant assets.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Willy W. Huaracha whose telephone number is (571)270-5510. The examiner can normally be reached on M-F 8:30-5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee Li can be reached on (571) 272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WH/
Examiner, Art Unit 2195
/BING ZHAO/Primary Examiner, Art Unit 2151
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