DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The following is a Final Office Action in response to communications received January 30, 2026. Claim(s) 6, 20 and 34 have been canceled. No Claims have been amended. No new claims have been added. Therefore, claims 1-5, 7-19, 21-33 and 35-42 are pending and addressed below.
Priority
Application No. 17109714 filed 12/02/2020 and having 1 RCE-type filing therein is a Continuation of 14134828 , filed 12/19/2013 ,now U.S. Patent # 10885583
Applicant Name/Assignee: Chicago Mercantile Exchange Inc.
Inventor(s): Bonig, Zachary; Zheng, Haifeng; Mendelson, Don; Donaghy, Mike; Lin, Akrapong
Response to Amendment/Arguments
Claim Rejections - 35 USC § 103
Applicant's arguments filed 01/30/2026 have been fully considered but they are not persuasive.
In the remarks applicant argues the prior art references fail to teach “storing, by the processor upon receipt of all of the received electronic message packets comprising a complete message of the plurality of messages, at least the message data thereof in an available position in a single data buffer comprising a plurality of positions in which message data may be stored in an order based on position availability and in which the message data of all received electronic message packets are stored together by the processor irrespective of which message source each of the received electronic message packets was received from, determining when the message data of a complete message has been received, and storing, in an order buffer separate from the data buffer, data indicative of an order of receipt of the complete message of each received electronic message packet which may be different from a time at which the electronic message packet was received, with respect to other received complete messages, associated with the position in which that message data was stored in the data buffer" Applicant further argues that the prior art Kragh teaches separate FIFO queues, as each analyzer may store a time stamped packet in any of the queues and each queue may contain a mix of data packets from any of the analyzers with no guarantee that any one queue will hold the received data packets in the order of the receipt by the system with respect to other queues. Applicant argues that because Kragh uses multiple queue/buffers and teaches that no data can be dequeued form one queue unless there is data present in all queues, dummy data is required to be inserted in empty queues to prevent line blocking, preventing data from being dequeued form any queue when a queue is empty. Accordingly the prior art does not teach data together in a single queue or storing all received electronic messages comprising a complete message in available position where all message data of all message packets are stored together irrespective of which message source of each received message packets. Applicant argues the prior art fails to teach data indicative of order of receipt of complete message of each received message packet may be different from a time at which the message packet was received with respect to other complete messages associated with the position in which the message data is stored. Applicant’s argument is not persuasive. A buffer can contain a plurality of queues and still be a single buffer. The prior art Kragh teaches with respect to the limitation “storing, by the processor upon receipt of all of the received electronic message packets comprising a complete message of the plurality of messages, at least the message data thereof in an available position in a single data buffer comprising a plurality of positions in which message data may be stored in an order based on position availability and in which the message data of all received electronic message packets are stored together by the processor irrespective of which message source each of the received electronic message packets was received from”… “storing, in an order buffer separate from the data buffer, data indicative of an order of receipt of the complete message of each received electronic message packet which may be different from a time at which the electronic message packet was received, with respect to other received complete messages, associated with the position in which that message data was stored in the data buffer” in para 0002 the prior art teaches receiving data packet and providing a time stamp the receiving encompassing plurality of input queues where the packet is dequeued at output storage position of an input queue of all input queues, 0009 wherein the prior art teaches data packets sequence of data packets transmitted as a single file where the stream of data packet is identified by stream identifying information and the data packet information determining the order such as sequence number of time stamp used for ordering of packets, 0013-0017 wherein the prior art teaches input queues provided where the output queue represents number of data having an order implemented having a number of storage positions along linear order from an input end to output end the storage has separately addressable elements and a number of such elements may form a queue, the storing unit being monolithic and teaches that the data items are not necessarily moved but points are moved where the storing may comprise forwarding/deriving an address of storage where the position of data are maintained irrespective of implementation, 0021-0022 wherein the prior art teaches dequeuing not position dependent but rather time dependent, 0024-0027 wherein the prior art teaches a process to prevent blocking because of empty queue by providing a dummy packet and in the dequeuing process the dummy and data packets are treated equally and teaches a receiving mean ensuring all earlier packets are represented in the queues. . The prior art further teaches para 0049 that the data packets received are provided a time stamp and inputted into a plurality of input queues (any available queue position) each having an output storage position, and teaches para 0078 the individual queues form when data packets are outputted a single memory formed both queues of a pair where the pointers are used for describing storage locations of the packets. The prior art teaches para 0038 wherein the prior art teaches plurality of output queues having an output end storage position to forward data for dequeues, para 0054 wherein the prior art teaches receiving plurality of data packets and providing a time stamp for each received data packet ensuring that data packets from multiple receiving means to the same input queue are forwarded in correct order, para 0056 teaches dequeuing by forwarding data packets de-queued to output queues each having an output end/storage position and generate dummy packets forwarded to output queues not having received packets for predetermined period of time the dequeuing deriving time stamp form de-queued data packet providing the dummy packet with the derived time stamp and forwarding the dummy packet to an output queue to which no de-queued packets have been forwarded, para 0078 wherein the prior art teaches where pairs of an input and output queue are formed a single memory maybe used to form both queues of pairs and pointers used for describing which packets are in the output queue and which storage locations are empty. Please note the input and output queues are separate storage buffers and thus provide teaching of the limitation “order buffer separate from the data buffer”. The dummy packets of the prior art inserted in empty queues does not conflict with the language that requires storing data indicative of order of receipt of the complement message where each received packet may be different from a time at which data is received as the dummy data packets are derived and not received and merely applied as a tool to allow smooth data de-queuing. As the prior art Kragh explicitly teaches the queues stored in a single file and teaches a “monolithic” storing unit containing the queues, the prior art teaches the limitations single data buffer. Although the prior art does not use the language “complete message” the prior art teaching “ensuring all earlier packets are represented in the queues” suggest the data packets are dequeued in their entirety. In combination with Kragh, the prior art McWilliams teach clearly the limitation “determining when the message data of the a complete message has been received. The prior art McWillaims teaches the limitations “storing, by the processor upon receipt of all of the received electronic message packets comprising a complete message of the plurality of messages, at least the message data thereof in an available position in a single data buffer comprising a plurality of positions in which message data may be stored in an order based on position availability and in which message data of all received electronic messages packets are stored together by the processor irrespective of which message source each of the received electronic message packets was received from, determining when the message data of a complete message has been received, and storing, in an order buffer separate from the data buffer, data indicative of an order receipt of the complete message of each received electronic message packet which may be different from a time at which the electronic message packet was received, with respect to other received complete messages_associated with the position in which that message data was stored in the data buffer” Specifically, McWilliams teaches in at least para 0194 wherein the prior art teaches a buffer as a whole with individual queues, para 0239-0240 wherein the prior art teaches message can be assembled in any order and read back then transmitted to send buffer and teaches message received and stored in buffer where buffer read/write message in any order and the contents of the buffer are transmitted when they are successfully transmitted; para 0453 wherein the prior art teaches the processor polls the transmission and determines transmission completed, para 01079 wherein the prior art teaches processor writes to registers until transmission is completed, 1083-1084 wherein the prior art teaches detecting message bytes from incoming data stream and teaches determining by the receiver that it has received entire message and sets the receive buffer full to prevent buffer being updated so that message cannot be overwritten. Accordingly, the combination teaches the limitation argued.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5 and 7-8; Claims 15-19 and 21-22; Claim(s) 29-33 and 35-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2012/093056 A1 by Kragh et al (Kragh), in view of US Pub No. 2002/0031132 A1 by McWilliams (McWilliams) and further in view of DE 102008034006 A1 by Lin et al (Lin) the translation herein as annotated by the examiner
In reference to Claim 1:
Kragh teaches:
(Previously Presented) A computer implemented method ((Kragh) in at least para 0004-0005) comprising:
receiving, by a network interface [receiving means] of a processor coupled with a network, a plurality of electronic message packets comprising a plurality of messages, a portion of which are communicated thereto from a first message source via the network and another portion of which are communicated thereto from a second message source, different from the first message source, via the network, wherein each of the plurality of electronic message packet comprises message data indicative of at least a portion of at least one of the plurality of messages ((Kragh) in at least Abstract; para 0001-0002, para 0004-0005, para 0010-0011, para 0013, para 0049, para 0060-0061, para 0064); and
storing, by the processor upon receipt of all of the received electronic message packets comprising a complete message of the plurality of messages, at least the message data thereof in an available position in a single data buffer [monolithic storing unit] comprising a plurality of positions in which message data may be stored in an order based on position availability and in which the message data of all received electronic message packets are stored together by the processor irrespective of which message source each of the received electronic message packets was received from,… ((Kragh) in at least para 0002, para 0004 wherein the prior art teaches data transfer through bluetooth, para 0009 wherein the prior art teaches identifying datapackets addresses or identifying information used to determine order of packets; para 0013-0017 wherein the prior art teaches data packets may be added to any type of storage, para 0014 wherein the prior art teaches FIFO implemented in a storage having a number of storage positions which may be monolithic where data items are not moved by pointers are moved, para 0014 wherein the prior art teaches the queue or all queues stored in circular buffers, para 0017 wherein the prior art teaches data packets may be added to any type of storage; para 0021-0022, para 0024-0027 wherein the prior art teaches if queue empty generating dummy packet to a queue to which no packets have been transmitted and adding and dequeuing dummy packet to a queue and dummy packet may be added other data; para 0033 wherein the prior art teaches receiving means that is least para 0049, para 0078), and storing, in an order buffer separate from the data buffer, data indicative of an order of receipt of the … message of each received electronic message packet which may be different from a time at which electronic message packet was received, with respect to other received …messages, associated with the position in which that message data was stored in the data buffer ((Kragh) in at least para 0021 wherein the prior art teaches de-queue data packet removing data packet which was received at earliest time stamp, para 0038, para 0042-0043 wherein the prior art teaches de-queuing data packets from input queue to output queue derived from time stamp, para 0047 where the prior art teaches outputting packets identical to input queues, para 0054 wherein the prior art teaches determination of fact that input queue has not received a data packet for determined period of time, para 0056, para 0064, para 0068, para 0074 wherein the prior art teaches data may be de-queued from output buffers, para 0078 wherein the prior art teaches queues formed in any suitable manner where input and output queue are formed a single memory may be used to form queues of pairs (input/output), ); and
enabling retrieval [dequeuing], by an application, of the stored message data from each of the positions of the data buffer, based on the stored data indicative of the order of receipt in the order buffer, such that the application retrieves each of the stored …messages in the order of receipt by the processor regardless of the order in which the message data is stored in the data buffer. ((Kragh) in at least Abstract; para 0013, para 0027, para 0038, para 0049, para 0052, para 0056, para 0064-0066, para 0072, para 0074, para 0076) .
Kragh suggest but does not explicitly teach:
receiving, by a network interface…messages…((Kragh) in at least para 0004, para 0050 wherein the prior art teaches receiving step receiving data packets form a data cable using bluetooth communication)
…an available position in a single data buffer…((Kragh) in at least para 0014 wherein the prior art teaches storage may be monolithic storing unit; para 0017 wherein the prior art teaches data packets may be added to any type of storage)
Although Kragh does not explicitly teach an interface, the prior art does teach a communication means for receiving data in a computer environment and teaches Bluetooth protocol as a communication element. Bluetooth protocol inherently requires a wireless interface in order to communicate. Additionally, communication means suggest that the elements for communication can be any communication means known to the public. Accordingly, the prior art provides some teaching that would have led one of ordinary skill in the art to arrive at the claimed limitation.
Kragh does not explicitly teach:
...stored such that the application receives each of the stored message data... determining when the message data of a complete message has been received… order of receipt of the complete message of each received electronic message packet…
Lin teaches:
storing, by the processor upon receipt of all of the received electronic message packets comprising a … message of the plurality of messages, at least the message data thereof in an available position in a single data buffer comprising a plurality of positions in which message data may be stored in an order based on position availability and in which message data of all received electronic messages packets are stored together by the processor irrespective of which message source each of the received electronic message packets was received from, determining when the message data of a complete message has been received, and storing, in an order buffer separate from the data buffer, data indicative of an order receipt of the … message of each received electronic message packet which may be different from a time at which the electronic message packet was received, with respect to other received …messages associated with the position in which that message data was stored in the data buffer (Lin) in at least Abstract wherein the prior art teaches processing unit has at least one data buffer the one data buffer has at least one logical input buffer and at least one logical output buffer; para 0007-0009, para 0046-0047, para 0049-0050, para 0066, para 0081, para 0084, para 0092, para 0099, para 0102 wherein the prior art teaches data movement controller directs data to specified address and after transmission is complete )
storing, in an order buffer separate from the data buffer, data indicative of an order of receipt of each received electronic message packet … ((Lin) in at least para 0012, para 0014, para 0016, para 0029, para 0031-0033, para 0043, para 0046-0048, para 0078, para 0081, para 0084, para 0092, para 0099-0100, para 0102)
Both Kragh and Lin are directed toward receiving FIFO data packets by a communication into a first input buffer where the data is then transferred to an output buffer. Lin teaches the motivation that the buffer receiving the FIFO can be at least one input buffer. Although Lin does not limit the input buffer to more than one input buffer as a possible option, the prior art makes clear that one buffer (a single input buffer) can be the architecture for receiving FIFO messages. According to KSR, known work in one field of endeavor may prompt variations of it for use in the same field if the variations are predictable to one of ordinary skill in the art and if the prior art itself provides some teaching that would have led one of ordinary skill in the art to arrive at the claimed “single buffer”. Furthermore, the prior art Lin provides a finite number of predictable solutions as to the FIFO messages being received by a single buffer. According to KSR common sense rationale when there is a choice of a finite number of identified solutions, to a recognized need one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success. Especially, when the prior art itself provide teaching and suggestion that would have led one of ordinary skill in the art to modify the “any type of storage” in a monolithic memory to be a one input buffer logic (receiving single buffer memory) as taught by Lin with a reasonable expectation of success.
McWilliams teaches:
receiving, by a network interface…messages…((McWilliams) in at least para 0026),
storing, by the processor upon receipt of all of the received electronic message packets comprising a complete message of the plurality of messages, at least the message data thereof in an available position in a single data buffer comprising a plurality of positions in which message data may be stored in an order based on position availability and in which message data of all received electronic messages packets are stored together by the processor irrespective of which message source each of the received electronic message packets was received from, determining when the message data of a complete message has been received, and storing, in an order buffer separate from the data buffer, data indicative of an order receipt of the complete message of each received electronic message packet which may be different from a time at which the electronic message packet was received, with respect to other received complete messages associated with the position in which that message data was stored in the data buffer ((McWilliams) in at least para 0194, para 0239-0240 wherein the prior art teaches message can be assembled in any order and read back then transmitted to send buffer and teaches message received and stored in buffer where buffer read/write message in any order; para 0248 wherein the prior art teaches port receives traffic at any one time; para 0453 wherein the prior art teaches processor polls and determines transmission completed, para 01079, para 1083-1084);
enabling retrieval, by an application, of the stored message data from each of the positions of the data buffer, based on the stored data indicative of the order of receipt in the order buffer, such that the application retrieves each of the stored complete messages in the order of receipt by the processor regardless of the order in which the message data is stored in the data buffer ((McWilliams) in at least para 0028-0029, para 0162, para 0453, para 0842-0843, para 0849, para 0856)
Both Kragh and McWilliams are directed toward communication in a computer environment receiving FIFO data packets by a communication means. McWilliams teaches the motivation of an application interface circuit for FIFO reception in a communication circuit where the received messages is determined when transmission is completed in order to determine at which time the process can be transmitted from another cell and in order to determine queue size. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the high level communication means for receiving FIFO messages of Kragh to include an application interface as taught by McWilliams since McWilliams teaches the motivation of an application interface circuit for FIFO reception in a communication circuit where the received messages is determined when transmission is completed in order to determine at which time the process can be transmitted from another cell and in order to determine queue size. .
In reference to Claim 2:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 1. Kragh further discloses the limitations of dependent claim 2
(Original) The computer implemented method of claim 1 (see rejection of claim 1 above),
wherein each of the plurality of electronic message packets comprise a format for transmission using Transmission Control Protocol (“TCP”) which organizes received electronic message packets based on origin.((Kragh) in at least para 0007-0008)
In reference to Claim 3:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 1. Kragh further discloses the limitations of dependent claim 3
(Previously Presented) The computer implemented method of claim 1 (see rejection of claim 1 above),
wherein the processor is comprised by the network ...through which each of the plurality of electronic message packets must pass for the message data thereof to reach the application.((Kragh) in at least para 0007, para 0009)
Kragh does not explicitly teach:
...interface...
McWilliams teaches:
...interface...((McWilliams) in at least para 0309)
Both Kragh and McWilliams are directed toward FIFO data transmission. McWilliams teaches the motivation of a interface for transmitting and receiving cells of the data. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the generic communication FIFO data network transmission of Kragh to include a interface as taught by McWilliams since McWilliams teaches the motivation of a interface for transmitting and receiving cells of the data.
In reference to Claim 4:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 1. Kragh further discloses the limitations of dependent claim 4.
(Previously Presented) The computer implemented method of claim 1 (see rejection of claim 1 above),
wherein the order of receipt of the message data of all received electronic message packets, is indicated by a location in the order buffer... [queue] in which each of the data indicative of the order of receipt is stored.((Kragh) in at least para 0009, para 0014, para 0016, para 0021 wherein the prior art teaches de-queue data packet removing data packet which was received at earliest time stamp, para 0038, para 0042-0043 wherein the prior art teaches de-queuing data packets from input queue to output queue derived from time stamp, para 0056, para 0064, para 0068, para 0074 wherein the prior art teaches data may be de-queued from output buffers),
Kragh does not explicitly teach:
...buffer...
Lin teaches:
. wherein the order of receipt of the message data of all received electronic message packets, is indicated by a location in the order buffer, in which each of the data indicative of the order of receipt is stored ((Lin) in at least Abstract; para 0004, para 0006-0009, para 0016, para 0022-0023, para 0029, para 0049, para 0066, para 0084, para 0092)
Both Kragh and Lin are directed toward storing FIFO data transmission data. Kragh teaches that any memory can be used for such processes. Lin teaches the motivation of buffer memory in order to contain data frame used to input data received for storage. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the generic any memory of Kragh to include buffer memory as taught by Lin since Lin teaches the motivation of buffer memory in order to contain data frame used to input data received for storage.
In reference to Claim 5:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 1. Kragh further discloses the limitations of dependent claim 5.
(Previously Presented) The computer implemented method of claim 1 (see rejection of claim 1 above),
wherein the data indicative of the order of receipt comprises data indicative of when each of the received electronic message packets was received by the processor, ((Kragh) in at least para 0014, para 0016-0017)
In reference to Claim 7:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 1. Kragh further discloses the limitations of dependent claim 7.
(Previously Presented) The computer implemented method of claim 1 (see rejection of claim 1 above), wherein the storing further comprises
the data indicative of the order of receipt thereof stored in the order buffer is based on the last of the received electronic message [data] packets comprising the …message to be received. ((Kragh) in at least para 0002, para 0004, para 0013-0014, para 0016-0017, para 0021-0022 wherein the prior art teaches de-queue data packet removing data packet which was received at earliest time stamp, para 0038, para 0042-0043 wherein the prior art teaches de-queuing data packets from input queue to output queue derived from time stamp, para 0049, para 0056, para 0064, para 0068, para 0074 wherein the prior art teaches data may be de-queued from output buffers)
Kragh does not explicitly teach:
...complete message...
McWilliams teaches:
…received electronic message packets comprising the complete message to be received ((McWilliams) in at least para 0194, para 0239-0240 wherein the prior art teaches message can be assembled in any order and read back then transmitted to send buffer and teaches message received and stored in buffer where buffer read/write message in any order; para 0248 wherein the prior art teaches port receives traffic at any one time; para 0453 wherein the prior art teaches processor polls and determines transmission completed, para 01079, para 1083-1084);
Both Kragh and McWilliams are directed toward communication in a computer environment receiving FIFO data packets by a communication means. McWilliams teaches the motivation of an application interface circuit for FIFO reception in a communication circuit where the received messages is determined when transmission is completed in order to determine at which time the process can be transmitted from another cell and in order to determine queue size. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the high level communication means for receiving FIFO messages of Kragh to include an application interface as taught by McWilliams since McWilliams teaches the motivation of an application interface circuit for FIFO reception in a communication circuit where the received messages is determined when transmission is completed in order to determine at which time the process can be transmitted from another cell and in order to determine queue size.
In reference to Claim 8:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 1. Kragh further discloses the limitations of dependent claim 8.
(Previously Presented) The computer implemented method of claim 1 (see rejection of claim 1 above), wherein
the data indicative of the order of receipt stored in the order buffer based on the first of the received electronic message [data] packets comprising the [data] to be retrieved ((Kragh) in at least para 0002, para 0004, para 0013-0014, para 0016-0017, para 0020-0021 wherein the prior art teaches de-queue data packet removing data packet which was received at earliest time stamp, para 0038, para 0042-0043 wherein the prior art teaches de-queuing data packets from input queue to output queue derived from time stamp, para 0049, para 0056, para 0064, para 0068, para 0074 wherein the prior art teaches data may be de-queued from output buffers).
McWilliams teaches:
…received electronic message packets comprising the complete message to be received ((McWilliams) in at least para 0194, para 0239-0240 wherein the prior art teaches message can be assembled in any order and read back then transmitted to send buffer and teaches message received and stored in buffer where buffer read/write message in any order; para 0248 wherein the prior art teaches port receives traffic at any one time; para 0453 wherein the prior art teaches processor polls and determines transmission completed, para 01079, para 1083-1084);
Both Kragh and McWilliams are directed toward communication in a computer environment receiving FIFO data packets by a communication means. McWilliams teaches the motivation of an application interface circuit for FIFO reception in a communication circuit where the received messages is determined when transmission is completed in order to determine at which time the process can be transmitted from another cell and in order to determine queue size. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the high level communication means for receiving FIFO messages of Kragh to include an application interface as taught by McWilliams since McWilliams teaches the motivation of an application interface circuit for FIFO reception in a communication circuit where the received messages is determined when transmission is completed in order to determine at which time the process can be transmitted from another cell and in order to determine queue size.
In reference to Claim 15:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 15.
The system functions of claim 15 correspond to the method steps of method claim 1. The additional limitations recited in claim 15 that go beyond the limitations of claim 1 include system include the structure comprising:
a first logic stored in a memory and configured to be executed by a processor coupled to a network to cause the processor to perform the operation that correspond to claim 1 ((Kragh) in at least para 0004, para 0014, para 0052, para 0078-0079);
a second logic stored in a memory and configured to be executed by the processor to perform the operation that correspond to claim 1 ((Kragh) in at least para 0004, para 0014, para 0052, para 0078-0079); and
Lin teaches and provides supporting evidence:
a first logic stored in a memory and configured to be executed by a processor coupled with a network to cause the processor to receive, … a plurality of electronic message packets, a portion of which are communicated thereto from a first message source via the network … wherein each of the plurality of electronic message packet comprises message data …((Lin) in at least Abstract wherein the prior art teaches processing unit has at least one data buffer the one data buffer has at least one logical input buffer and at least one logical output buffer; para 0007-0009, para 0046-0047, para 0081);
a second logic stored in a memory and configured to be executed by the processor to cause the processor to store, upon receipt of each of the received electronic message packets, at least the message data of the received electronic message packet in an available position of a single data buffer, ……((Lin) in at least Abstract wherein the prior art teaches processing unit has at least one data buffer the one data buffer has at least one logical input buffer and at least one logical output buffer; para 0007-0009, para 0046-0047, para 0081), and
store, in an order buffer separate from the data buffer, data indicative of an order of receipt of each received electronic message packet which may be different from a time at which electronic message packet was received, with respect to others of the received electronic message packets, … ((Lin) in at least para 0012, para 0014, para 0016, para 0029, para 0032, para 0043, para 0046-0048, para 0078, para 0081)
Both Kragh and Lin are directed toward receiving FIFO data packets by a communication into a first input buffer where the data is then transferred to an output buffer. Lin teaches the motivation that the buffer receiving the FIFO can be at least one input buffer. Although Lin does not limit the input buffer to more than one input buffer as a possible option, the prior art makes clear that one buffer (a single input buffer) can be the architecture for receiving FIFO messages. According to KSR, known work in one field of endeavor may prompt variations of it for use in the same field if the variations are predictable to one of ordinary skill in the art and if the prior art itself provides some teaching that would have led one of ordinary skill in the art to arrive at the claimed “single buffer”. Furthermore, the prior art Lin provides a finite number of predictable solutions as to the FIFO messages being received by a single buffer. According to KSR common sense rationale when there is a choice of a finite number of identified solutions, to a recognized need one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success. Especially, when the prior art itself provide teaching and suggestion that would have led one of ordinary skill in the art to modify the “any type of storage” in a monolithic memory to be a one input buffer logic (receiving single buffer memory) as taught by Lin with a reasonable expectation of success.
Therefore, claim 15 has been analyzed and rejected as previously discussed with respect to claim 1.
In reference to Claim 16:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 15. Kragh further discloses the limitations of dependent claim 16
System claim 16 functions corresponds to the steps of method claim 2. Therefore, claim 16 has been analyzed and rejected as previously discussed with respect to claim 2
In reference to Claim 17:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 15. Kragh further discloses the limitations of dependent claim 17
System claim 17 functions corresponds to the steps of method claim 3. Therefore, claim 17 has been analyzed and rejected as previously discussed with respect to claim 3
In reference to Claim 18:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 15. Kragh further discloses the limitations of dependent claim 16
System claim 18 functions corresponds to the steps of method claim 4. Therefore, claim 18 has been analyzed and rejected as previously discussed with respect to claim 4
In reference to Claim 19:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 15. Kragh further discloses the limitations of dependent claim 19
System claim 19 functions corresponds to the steps of method claim 5. Therefore, claim 19 has been analyzed and rejected as previously discussed with respect to claim 5
In reference to Claim 21:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 15. Kragh further discloses the limitations of dependent claim 21
System claim 21 functions corresponds to the steps of method claim 7. Therefore, claim 21 has been analyzed and rejected as previously discussed with respect to claim 7.
In reference to Claim 22:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 15. Kragh further discloses the limitations of dependent claim 22
System claim 22 functions corresponds to the steps of method claim 8. Therefore, claim 22 has been analyzed and rejected as previously discussed with respect to claim 8.
In reference to Claim 29:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 29.
The system functions of claim 29 correspond to the method steps of method claim 1. The additional limitations recited in claim 29 that go beyond the limitations of claim 1 include system include the structure comprising:
at least on memory capable to store the perform the operation that correspond to claim 1 ((Kragh) in at least para 0014, para 0052, para 0078-0079);
at least one processor to perform the operation that correspond to claim 1 ((Kragh) in at least para 0004, para 0014, para 0052, para 0079)
In reference to Claim 30:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 29. Kragh further discloses the limitations of dependent claim 30
System claim 30 functions corresponds to the steps of method claim 2. Therefore, claim 30 has been analyzed and rejected as previously discussed with respect to claim 2
In reference to Claim 31:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 29. Kragh further discloses the limitations of dependent claim 31
System claim 31 functions corresponds to the steps of method claim 3. Therefore, claim 31 has been analyzed and rejected as previously discussed with respect to claim 3
In reference to Claim 32:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 29. Kragh further discloses the limitations of dependent claim 16
System claim 32 functions corresponds to the steps of method claim 4. Therefore, claim 32 has been analyzed and rejected as previously discussed with respect to claim 4
In reference to Claim 33:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 29. Kragh further discloses the limitations of dependent claim 33
System claim 33 functions corresponds to the steps of method claim 5. Therefore, claim 33 has been analyzed and rejected as previously discussed with respect to claim 5
In reference to Claim 35:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 29. Kragh further discloses the limitations of dependent claim 35
System claim 35 functions corresponds to the steps of method claim 7. Therefore, claim 35 has been analyzed and rejected as previously discussed with respect to claim 7
In reference to Claim 36:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 34. Kragh further discloses the limitations of dependent claim 36
System claim 36 functions corresponds to the steps of method claim 8. Therefore, claim 36 has been analyzed and rejected as previously discussed with respect to claim 8
Claim(s) 9-10 of claim 1, Claims 23-25 of claim 15; Claims 35-39 of claim 29 above is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2012/093056 A1 by Kragh et al (Kragh), in view of DE 102008034006 A1 by Lin et al (Lin) the translation herein as annotated by the examiner, in view of US Pub No. 2002/0031132 A1 by McWilliams (McWilliams), and further in view of US Patent No. 9,501,795 B1 by Friedman (Friedman)
In reference to Claim 9:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 1. Kragh further discloses the limitations of dependent claim 9.
(Previously Presented) The computer implemented method of claim 1 (see rejection of claim 1 above), wherein the storing further comprises
the data indicative of the order of receipt thereof stored in the order buffer is based on the last of a threshold percentage of the received plurality of electronic message packets comprising the complete message to be received.
Friedman teaches:
...message... ((Friedman) in at least Col 12 lines 18-32)
the data indicative of the order of receipt thereof stored in the order buffer is based on the last of a threshold percentage of the received plurality of electronic message packets. ((Friedman) in at least Col 17 lines 62-Col 18 lines 1-3)
Both Kragh and Friedman are directed toward receiving FIFO transmission data. Friedman teaches the motivation that in a trading environment buy/sell order related messages on FIFO basis for exchange messages that have FIFO parameters. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the data packets of Kragh to include messages as taught by Friedman since Friedman teaches the motivation that in a trading environment buy/sell order related messages on FIFO basis for exchange messages that have FIFO parameters.
Both Kragh and Friedman are directed toward receiving FIFO transmission data. Friedman teaches the motivation that in a trading environment buy/sell order related messages on FIFO basis for exchange messages that the host server receives a drop copy of order form client to perform risk check process in order to determine indications of buffer events including threshold exceed that indicate exchange specific errors. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the storing of Kragh to include risk check process of Friedman since Friedman teaches the motivation that in a trading environment buy/sell order related messages on FIFO basis for exchange messages that the host server receives a drop copy of order form client to perform risk check process in order to determine indications of buffer events including threshold exceed that indicate exchange specific errors.
McWilliams teaches:
the received plurality of electronic message packets comprising the complete message to be received ((McWilliams) in at least para 0194, para 0239-0240 wherein the prior art teaches message can be assembled in any order and read back then transmitted to send buffer and teaches message received and stored in buffer where buffer read/write message in any order; para 0248 wherein the prior art teaches port receives traffic at any one time; para 0453 wherein the prior art teaches processor polls and determines transmission completed, para 01079, para 1083-1084);
Both Kragh and McWilliams are directed toward communication in a computer environment receiving FIFO data packets by a communication means. McWilliams teaches the motivation of an application interface circuit for FIFO reception in a communication circuit where the received messages is determined when transmission is completed in order to determine at which time the process can be transmitted from another cell and in order to determine queue size. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the high level communication means for receiving FIFO messages of Kragh to include an application interface as taught by McWilliams since McWilliams teaches the motivation of an application interface circuit for FIFO reception in a communication circuit where the received messages is determined when transmission is completed in order to determine at which time the process can be transmitted from another cell and in order to determine queue size.
In reference to Claim 10:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 1. Kragh further discloses the limitations of dependent claim 10.
Claim Interpretation: A gateway is a node in a computer network that serves as an entrance to another network. A node is a processing location where data stops
for either transporting or reading. (see Article Gateway Node)
(Currently Amended) The computer implemented method of claim 1 (see rejection of claim 1 above), wherein the message data of the plurality of electronic message packets comprises
Kragh does not explicitly teach:
financial message the first and second message sources comprise market participants, and the application comprises an order entry gateway application for use with an exchange operational to match trades using the financial messages.
Friedman teaches:
financial message the first and second message sources ((Friedman) in at least Col 12 lines 18-32) comprise market participants ((Friedman in at least Col 2 lines 58-65, Col 6 lines 34-40), and the application comprises an order entry gateway [node] application for use with an exchange operational to match trades using the financial messages [directed toward intended use] ((Friedman) in at least Col 9 lines 40-44).
Both Kragh and Friedman are directed toward receiving FIFO transmission data. Friedman teaches the motivation that in a trading environment buy/sell order related messages on FIFO basis for exchange messages that have FIFO parameters. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the data packets of Kragh to include messages as taught by Friedman since Friedman teaches the motivation that in a trading environment buy/sell order related messages on FIFO basis for exchange messages that have FIFO parameters.
Both Kragh and Friedman are directed toward receiving FIFO transmission data. Friedman teaches the motivation of a network processing inspection node [gateway] in order to examine the data portion of a data packet in order to determine which order may be routed in order to reduce latency. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify architecture for receiving data packets of Kragh to include node/gateway of Friedman since Friedman teaches the motivation of a network processing inspection node [gateway] in order to examine the data portion of a data packet in order to determine which order may be routed in order to reduce latency.
In reference to Claim 23:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 15. Kragh further discloses the limitations of dependent claim 23
System claim 23 functions corresponds to the steps of method claim 9. Therefore, claim 23 has been analyzed and rejected as previously discussed with respect to claim 9.
In reference to Claim 24:
The combination of Kragh, Lin and McWilliams discloses the limitations of dependent claim 15. Kragh further discloses the limitations of dependent claim 24
System claim 24 functions corresponds to the steps of method claim 10. Therefore, claim 24 has been analyzed and rejected as previously discussed with respect to claim 10.
In reference to Claim 37:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 34. Kragh further discloses the limitations of dependent claim 37
System claim 37 functions corresponds to the steps of method claim 9. Therefore, claim 37 has been analyzed and rejected as previously discussed with respect to claim 9
In reference to Claim 38:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 29. Kragh further discloses the limitations of dependent claim 38
System claim 38 functions corresponds to the steps of method claim 10. Therefore, claim 38 has been analyzed and rejected as previously discussed with respect to claim 10
Claim(s) 12-13 of claim 1 above, Claims 26-27 of claim 15 above, Claims 40-42 of claim 29 above, is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2012/093056 A1 by Kragh et al (Kragh), in view of DE 102008034006 A1 by Lin et al (Lin) the translation herein as annotated by the examiner, in view of US Pub No. 2002/0031132 A1 by McWilliams (McWilliams), and further in view of US Pub No. 2011/0019673 A1 by Gutierrez (Gutierrez)
In reference to Claim 12:
The combination of Kragh, Lin and McWilliams discloses the limitations of dependent claim 1. Kragh further discloses the limitations of dependent claim 12.
(Original) The system of claim 1 (see rejection of claim 1 above),
Kragh does not explicitly teach:
wherein the plurality of message sources are each indicated on a list of sources, and wherein the first logic is further configured to determine whether each message of the plurality of messages originated from a source included on the list of sources.
Gutierrez teaches:
wherein the plurality of message sources are each indicated on a list of sources, and wherein the first logic is further configured to determine whether each message of the plurality of messages originated from a source included on the list of sources ((Gutierrez) in at least para 0019, para 0027-0028, para 0032, para 0035)
Both Kragh and Gutierrez are directed toward receiving FIFO transmission data from a plurality of sources. Gutierrez teaches the motivation of include/exclude source list so that the sources of messages a group of messages in order to reduce or obviates the processing of unwanted packets. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the generic teaching of messages from different sources of Kragh to include source filtering as taught by Gutierrez since Gutierrez teaches the motivation of include/exclude source list so that the sources of messages a group of messages in order to reduce or obviates the processing of unwanted packets
In reference to Claim 13:
The combination of Kragh, , Lin, McWilliams and Gutierrez discloses the limitations of dependent claim 12. Kragh further discloses the limitations of dependent claim 13.
(Previously Presented) The system of 12 (see rejection of claim 12 above),
wherein second logic is further configured to only store in the common buffer electronic message packets ... ((Kragh) in at least para 0002, para 0004, para 0013-0014, para 0016-0017, para 0021-0022, para 0049, para 0078)
Kragh does not explicitly teach:
determined to have a source indicated on the list of sources.
Gutierrez teaches
wherein second logic is further configured to only store in the common buffer electronic message packets determined to have a source indicated on the list of sources. ((Gutierrez) in at least para 0019, para 0027-0028, para 0032, para 0035, para 0143 wherein the prior art teaches the control registers may be part of the same memory including any one of the memories)
Both Kragh and Gutierrez are directed toward receiving FIFO transmission data from a plurality of sources. Gutierrez teaches the motivation of include/exclude source list so that the sources of messages a group of messages in order to reduce or obviates the processing of unwanted packets. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the generic teaching of messages from different sources of Kragh to include source filtering as taught by Gutierrez since Gutierrez teaches the motivation of include/exclude source list so that the sources of messages a group of messages in order to reduce or obviates the processing of unwanted packets
In reference to Claim 26:
The combination of Kragh, Lin and McWilliams discloses the limitations of dependent claim 15. Kragh further discloses the limitations of dependent claim 26
System claim 26 functions corresponds to the steps of method claim 11. Therefore, claim 26 has been analyzed and rejected as previously discussed with respect to claim 11.
In reference to Claim 27:
The combination of Kragh, Lin and Williams discloses the limitations of dependent claim 26. Kragh further discloses the limitations of dependent claim 27
System claim 27 functions corresponds to the steps of method claim 12. Therefore, claim 27 has been analyzed and rejected as previously discussed with respect to claim 12.
In reference to Claim 40:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 15. Kragh further discloses the limitations of dependent claim 40
System claim 40 functions corresponds to the steps of method claim 12. Therefore, claim 40 has been analyzed and rejected as previously discussed with respect to claim 12.
In reference to Claim 41:
The combination of Kragh, Lin and McWilliams discloses the limitations of dependent claim 40. Kragh further discloses the limitations of dependent claim 41
System claim 41 functions corresponds to the steps of method claim 13. Therefore, claim 41 has been analyzed and rejected as previously discussed with respect to claim 13.
Claim(s) 11 and 14 of claim 1 above, Claims 25 and 28 of claim 15 above, Claims 39 and 42 of claim 29 above, is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2012/093056 A1 by Kragh et al (Kragh), in view of DE 102008034006 A1 by Lin et al (Lin) the translation herein as annotated by the examiner, in view of US Pub No. 2002/0031132 A1 by McWilliams (McWilliams) as applied to claim 1 above, and further in view of JP 4078740 B2 herein annotated by (JP407)
In reference to Claim 11:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 1. Kragh further discloses the limitations of dependent claim 11.
(Previously Presented) The system of claim 1 (see rejection of claim 1 above),
Kragh does not explicitly teach:
wherein source information of each of the plurality of electronic message packets is maintained and provided with the organized electronic message packets for the application.
JP407 teaches:
wherein source information of each of the plurality of electronic message packets is maintained and provided with the organized electronic message packets for the application.((JP407) in at least para 0053-0054, para 0089, para 0095)
Both Kragh and JP407 are directed toward receiving FIFO transmission data from a plurality of sources. JP407 teaches the motivation of storing in the FIFO, the source node ID in the header that is read by the post reception processing unit in order to determine important message processing information. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify the generic teaching of messages from different sources of Kragh to include source information in each message packet as taught by JP407 since JP407 teaches the motivation of storing in the FIFO, the source node ID in the header that is read by the post reception processing unit in order to determine important message processing information.
In reference to Claim 14:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 1. Kragh further discloses the limitations of dependent claim 14.
(Original) The computer implemented method of claim 1 (see rejection of claim 1 above),
Kragh does not explicitly teach:
wherein the receiving and storing are handled by a network layer and the application accesses the buffer via a transport layer coupled with the network layer
JP407 teaches:
wherein the receiving and storing are handled by a network layer and the application accesses the buffer via a transport layer coupled with the network layer((JP407) in at least para 0005-0006, para 0011, para 0018, para 0021, para 0025-0026)
Both Kragh and JP407 are directed toward receiving FIFO transmission data. JP407 teaches the motivation of first and second logic handled by the link/network layer in order to control the transfer of the data packets. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify architecture for receiving data packets of Kragh to include architecture as taught by JP407 since P407 teaches the motivation of first and second logic handled by the link/network layer in order to control the transfer of the data packets.
In reference to Claim 25:
The combination of Kragh, Lin and McWilliams discloses the limitations of dependent claim 15. Kragh further discloses the limitations of dependent claim 24
System claim 25 functions corresponds to the steps of method claim 11. Therefore, claim 25 has been analyzed and rejected as previously discussed with respect to claim 11.
In reference to Claim 28:
The combination of Kragh, Lin and McWilliams discloses the limitations of dependent claim 15. Kragh further discloses the limitations of dependent claim 28.
(Previously Presented)The system of 15 (see rejection of claim 8 above),
Kragh does not explicitly teach:
wherein the first logic and the second logic are handled by a network layer, and the application accesses the common buffer via a transport layer coupled with the network layer.
JP407 teaches:
wherein the first logic and the second logic are handled by a network layer, and the application accesses the ... buffer via a transport layer coupled with the network layer.((JP407) in at least para 0005-0006, para 0011, para 0018, para 0021, para 0025-0026)
Both Kragh and JP407 are directed toward receiving FIFO transmission data. JP407 teaches the motivation of first and second logic handled by the link/network layer in order to control the transfer of the data packets. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify architecture for receiving data packets of Kragh to include architecture as taught by JP407 since P407 teaches the motivation of first and second logic handled by the link/network layer in order to control the transfer of the data packets.
In reference to Claim 39:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 29. Kragh further discloses the limitations of dependent claim 39
System claim 39 functions corresponds to the steps of method claim 11. Therefore, claim 39 has been analyzed and rejected as previously discussed with respect to claim 11
In reference to Claim 42:
The combination of Kragh, Lin and McWilliams discloses the limitations of independent claim 29. Kragh further discloses the limitations of dependent claim 42
(Original) The system of claim 29 (see rejection of claim 29 above), wherein the processor is further configured to cause the system to receive and store each of the plurality of electronic message packets...the common buffer...((Kragh) in at least para 0014, para 0078)
Kragh does not explicitly teach:
using a network layer of the system, and the application accesses the buffer via a transport layer coupled with the network layer
JP407 teaches:
using a network layer of the system, and the application accesses the buffer via a transport layer coupled with the network layer ((JP407) in at least para 0005-0006, para 0011, para 0018, para 0021, para 0025-0026)
Both Kragh and JP407 are directed toward receiving FIFO transmission data. JP407 teaches the motivation of first and second logic handled by the link/network layer in order to control the transfer of the data packets. It would have been obvious to one having ordinary skill at the time of effective filing the invention was made to modify architecture for receiving data packets of Kragh to include architecture as taught by JP407 since P407 teaches the motivation of first and second logic handled by the link/network layer in order to control the transfer of the data packets.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. DE 102006058511 A1 by Englbrecht; CN 1146248 C by Kim
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARY M GREGG/Examiner, Art Unit 3695
/CHRISTINE M Tran/Supervisory Patent Examiner, Art Unit 3695
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