Office Action Predictor
Last updated: April 17, 2026
Application No. 17/123,148

VCSEL ARRAY WITH SMALL PULSE DELAY

Non-Final OA §103
Filed
Dec 16, 2020
Examiner
HELLNER, MARK
Art Unit
3645
Tech Center
3600 — Transportation & Electronic Commerce
Assignee
Trumpf Photonic Components GMBH
OA Round
3 (Non-Final)
91%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
1339 granted / 1477 resolved
+38.7% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
38 currently pending
Career history
1515
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
42.2%
+2.2% vs TC avg
§102
29.7%
-10.3% vs TC avg
§112
13.6%
-26.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1477 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In view of the appeal brief filed on 9/18/2024, PROSECUTION IS HEREBY REOPENED. New grounds of rejection are set forth below. To avoid abandonment of the application, appellant must exercise one of the following two options: (1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or, (2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid. A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below: /YUQING XIAO/Supervisory Patent Examiner, Art Unit 3645 Information Disclosure Statement The information disclosure statement filed 9/16/2024 has been considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-9, 12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Warren (United States Patent Application Publication No. 2016/0164261) in view of Joseph (United States Patent No. 8,848,757). With respect to claim 1, Warren discloses: A Vertical Cavity Surface Emitting Laser (VCSEL) array [ taught by figure 4], the VCSEL array comprising: at least two VCSEL sub-arrays [ figure 5 shows a plurality of subarrays; also see paragraph [0009]] each of the VCSEL sub-arrays comprising a plurality of VCSELs arranged on a substrate [ taught by figures 5A and 5B; paragraph [0007]] wherein the at least two VCSEL sub-arrays are electrically contacted by a first electrical contact arrangement common to the VCSELs within a respective VCSEL sub-array, of the VCSEL sub-arrays [ figure 5A shows the cathode sub mount (525) being common to the plurality of VCSEL elements ], and a second electrical contact arrangement, wherein the second electrical contact arrangement comprises a plurality of second electrical contacts, each of the second electrical contacts contacting a respective single VCSEL within the respective VCSEL sub-array, individually, wherein each of the second electrical contacts comprises a second metal- semiconductor interface to a second semiconductor layer of an associated VCSEL of the plurality of VCSELs [ figure 5A shows the anode sub mount (530) individually driving the plurality of VCSEL elements ], wherein the second electrical contacts are arranged to electrically pump the associated VCSEL along a respective current path, of a plurality of current paths, to the first electrical contact arrangement [ read on the operation of the device wherein current flows between and anode and a cathode ], wherein the current paths between the first electrical contact arrangement common to the VCSELs within the respective VCSEL sub-array and the second electrical contacts via the plurality of VCSELs are characterized by at least one symmetry selected out of the group of rotation symmetry, mirror symmetry, and translation symmetry, and wherein the first electrical contact arrangement and the second electrical contact arrangement are arranged on the same side of the substrate [ figure 5A shows that anode and cathode sub mounts in the same side of the device]. Warren does not explicitly disclose wherein the current paths between the first electrical contact arrangement common to the VCSELs within the respective VCSEL sub-array and the second electrical contacts via the plurality of VCSELs are characterized by at least one symmetry selected out of the group of rotation symmetry, mirror symmetry, and translation symmetry. Figures 3A, 3B and 5 of Joseph teach that it was known before the effective filing date of the present application to have used electrical contacts (204 and 202) to apply current to an array of VCSELs wherein current contacts create current paths between the first electrical contact arrangement common to the VCSELs within the respective VCSEL sub-array and the second electrical contacts via the plurality of VCSELs are characterized by at least one symmetry selected out of the group of rotation symmetry, mirror symmetry, and translation symmetry. Also, paragraph [0073] of Warren states, “…One example of an illumination module 300a is described in more detail in commonly owned U.S. Pat. No. 8,848,757, issued Sep. 30, 2014, filed Mar. 31, 2011 and entitled “Multibeam Arrays of Optoelectronic Devices for High Frequency Operation.”…” Therefore, it would have been obvious for a person of ordinary skill in the art to have used the electrical contact mounting structure disclosed by Joseph in the device of Warren because Joseph taught this was a known means to apply current to an array of VCSEL; and also, that this type of contact structure was suggested as an example by Warren. Claim 14 is rejected by the combination of Warren and Joseph, as applied to claim 1. With respect to claim 2, Warren discloses: The VCSEL array according to claim 1, wherein the substrate of the at least two VCSEL sub-arrays is a common substrate [ paragraph [0073] states, “…The laser arrays 505 are fabricated on one surface of a Gallium Arsenide die 510 in a process that allows both the cathode 515 and anode 520 contacts to be made on the same surface of the die..."], and wherein the current paths between the first electrical contact arrangement of a first VCSEL sub-array, of the VCSEL sub-arrays, and the second electrical contacts via the plurality of VCSELs of the first VCSEL sub-array and the second electrical contact arrangement of the second VCSEL sub-array, of the VCSEL sub-arrays, and the second electrical contacts via the plurality of VCSELs of the second VCSEL sub -array are characterized by at least one symmetry selected out of the group of rotation symmetry, mirror symmetry, and translation symmetry [ met by using the electrical contact structure disclosed by Joseph for the reasons to combine as set forth with respect to claim 1 ]. With respect to claim 3, Warren discloses: The VCSEL array according to claim 1, wherein the first electrical contact arrangement comprises at least one first electrical contact [ met by the cathode submount (525) ], wherein the at least one first electrical contact comprises a first metal-semiconductor interface to a first semiconductor layer of the VCSEL array [ the cathode submount (525) is a metal ], and wherein the current paths are defined between the first metal-semiconductor interface and the second metal-semiconductor interface [ current flows to the GaAs laser array die (510) ]. Therefore, claim 3 is met by the combination of Warren and Joseph, as applied to claim 1. With respect to claim 8, Warren discloses: The VCSEL array according to claim 1, wherein the VCSELs are bottom emitters [ figure 5A shows light propagating out of the top of GaAs laser array die (510) ]. Therefore, claim 8 is met by the combination of Warren and Joseph, as applied to claim 1. With respect to claim 12, Warren discloses: A light emitting device comprising the VCSEL array according to claim 1 and an electrical driver for providing an electrical drive current to the VCSELs [ taught by the laser driver electronics (230), in figure 2]. Therefore, claim 12 is met by the combination of Warren and Joseph, as applied to claim 1. The limitations recited by claims 4-7, 15 and 16 would have been met by a skilled artisan because it would have been obvious for a person of ordinary skill in electrical and optical engineering to have had a reasonable expectation of success in optimizing the impedance of the array elements disclosed by the device of Warren. Note the cited prior art demonstrates that the level of skill in the art would have required expertise in the design and fabrication of electronic circuits - impedance matching was known to improve efficiency. Therefore, claims 4-7, 15 and 16 would have been met by a skilled artisan producing the device created by the combination of Warren and Joseph, as applied to claim 1. Claim 9 would have been met by using flip chip methods in the construction of the device of Warren. Therefore, it would have been obvious for a person of ordinary skill in the art to have had a reasonable expectation of success in using a flip chip process to fabricate the device of Warren, as motivated by paragraph [0073], which states, " The two die 510, 535 are aligned and bonded using conventional EES chip bonding processes. " As a result, claim 9 is met by a skilled artisan fabricating the device produced by the combination of Warren and Joseph, as applied to claim 1. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Warren (United States Patent Application Publication No. 2016/0164261) in view of Joseph (United States Patent No. 8,848,757), as applied to claim 12 above, and further in view of Hellmig et al (United States Patent Application Publication No. 2018/0038944). Claim 13 recites: A time-of-flight camera comprising the light emitting device according to claim 12, the time-of-flight camera further comprising a light detector for detecting laser light reflected by an object and an evaluator, wherein the evaluator is configured to determine a distance to the object based on the laser light detected by the light detector. The modification of the combination of Warren and Joseph, as applied to claim 12, that would have produced claim 13, would have required the use of its illuminator in a time-of-flight camera system. Hellmig et al discloses an illumination system similar to Warren and also teaches that this type of illuminator can be used in a time-of-flight camera system. Paragraph [0004] states, " The illumination device may be suitable for camera systems and time of fight based distance detection devices...”. Therefore, it would have been obvious for a person of ordinary skill in the art to have had a reasonable expectation of success in using the illuminator produced by the combination of Warren and Joseph, as applied to claim 12, in a time-of-flight camera system because Hellmig et al taught that this was a known use for this type of device. Allowable Subject Matter Claims 10 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication should be directed to MARK HELLNER at telephone number (571)272-6981. Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. /MARK HELLNER/Primary Examiner, Art Unit 3645
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Prosecution Timeline

Dec 16, 2020
Application Filed
Dec 10, 2023
Non-Final Rejection — §103
Mar 12, 2024
Response Filed
Apr 25, 2024
Final Rejection — §103
Jun 28, 2024
Notice of Allowance
Aug 07, 2024
Response after Non-Final Action
Aug 07, 2024
Response after Non-Final Action
Aug 16, 2024
Response after Non-Final Action
Aug 21, 2024
Response after Non-Final Action
Sep 18, 2024
Response after Non-Final Action
Sep 20, 2024
Notice of Allowance
Oct 30, 2025
Response after Non-Final Action
Jan 04, 2026
Non-Final Rejection — §103
Mar 20, 2026
Examiner Interview Summary
Mar 25, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+8.2%)
2y 10m
Median Time to Grant
High
PTA Risk
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