DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This communication is considered fully responsive to the amendment filed on 07/11/2025.
Claims 1, 10, 15, 23, and 26 have been amended.
Response to Arguments
Applicant’s amendments with respect to claims 1, 10, 15, 23, and 26 filed on 07/11/2025 have been considered but are not persuasive because the amended limitations are disclosed by newly identified prior art Goh et al. (WO 2018009166 A1). It is addressed in the instant Office Action with newly identified prior art.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 10-11, 15, 22, 23, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goh et al. (WO 2018009166 A1), hereinafter Goh.
Regarding claim 1, Goh discloses a stiffener for an electronic package, comprising:
a first layer (140) (FIG. 1, [0037]),
wherein the first layer is conductive (140) (FIG. 1, [0037]);
a second layer (131) (FIG. 1, [0037]) over the first layer (140)), wherein the second layer (131) is insulative (131) ( [0037]);
a third layer (141) (FIG. 1, [0037]) over the second layer (portion of 131 between 140 and 141), wherein the third layer is conductive (141) ([0037]);
a leg (118) (FIG. 1, [0038])) attached to the third layer (141) ,
wherein the leg extends towards the first layer (140), and
wherein an entirety of the leg (118) does not vertically overlap with the second layer (portion of 131 between 140 and 141) (See FIG. 1)
Regarding claim 2, Goh discloses the stiffener of claim 1,
Goh discloses wherein the first layer (140) , the second layer ( portion of 131 between 140 and 141)) , and the third layer (141) are rings (FIG. 1 and FIG. 2, [0033]) with an interior edge (See FIG. FIG. 1 attached below) and an exterior edge (See FIG. FIG. 1 attached below).
Regarding claim 3, Goh discloses the stiffener of claim 2,
Goh discloses wherein the leg (118) is provided adjacent to the exterior edge (See FIG. 1 and FIG. 2 attached in claim 2.).
Regarding claim 4, Goh disclose the stiffener of claim 1,
Goh discloses wherein the leg is one leg in a plurality of legs (both side of legs 118) (See FIG. 1) that extend towards the first layer (140).
Regarding claim 5, Goh disclose the stiffener of claim 1,
Ogawa discloses wherein the leg (118) and the third layer (141) are a monolithic structure (See FIG. 1).
Regarding claim 10, Goh discloses an electronic package, comprising:
a package substrate (110) (FIG. 1, [0028]);
a die (121) (FIG. 1, [0028]) attached to the package substrate (110) ; and
a stiffener (130) (FIG. 3, [0032]) surrounding the die (121) (FIG. 3, [0028]), wherein the stiffener (130) comprises:
a first layer (140) (FIG. 1, [0037]), wherein the first layer is a conductive material (140) (FIG. 1, [0037]) , and wherein the first layer (140) (FIG. 1, [0037]) is electrically coupled to the package substrate (110) (FIG. 1, [0030]);
a second layer (Portion of 131 between 140 and 141)) (FIG. 1, [0037]) over the first layer (140), wherein the second layer is an insulating material (Portion of 131 between 140 and 141) ( [0037]);
a third layer (141) (FIG. 1, [0037]) over the second layer (Portion of 131 between 140 and 141) , wherein the third layer (141) is a conductive material (141) ([0037]); and
a leg (118) (FIG. 1, [0038])) attached to the third layer (141) ,
wherein the leg extends towards the first layer (140), and
wherein an entirety of the leg (118) does not vertically overlap with the second layer (portion of 131 between 140 and 141) (See FIG. 1).
Regarding claim 11, Goh discloses the electronic package of claim 10,
Goh discloses further comprising:
a second die (120) (See FIG. 1 and FIG.3) surrounded by the stiffener (113) (FIG. 3, [0031]), wherein the stiffener (113) further comprises:
a second leg (118 on the side of 130) attached to the third layer (141) and electrically coupled to the package substrate (110)
wherein the leg (118 on the side of 117) is electrically coupled to the die (121)) (See FIG. 1), and wherein the second leg (118 on the side of 130) is electrically coupled to the second die (120).
Regarding claim 15 , Goh discloses stiffener for an electronic package, comprising:
an outer shell (233, 232a, 232 b) (FIG. 5, [0035]); and
capacitor (130) (FIG. 1, [0028]) within the outer shell (233, 232a, 232 b) (FIG. 5,), wherein the capacitor (130) comprises:
a first electrode (horizontal portion of 140) (FIG. 1, [0037]);
a first dielectric layer (portion of 131 between 140 and 141)) (FIG. 1, [0037]) over the first electrode (140); and
a second electrode (141) (FIG. 1, [0037]) over the first dielectric layer (portion of 131 between 140 and 141)
the second electrode (141) (FIG. 2 (d), [0032]) has a leg (118 on the side of 130),
wherein an entirety of the leg (118) does not vertically overlap with the second layer (portion of 131 between 140 and 141).
Regarding claim 22, Goh shows the outer shell is a ring (outer sidewall of [130] in fig. 2).
Regarding claim 23, Goh discloses an electronic package, comprising:
a package substrate (110) (FIG. 1, [0028]);
a die (121) (FIG. 1, [0028]) on the package substrate (110); and
a stiffener (130) (FIG. 3, [0032]) surrounding the die (121),
wherein the stiffener (130) comprises:
an outer shell (233, 232a, 232 b) (FIG. 5, [0035]); and
a capacitor (130) (FIG. 1, [0028]) within the outer shell (233, 232a, 232 b) (FIG. 5, [0035]), wherein the capacitor (130) comprises:
a first layer (140) (FIG. 1, [0037]), wherein the first layer is conductive (140) ([0037]);
a second layer (Portion of 131 between 140 and 141) (FIG. 1, [0037]) over the first layer (140), wherein the second layer is insulative ([0037]);
a third layer (141) (FIG. 1, [0037]) over the second layer (Portion of 131 between 140 and 141),
wherein the third layer (141) is conductive ([0037]); and
a leg (118) (FIG. 1, [0038]) attached to the third layer (141), wherein the leg extends towards the first layer (140) (FIG. 1),
wherein an entirety of the leg (118) does not vertically overlap with the second layer (Portion of 131 between 140 and 141).
Regarding claim 26, Goh discloses an electronic package, comprising:
a package substrate (110) (FIG. 1, [0028]);
a die (121) (FIG. 1, [0028]) attached to the package substrate (110); and
a stiffener (130) (FIG. 3, [0032]) surrounding the die (121),
wherein the stiffener (130) comprises:
a first layer (140) (FIG. 1, [0037]),
wherein the first layer is a conductive material (140) (FIG. 1, [0037]), and wherein the first layer (140) is electrically coupled to the package
substrate (110) (See FIG. 1);
a second layer (Portion of 131 between 140 and 141) (FIG. 1, [0037]) over the first layer (140), wherein the second layer is an insulating material (Portion of 131 between 140 and 141) ( [0037]);
a third layer (141) (FIG. 1, [0037]) over the second layer (Portion of 131
between 140 and 141), wherein the third layer (141) is a conductive material ([0037]);
a leg (118 on the right side of FIG. 1) (FIG. 1, [0038]) attached to the third layer (141)and electrically coupled to the package substrate (110); and
a second die (120) (See FIG. 1 and FIG.3) surrounded by the stiffener (130) (FIG. 2, [0031]),
wherein the stiffener (130) further comprises:
a second leg (118 on the left side of FIG. 1) attached to the third layer(141)and electrically coupled to the package substrate (110),
wherein the leg (118 on the right side of FIG. 1) is electrically coupled to the die (121), and
wherein the second leg (118 on the left side of FIG. 1) is electrically coupled to
the second die (120) .
wherein an entirety of the leg (118) does not vertically overlap with the second layer (Portion of 131 between 140 and 141).
Claims 1 and 7 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ogawa (JP 2000232260 A), hereinafter Ogawa.
Regarding claim 1 (additional rejection), Ogawa discloses a stiffener for an electronic package, comprising:
a first layer (331) (FIG. 11(b), [0061]), wherein the first layer is conductive ([0061]; base electrode layer);
a second layer (332) (FIG. 11(b), [0063]) over the first layer (331) (FIG. 11(b), [0061]), wherein the second layer (332) (FIG. 11(b), [0063]) is insulative ([0063]; dielectric);
a third layer (333) (FIG. 11(b), [0064]) over the second layer (332) (FIG. 11(b), [0063]), wherein the third layer (333) (FIG. 11(b), [0063]) is conductive ([0063]; electrode); and
a leg (336) (FIG. 11(b), [0063]) attached to the third layer (333)
wherein the leg (336) extends towards the first layer (331), and
wherein an entirety of the leg (336) does not vertically overlap with the second layer (332)
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Regarding claim 7, Ogawa discloses the stiffener of claim 1 (see additional rejection of claim 1),
Ogawa discloses further comprising:
a fourth layer (337) (FIG. 11(b), [0078]) over the third layer (334) (FIG. 11(b), [0076]), wherein the fourth layer (337) (FIG. 11(b), [0078]) is an insulating material ([0078]);
a fifth layer (338) (FIG. 11(b), [0078]) over the fourth layer (337) (FIG. 11(b), [0078]), wherein the fifth layer (338) (FIG. 11(b), [0078]) is a conductive material ([0078]); and
a second leg (340) (FIG. 11(b), [0077]) attached to the fifth layer (338) (FIG. 11(b), [0078]),
wherein the second leg (340) (FIG. 11(b), [0077]) extends towards the first layer (331) (FIG. 11(b), [0077])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Goh and in view of Stone et al. (US 20030060063 A1), hereinafter Stone.
Regarding claim 12, Goh discloses the electronic package of claim 10,
Goh does not disclose further comprising:
a socket attached to the package substrate, wherein the socket comprises:
a plurality of pins; and
a conductive sheet between the plurality of pins.
Stone discloses a socket (See FIG. 5 attached below) attached to the package substrate (60) (FIG. 5, [0028]) wherein the socket comprises:
a plurality of pins (10, 11) (FIG. 5, [0021]); and
a conductive sheet (12) (FIG. 5, [0021]) between the plurality of pins (10, 11) (FIG. 5, [0021]).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to have modified Goh’s device structure to include the socket, as taught by Stone, to reduce the impedance discontinuity ([0002]).
Regarding claim 14, Goh and Stone disclose the electronic package of claim 12,
Goh does not disclose wherein the conductive sheet is configured to short circuit a power or ground plane on a board attached to the socket.
Stone discloses wherein the conductive sheet (12) (FIG. 5, [0027]) is configured to short circuit a power or ground plane on a board (60) (FIG. 5, [0028]) attached to the socket (See FIG. 5 attached in claim 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to have modified Ogawa’s device structure to include the conductive sheet, as taught by Stone, to provide capacitive coupling to pins and reduce the impedance discontinuity at the socket ([0022]).
Claims 20 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Goh and in view of Figueroa et al. (US 20020075630 A1), hereinafter Figueroa.
Regarding claim 20, Goh discloses the stiffener of claim 15,
Goh does not disclose wherein the outer shell comprises a cavity, and wherein the capacitor is positioned in the cavity.
Figueroa discloses wherein the outer shell (1204) (FIG. 12, [0070]) comprises a cavity (inside 1204) (FIG. 12), and wherein the capacitor (1200) (FIG. 12, [), [0070]) is positioned in the cavity (See FIG. 12).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ogawa’s structure capacitor to be positioned in the cavity, in order to be electrically connected to power and ground ([0071])
Regarding claim 24, Goh discloses the electronic package of claim 23,
Goh do not disclose specifically wherein the outer shell is grounded.
Figueroa discloses wherein the outer shell (1204) (FIG. 12, [0071]) is grounded ([0071]; these electrode and non-conductive layers 1208 1210 supply a capacitive charge when the left and right extended lands 1204 are electrically connected to power and ground, respectively.).
Therefore, It would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to have modified the outer shell Goh’s system to be grounded. as taught by Figueroa, for safety and equipment protection and suppression of the noise ([0090])
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Goh, in view of Figueroa, and further in view of Ogawa.
Regarding claim 21, Goh and Figueroa disclose the stiffener of claim 20,
Ogawa discloses wherein the capacitor (125) (FIG. 2(d), [0028]) is secured in the cavity (inside 123) (FIG. 2(d), [0029]) by a mold layer (121; stiffener body for rigidity) (FIG. 2(d), [0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ogawa’s capacitor to be positioned in the cavity by a mold layer, for cavity cover the stiffener body ([0029]) and to be electrically connected to power and ground.
Allowable Subject Matter
Claims 6, 8, 13, 16, 17 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAESUN LEE whose telephone number is (571)272-0943. The examiner can normally be reached Mon- Fri, 8 - 5 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAESUN LEE/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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