Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s cancellation of claims 3 – 4, 6, 16, 21, and 25 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 2, 7 – 13, 18 – 20, 22, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190006264 A1 hereinafter Vaidya.
For claim 1, Vaidya teaches an electronic package, comprising: a package substrate with a die side and a land side (fig. 7 showing a substrate 101 with two sides); a pad on the land side (fig. 7 numeral 103); a dielectric layer covering sidewalls of the pad, the dielectric layer having an uppermost surface at a same level as an uppermost surface of the pad, and the dielectric layer having a bottommost surface at a same level as a bottommost surface of the pad (fig. 7 numeral 115); and a surface finish on the uppermost surface of the pad and extending onto the uppermost surface of the dielectric layer (fig. 7 numeral 119). Vaidya also teaches embodiments wherein a solder resist over and in direct contact with the uppermost surface of the dielectric layer (fig. 6G shows solder resist 106 over and in contact with the dielectric layer 115). Vaidya does not explicitly teach an a surface finish on the uppermost surface of the pad and extending onto the uppermost surface of the dielectric layer, and a solder resist on and in direct contact with the uppermost surface of the dielectric layer in a singular embodiment. However, Vaidya also teaches that the various embodiments taught can be combined, and that various elements of each embodiment can be combine, removed, or mixed and that the embodiments are not mutually exclusive (Par. [0101 – 0103]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the surface finish embodiment and the solder resist embodiment in Vaidya together as Vaidya teaches combining the various embodiments and as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
For claim 2, Vaidya teaches all of claim 1. Vaidya also teaches the dielectric layer is a different material than a layer of the package substrate (Par. [0028]; Par. [0053]).
For claim 7, Vaidya teaches all of claim 1. Vaidya also teaches an opening through the solder resist that exposes a top surface of the pad is wider than the pad (fig. 6G numeral 116).
For claim 8, Vaidya teaches all of claim 7. Vaidya does not explicitly state that the pad is a metal defined pad. Vaidya does teach that the pad is formed from a metallization, and is surrounded by a dielectric layer (Par. [0058 – 0059]) and is shown inside a dielectric layer (fig. 6E numeral 103). Vaidya also teaches a variety of deposition methods that can be used for the pads (Par. [0039]) and that the pads are free of dielectric materials (Par. [0041]). Given the broadest reasonable interpretation of the term metal defined pad, Vaidya appears to teach a metal defined pad as the pad is metal, lacks dielectric material, is defined by the metal itself and not by a solder mask (i.e. is not a solder mask defined pad), and is located within a dielectric layer.
For claim 9, Vaidya teaches all of claim 1. Vaidya also teaches a die attached to the die side of the package substrate (fig. 11 numeral 929).
For claim 10, Vaidya teaches all of claim 9. Vaidya also teaches the die being coupled to the pad by conductive routing through a thickness of the package substrate (fig. 11 shows conductive vias 910 running through the package).
For claim 11, Vaidya teaches a method of forming an electronic package, comprising: forming a pad on a land side of a package substrate (fig. 6A numeral 103); disposing a dielectric layer over the pad (fig. 6B numeral 115); recessing the dielectric layer to expose an uppermost surface of the pad, wherein the dielectric remains over sidewall surfaces of the pad, the dielectric layer having an uppermost surface at a same level as the uppermost surface of the pad, and the dielectric layer having a bottommost surface at a same level as the uppermost surface of the pad, and the dielectric layer having a bottommost surface at a same level as a bottommost surface of the pad (fig. 6C numeral 116); and forming a surface finish on the uppermost surface of the pad and extending onto the uppermost surface of the dielectric layer (fig. 7 numeral 119; Par. [0064]). ). Vaidya also teaches embodiments wherein a solder resist is formed over and in direct contact with the uppermost surface of the dielectric layer (fig. 6G shows solder resist 106 over and in contact with the dielectric layer 115). Vaidya does not explicitly teach an a surface finish on the uppermost surface of the pad and extending onto the uppermost surface of the dielectric layer, and a solder resist on and in direct contact with the uppermost surface of the dielectric layer in a singular embodiment. However, Vaidya also teaches that the various embodiments taught can be combined, and that various elements of each embodiment can be combine, removed, or mixed and that the embodiments are not mutually exclusive (Par. [0101 – 0103]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the forming of the surface finish embodiment and the solder resist embodiment in Vaidya together as Vaidya teaches combining the various embodiments and as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
For claim 12, Vaidya teaches all of claim 11. Vaidya also teaches forming an opening through the dielectric layer exposes the uppermost surface of the pad (fig. 6F numeral 115).
For claim 13, Vaidya teaches all of claim 12. Vaidya also teaches a width of the opening through the dielectric layer is wider than a width of the pad (fig. 6E shows the pad 103 fully surrounded by the dielectric layer 115 and therefor the dielectric layer opening must be wider than the pad).
For claim 18, Vaidya teaches all of claim 11. Vaidya also teaches a die side of the package substrate is covered by a protective film during the operation of recessing the dielectric layer (fig. 6B - 6I shows protective film 112 covering a die side of the substrate 101 during the recessing process of the dielectric layer 115).
For claim 19, Vaidya teaches all of claim 11. Vaidya also teaches forming first level interconnects on a die side of the package substrate after exposing the surface of the pad (fig. 7 shows the formation of the first level interconnect by applying the surface finish 119 on top of the pad 103 after the recessing the dielectric 115).
For claim 20, Vaidya teaches a land side interconnect of a package substrate, comprising: a pad over a land side the package substrate , wherein the pad has a first surface connected to a via (fig. 7 numeral 103 shows a pad connected to a via), a second surface opposite the first surface, and sidewall surfaces connecting the first surface to the second surface (the pad 103 is shown to be rectangular with sidewalls and a first and a second surface opposite each other); a dielectric layer over the land side of the package substrate and directly contacting the sidewall surface of the pad, wherein the dielectric layer does not contact the second surface of the pad, wherein the dielectric layer has an uppermost surface at a same level as the second surface of the pad, and the dielectric layer having a bottom surface at a same level as the bottommost surface of the pad (fig. 7 numeral 115); and a surface finish on the second surface of the pad and extending onto the uppermost surface of the dielectric layer (fig. 7 numeral 119). Vaidya also teaches embodiments wherein a solder resist is formed over and in direct contact with the uppermost surface of the dielectric layer (fig. 6G shows solder resist 106 over and in contact with the dielectric layer 115). Vaidya does not explicitly teach an a surface finish on the uppermost surface of the pad and extending onto the uppermost surface of the dielectric layer, and a solder resist on and in direct contact with the uppermost surface of the dielectric layer in a singular embodiment. However, Vaidya also teaches that the various embodiments taught can be combined, and that various elements of each embodiment can be combine, removed, or mixed and that the embodiments are not mutually exclusive (Par. [0101 – 0103]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the forming of the surface finish embodiment and the solder resist embodiment in Vaidya together as Vaidya teaches combining the various embodiments and as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
For claim 22, Vaidya teaches all of claim 20. Vaidya also teaches an opening through the solder resist layer exposes the second surface of the pad, wherein the solder resist layer does not contact the second surface of the pad (fig. 6G numeral 116).
For claim 24, Vaidya teaches An electronic system, comprising: a board (fig. 12 numeral 1210); a package substrate coupled to the board (fig. 12 Par. [0017]; fig. 7 numeral 101); land side interconnects on the package substrate (fig. 7 numeral 104), wherein individual ones of the land side interconnects comprise: a pad over a land side of the package substrate, wherein the pad has a first surface connected to a via, a second surface opposite from the first surface, and sidewall surfaces connecting the first surface to the second surface (fig. 7 numeral 103 shows a rectangular pad with sidewalls connecting two sides, one of the two sides connected to a via); a dielectric layer over the land side of the package substrate and directly contacting the sidewall surfaces of the pad, wherein the dielectric layer does not contact the second surface of the pad, wherein the dielectric layer has an uppermost surface at a same level as the second surface of the pad, and wherein the dielectric layer having a bottommost surface at a same level as the bottommost surface of the pad (fig. 7 numeral 115); and a surface finish on the second surface of the pad and extending onto the uppermost surface of the dielectric layer (fig. 7 numeral 119); and a die coupled to a die side of the package substrate (fig. 11 numeral 929; Par. [0080]). Vaidya also teaches embodiments wherein a solder resist over and in direct contact with the uppermost surface of the dielectric layer (fig. 6G shows solder resist 106 over and in contact with the dielectric layer 115). Vaidya does not explicitly teach an a surface finish on the uppermost surface of the pad and extending onto the uppermost surface of the dielectric layer, and a solder resist on and in direct contact with the uppermost surface of the dielectric layer in a singular embodiment. However, Vaidya also teaches that the various embodiments taught can be combined, and that various elements of each embodiment can be combine, removed, or mixed and that the embodiments are not mutually exclusive (Par. [0101 – 0103]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the surface finish embodiment and the solder resist embodiment in Vaidya together as Vaidya teaches combining the various embodiments and as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Response to Arguments
Applicant's arguments filed 10/30/2025 have been fully considered but they are not persuasive.
Applicant’s arguments directed to claims 1, 11, 20, and 24 is focused on the prior art of record does not teach a solder resist on and in direct contact with the uppermost surface of the dielectric layer. This argument is not persuasive as the prior art of record (Vaidya) teaches a solder resist on and in direct contact with the uppermost surface of the dielectric layer, and that the various embodiments taught can be combined, mixed, or that various parts can be removed or combined (see the rejection above; Vaidya, Par. [101 – 103]). Vaidya does not teach away from combining the elements and no teaching in Vaidya suggests that combining the elements would result in the dielectric layer and the solder resist not being in direct contact. The solder resist as taught in Vaidya is shown to be in direct contact with the dielectric layer when implemented. For these reasons the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815