Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/25/2026 has been entered.
Status of the Claims
Claims 1, 11-12, and 18-19 have been amended. Claims 1-20 are currently pending and have been considered by the Examiner.
Claim Objections
Claims 9 and 13 objected are to because of the following informalities: In claim 9, line 2, Examiner recommends amending “the designated selected set” to recite “the selected set” to match the language of claim 8.
In claim 13, line 2, Examiner recommends amending “the designated selected set” to recite “the selected set” to match the language of claim 12. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the execution of the task" in line 7. There is insufficient antecedent basis for this limitation in the claim. Line 2 recites “solving a task” and it is unclear if this is the same or different from the execution of the task. Examiner treats “the execution of the task” as “the solving of the task”.
Claims 12-17 are rejected for failing to cure the deficiencies of claim 11.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claims 1-10 recite a system comprising a processor, claims 11-17 recite a method, and claims 18-20 recite a non-transitory computer readable medium (a product). A system, a method, and a product each falls under one of the four statutory categories of patent eligible subject matter.
Claim 1
Step 2A Prong 1: Evaluating a set of instructions for solving a task is an evaluation mental process which can reasonably be performed in the human mind with the aid of pencil and paper.
Utilize the stored intermediate result and the received predicted next intermediate result to provide a rank of the selected one of the plurality of sets of instructions is a judgement and evaluation mental process which can reasonably be performed in the human mind with the aid of pencil and paper. The claim recites an abstract idea.
Step 2A Prong 2: At least one processor capable of executing a plurality of sets of instructions for solving the task, the plurality of sets of instructions including one or more solvers amounts to generic computer components for applying the abstract ideas on a generic computer under MPEP 2106.05(f).
At least one memory coupled to the at least one processor, the at least one processor being configured to perform operations amounts to generic computer components for applying the abstract ideas on a generic computer under MPEP 2106.05(f).
Provide, via the at least one memory, a task input to a selected one of the plurality of sets of instructions to perform the task amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f).
Store, in the at least one memory, an intermediate result by the selected one of the plurality of sets of instructions at an intermediate stage while solving the task amounts to insignificant extra-solution activity under MPEP 2106.05(g).
The intermediate result being generated at a specific stage during the execution of the task, before reaching a final result of the task amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f).
The intermediate result being stored in a solver input buffer provided by a controller and populated with task data supplied to the solver amounts to insignificant extra-solution activity under MPEP 2106.05(g). A controller is a generic computer component for applying the abstract ideas on a generic computer under MPEP 2106.05(f).
Receive a prediction of a next intermediate result from the selected one of the plurality of sets of instructions amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f).
Perform the task using a highest ranked set of instructions in the provided rank amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f).
The additional elements as disclosed above, alone or in combination, do not integrate the abstract ideas into a practical application as they are mere insignificant extra solution activities as disclosed in combination with generic computer functions that are implemented to perform the abstract ideas disclosed above. The claim is directed to an abstract idea.
Step 2B: At least one processor capable of executing a plurality of sets of instructions for solving the task, the plurality of sets of instructions including one or more solvers amounts to generic computer components for applying the abstract ideas on a generic computer under MPEP 2106.05(f).
At least one memory coupled to the at least one processor, the at least one processor being configured to perform operations amounts to generic computer components for applying the abstract ideas on a generic computer under MPEP 2106.05(f).
Provide, via the at least one memory, a task input to a selected one of the plurality of sets of instructions to perform the task amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f).
Store, in the at least one memory, an intermediate result by the selected one of the plurality of sets of instructions at an intermediate stage while solving the task is a well-understood, routine, conventional activity of storing information in memory, which the courts have recognized, under MPEP 2106.05(d)(II).
The intermediate result being generated at a specific stage during the execution of a task or process, before reaching a final result amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f).
The intermediate result being stored in a solver input buffer provided by a controller and populated with task data supplied to the solver is a well-understood, routine, conventional activity of storing information in memory, which the courts have recognized, under MPEP 2106.05(d)(II). A controller is a generic computer component for applying the abstract ideas on a generic computer under MPEP 2106.05(f).
Receive a prediction of a next intermediate result from the selected one of the plurality of sets of instructions amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f).
Perform the task using a highest ranked set of instructions in the provided rank amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f).
The additional elements as disclosed above, in combination with the abstract ideas, are not sufficient to amount to significantly more than the abstract ideas as they are well-understood, routine and conventional activities as disclosed in combination with generic computer functions that are implemented to perform the abstract ideas disclosed above. The claim is not patent eligible.
Claim 2 incorporates the rejection of claim 1.
Step 2A Prong 1: The abstract ideas of claim 1 are incorporated.
Step 2A Prong 2 and Step 2B: The plurality of sets of instructions includes at least one domain-specific solver amounts to a mere field of use and technological environment under MPEP 2106.05(h). The claim is not patent eligible.
Claim 3 incorporates the rejection of claim 2.
Step 2A Prong 1: The abstract ideas of claim 2 are incorporated.
Step 2A Prong 2 and Step 2B: The at least one domain-specific solver includes at least one of a Monte Carlo, Particle Methods, and Sparse Solver amounts to a mere field of use and technological environment under MPEP 2106.05(h). The claim is not patent eligible.
Claim 4 incorporates the rejection of claim 1.
Step 2A Prong 1: The abstract ideas of claim 1 are incorporated.
Step 2A Prong 2 and Step 2B: The plurality of sets of instructions includes at least one machine learning (ML) solver amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f) and a mere field of use and technological environment under MPEP 2106.05(h). The claim is not patent eligible.
Claim 5 incorporates the rejection of claim 4.
Step 2A Prong 1: The abstract ideas of claim 4 are incorporated.
Step 2A Prong 2 and Step 2B: The at least one ML solver includes at least one of a Markov model, a decision tree, and a support vector machine (SVM) solver amounts to a mere field of use and technological environment under MPEP 2106.05(h). The claim is not patent eligible.
Claim 6 incorporates the rejection of claim 1.
Step 2A Prong 1: The abstract ideas of claim 1 are incorporated.
Step 2A Prong 2 and Step 2B: The plurality of sets of instructions includes at least one artificial intelligence (Al) solver amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f) and a mere field of use and technological environment under MPEP 2106.05(h). The claim is not patent eligible.
Claim 7 incorporates the rejection of claim 6.
Step 2A Prong 1: The abstract ideas of claim 6 are incorporated.
Step 2A Prong 2 and Step 2B: The at least one Al solver includes at least one of a Convolutional neural network solver and long short-term memory (LSTM) Neural Network solver amounts to a mere field of use and technological environment under MPEP 2106.05(h). The claim is not patent eligible.
Claim 8 incorporates the rejection of claim 1.
Step 2A Prong 1: The abstract ideas of claim 1 are incorporated. Designating a set of instructions based on the provided rank is a judgement and evaluation mental process which can reasonably be performed in the human mind with the aid of pencil and paper.
Step 2A Prong 2 and Step 2B: The at least one processor amounts to a generic computer component for applying the abstract ideas on a generic computer under MPEP 2106.05(f). The claim is not patent eligible.
Claim 9 incorporates the rejection of claim 8.
Step 2A Prong 1: The abstract ideas of claim 8 are incorporated.
Step 2A Prong 2 and Step 2B: The at least one processor uses the designated selected set of instructions for future processing of the task amounts to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f). The claim is not patent eligible.
Claim 10 incorporates the rejection of claim 1.
Step 2A Prong 1: The abstract ideas of claim 1 are incorporated.
Step 2A Prong 2 and Step 2B: Operating in an execution environment including an encrypted memory buffer amounts to a mere field of use and technological environment under MPEP 2106.05(h). The claim is not patent eligible.
Claim 11 recites a method which implements the same features as the system of claim 1 and is therefore rejected for at least the same reasons.
Claim 12 incorporates the rejection of claim 11.
Step 2A Prong 1: The abstract ideas of claim 11 are incorporated. Designating the highest ranked set of instructions based on the provided rank is a judgement and evaluation mental process which can reasonably be performed in the human mind with the aid of pencil and paper.
Step 2A Prong 2 and Step 2B: The at least one processor amounts to a generic computer component for applying the abstract ideas on a generic computer under MPEP 2106.05(f). The claim is not patent eligible.
Claim 13 recites a method which implements the same features as the system of claim 9 and is therefore rejected for at least the same reasons.
Claim 14 incorporates the rejection of claim 11.
Step 2A Prong 1: The abstract ideas of claim 11 are incorporated.
Step 2A Prong 2 and Step 2B: The plurality of sets of instructions includes at least one set of instructions selected from at least one domain-specific solver amounts to a mere field of use and technological environment under MPEP 2106.05(h).
At least one machine learning (ML) solver and at least one artificial intelligence (AI) solver amount to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f) and mere fields of use and technological environments under MPEP 2106.05(h). The claim is not patent eligible.
Claims 15-17 each recite a method which implements the same features as the system of claims 3, 5, 7, respectively, and are therefore rejected for at least the same reasons.
Claim 18 recites a product which implements the same features as the system of claim 1 and is therefore rejected for at least the same reasons.
In Step 2A Prong 2 and Step 2B, a non-transitory computer readable medium including code stored thereon which when executed by a processor cause a system to perform a method amounts to generic computer components for applying the abstract ideas on a generic computer under MPEP 2106.05(f). The claim is not patent eligible.
Claim 19 incorporates the rejection of claim 18.
Step 2A Prong 1: The abstract ideas of claim 18 are incorporated. Designating the highest ranked set of instructions based on the provided rank is a judgement and evaluation mental process which can reasonably be performed in the human mind with the aid of pencil and paper.
Step 2A Prong 2 and Step 2B: The at least one processor amounts to a generic computer component for applying the abstract ideas on a generic computer under MPEP 2106.05(f). The claim is not patent eligible.
Claim 20 incorporates the rejection of claim 18.
Step 2A Prong 1: The abstract ideas of claim 18 are incorporated.
Step 2A Prong 2 and Step 2B: The plurality of sets of instructions includes at least one set of instructions selected from at least one domain-specific solver amounts to a mere field of use and technological environment under MPEP 2106.05(h).
At least one machine learning (ML) solver, and at least one artificial intelligence (AI) solver amount to mere instructions to apply the abstract ideas on a generic computer under MPEP 2106.05(f) and mere fields of use and technological environments under MPEP 2106.05(h). The claim is not patent eligible.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, 8-9, 11-14, 16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Volodarskiy et al. (US 20200175354 A1, cited in the PTO-892 issued on 07/09/2024).
Regarding claim 1, Volodarskiy teaches: A system for evaluating a set of instructions for solving a task, the system comprising: at least one processor capable of executing a plurality of sets of instructions for solving the task, the plurality of sets of instructions including one or more solvers; and ([0026], [0029], lines 1-2, and [0054], lines 1-4 and 20-25 teaches executing machine-learning algorithms on a processor. A “set of instructions for solving a task” and “solvers” are machine-learning algorithms, and the task includes predicting a target feature based on input features.)
at least one memory coupled to the at least one processor, the at least one processor being configured to: ([0019], lines 1-7 and 11-13 discloses platform 110 including servers for executing functions, and the platform comprises databases 114. The databases are memory.)
provide, via the at least one memory, a task input to a selected one of the plurality of sets of instructions to perform the task; ([0052], lines 1 and 3-6 and [0053], lines 1-3 discloses retrieving raw data from database 114 (“memory”) and preprocessing it. [0055], [0056], lines 1-5, [0064], lines 7-11 (disclosing that step 405 may be part of step 340, and step 412 may be part of step 350), and [0066]-[0067] discloses executing trials for a plurality of machine learning-algorithms or models, which performs a prediction task. A selected set of instructions is one of the machine-learning algorithms/models in the batch of trials, and a task input includes preprocessed data provided via database 114.)
store, in the at least one memory, an intermediate result by the selected one of the plurality of sets of instructions at an intermediate stage while solving the task, wherein the intermediate result is generated at a specific stage during the execution of the task before reaching a final result of the task, ([0067]-[0069] discloses executing a trial, which would include processing a model, storing results of a trial in database 114, and then determining whether or not there is sufficient data to perform an intermediate selection of models to be evaluated. This means a result of the first trial of machine learning algorithms is an intermediate result at an intermediate stage while solving the task. A final result of the task would be a model prediction made during deployment in [0059], lines 1-3.)
wherein the intermediate result is stored in a solver input buffer provided by a controller and populated with task data supplied to the solver; ([0023], lines 1-8, [0052], line 6 (database 114 stores raw data), and [0067], where “a solver input buffer” is database 114, it is populated with data to be supplied to the model, and it also stores results from each trial. Since data can be read from and written to database 114, this indicates platform 110 includes a controller.)
receive a prediction of the next intermediate result from the selected one of the plurality of sets of instructions; ([0069]-[0070], [0072] discloses estimating an accuracy of one of the models from the trial. Since estimating an accuracy would require a model output, this section teaches generating a next intermediate result as the model output during accuracy estimation.)
utilize the stored intermediate result and the received predicted next intermediate result to provide a rank of the selected one of the plurality of sets of instructions; and ([0055], [0056], lines 1-5, and [0057], lines 1-6 discloses evaluating and ranking models on a leaderboard.)
perform the task using a highest ranked set of instructions in the provided rank. ([0058] and [0059], lines 1-3)
Regarding claim 4, Volodarskiy teaches: The system of claim 1 wherein the plurality of sets of instructions includes at least one machine learning (ML) solver. ([0026])
Regarding claim 5, Volodarskiy teaches: The system of claim 4 wherein the at least one ML solver includes at least one of a Markov model, a decision tree, and a support vector machine (SVM) solver. ([0026], line 6 teaches a random forest algorithm, which comprises multiple decision trees.)
Regarding claim 6, Volodarskiy teaches: The system of claim 1 wherein the plurality of sets of instructions includes at least one artificial intelligence (Al) solver. ([0026], lines 6-8 teaches deep neural networks.)
Regarding claim 8, Volodarskiy teaches: The system of claim 1 wherein the at least one processor designates a set of instructions based on the provided rank. ([0058])
Regarding claim 9, Volodarskiy teaches: The system of claim 8 wherein the at least one processor uses the designated selected set of instructions for future processing of the task. ([0059], lines 1-3)
Claim 11 recites a method which implements the same features as the system of claim 1 and is therefore rejected for at least the same reasons.
Regarding claim 12, Volodarskiy teaches: The method of claim 11 further comprising designating the highest ranked set of instructions based on the provided rank. ([0058] discloses selecting a single model, which would correspond to the model at the top of the leaderboard.)
Claim 13 recites a method which implements the same features as the system of claim 9 and is therefore rejected for at least the same reasons.
Regarding claim 14, Volodarskiy teaches: The method of claim 11 wherein the plurality of sets of instructions includes at least one set of instructions selected from at least one domain-specific solver, at least one machine learning (ML) solver, and ([0026] teaches machine learning solvers. Line 6 teaches a random forest algorithm. The limitation “at least one ML solver” corresponds to a random forest algorithm.)
at least one artificial intelligence (AI) solver. ([0026], lines 6-8 teaches deep neural networks.)
Claim 16 recites a method which implements the same features as the system of claim 5 and is therefore rejected for at least the same reasons.
Claim 18 recites a product which implements the same features as the system of claim 1 and is therefore rejected for at least the same reasons.
Volodarskiy teaches: A non-transitory computer readable medium including code stored thereon which when executed by a processor cause the system to perform a method ([0033])
Regarding claim 19, Volodarskiy teaches: The computer readable medium of claim 18 further comprising designating the highest ranked set of instructions based on the provided rank. ([0058] discloses selecting a single model, which would correspond to the model at the top of the leaderboard.)
Regarding claim 20, Volodarskiy teaches: The computer readable medium of claim 18 wherein the plurality of sets of instructions includes at least one set of instructions selected from at least one domain-specific solver, at least one machine learning (ML) solver, and ([0026] teaches machine learning solvers. Line 6 teaches a random forest algorithm. The limitation “at least one ML solver” corresponds to a random forest algorithm.)
at least one artificial intelligence (AI) solver. ([0026], lines 6-8 teaches deep neural networks.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Volodarskiy et al. (US 20200175354 A1, cited in the PTO-892 issued 07/09/2024) in view of Georgescu et al. (US 20160174902 A1)
Regarding claim 2, Volodarskiy teaches: The system of claim 1 wherein the plurality of sets of instructions includes at least one
However, Volodarskiy does not explicitly teach: domain-specific
But Georgescu teaches: domain-specific solver ([0089], lines 1-22 discloses a sparse deep neural network for detecting 3D objects in volumetric medical image data. A “domain” includes image data.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included Georgescu’s sparse deep neural network as one of Volodarskiy’s available algorithm. A motivation for the combination is that fast and robust anatomical object detection is a fundamental task in medical image analysis, and automatic detection of an anatomical object is a prerequisite for many medical image analysis tasks. (Georgescu, [0003], lines 1-7)
Regarding claim 3, the combination of Volodarskiy and Georgescu teaches: The system of claim 2.
Volodarskiy does not explicitly teach: wherein the at least one domain-specific solver includes at least one of a Monte Carlo, Particle Methods, and Sparse Solver.
But Georgescu teaches: wherein the at least one domain-specific solver includes at least one of a Monte Carlo, Particle Methods, and Sparse Solver. ([0089], lines 1-22 discloses a sparse deep neural network for detecting 3D objects in volumetric medical image data.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included Georgescu’s sparse deep neural network as one of Volodarskiy’s available algorithm. A motivation for the combination is to reduce computational resources consumed by traditional deep neural network architectures. (Georgescu, [0089], lines 1-8)
Claim 15 recites a method which implements the same features as the system of claims 2 and 3 and is therefore rejected for at least the same reasons.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Volodarskiy et al. (US 20200175354 A1, cited in the PTO-892 issued on 07/09/2024) in view of Bardy et al. (US 20180206752 A1, cited in the PTO-892 issued on 11/07/2025).
Regarding claim 7, Volodarskiy teaches: The system of claim 6 wherein the at least one Al solver includes at least one of a
However, Volodarskiy does not explicitly teach: at least one of a Convolutional neural network solver and long short-term memory (LSTM).
But Bardy teaches: at least one of a Convolutional neural network solver and long short-term memory (LSTM). ([0096], lines 8-12)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have included Bardy’s convolutional neural network as one of Volodarskiy’s available algorithm. A motivation for the combination is to process ECG data. (Bardy, [0096])
Claim 17 recites a method which implements the same features as the system of claim 7 and is therefore rejected for at least the same reasons.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Volodarskiy et al. (US 20200175354 A1, cited in the PTO-892 issued 07/09/2024) in view of Ho et al. (US 20200007931 A1, cited in the PTO-892 issued 07/09/2024).
Regarding claim 10, Volodarskiy teaches: The system of claim 1 operating in an execution environment including
However, Volodarskiy does not explicitly teach: an encrypted memory buffer.
But Ho teaches: an encrypted memory buffer ([0087], lines 1-10 and [0088] discloses an encrypted video is stored to a memory buffer, the encrypted video is retrieved from the memory buffer, and a neural network processor decrypts the video by applying a neural network. The limitation “an encrypted memory buffer” corresponds to a memory buffer storing encrypted video.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Ho’s memory buffer storing an encrypted video into Volodarskiy, and to have used a neural network to decrypt the encrypted video. A motivation for the combination is to accelerate machine learning and artificial intelligence inference for video processing while maintaining the protection of the protected media content during the inference processing. (Ho, [0003])
Response to Arguments
Below are the Examiner’s responses to the Applicant’s arguments filed 08/25/2026.
Applicant’s Arguments Under 35 U.S.C. 101 – Step 2A, Prong 1: On page 10, the Applicant disagrees with the previous mental process grouping because it improperly strips away the concrete technical architecture recited throughout the claims and characterizes the invention at an impermissibly high level of abstraction. On page 11, the Applicant submits that a human mind cannot populate a solver input buffer, receive prediction outputs from multiple server processes, and enforce a hard real-time deadline. Applicant argues this is not a mental process, but a concrete technical arrangement that has no meaningful analog in human cognition.
Examiner’s Response: Applicant's arguments have been fully considered but they are not persuasive. In the 101 analysis of pending claim 1, in step 2A prong 1, the limitation “evaluating a set of instructions for solving a task” is an evaluation mental process, and the limitation “utilize the stored intermediate result and the received predicted next intermediate result to provide a rank of the selected one of the plurality of sets of instructions” is a judgement and evaluation mental process. As explained on page 27 in the Final Office Action, a human mind can compare results obtained during the task performances. Instant specification paragraph [0115] discloses the ranking may be made by measuring performance and resource demands of each solver. The different measurements may guide ranking independently or via a weighted sum using some or all of the variables. This indicates the measurement is a numerical value. Comparing the results to determine a ranking would amount to ranking the sets of instructions starting with the best measurement. A human mind can reasonably rank the sets of instructions if given the corresponding measurements.
The claimed limitations of populating a solver input buffer and receiving a prediction output from a process are not considered to be mental processes, but additional elements to be considered in step 2A Prong 2. Claim 1 does not explicitly recite that the buffer is “on a configurable N-second clock cycle” and “concurrently receive prediction outputs from multiple server processes polling a separate prediction buffer at the same periodicity, and enforce a real-time deadline that removes non-compliant solver processes from the evaluation cycle.” Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Since claim 1 does not recite the above technical features, the rejection of claim 1 does not strip away a concrete technical architecture, as argued by the Applicant.
Additionally, since the only abstract ideas recited by claim 1 are “evaluating a set of instructions for solving a task” and “utilize the stored intermediate result and the received predicted next intermediate result to provide a rank of the selected one of the plurality of sets of instructions”, these limitations do not characterize the invention at an impermissibly high level of abstraction.
Applicant’s Arguments Under 35 U.S.C. 101 – Step 2A, Prong 2: On pages 11-13, the Applicant argues that the combination of elements improves the functioning of the system by ensuring that the processor ultimately performs the task with the solver best suited to produce accurate and timely intermediate and final results thereby providing a concrete technical benefit rooted in the claimed architecture.
Examiner’s Response: Applicant's arguments have been fully considered but they are not persuasive. The claimed invention of claim 1 is directed to evaluating and ranking instructions/solvers based on a series of executed computer instructions, data transmission, and memory access, and then applying the highest ranked instruction/solver. Every computer elements of claim 1 is recited at a high level of generality such that it amounts to a generic computer component under MPEP 2106.05(f). The solver input buffer stores an intermediate result and task data, and it performs the function of a generic computer storage component. The controller controls dataflow to and from the solver input buffer, and it performs the function of a generic computer processing component. The controller transferring data into and out of the solver input buffer (a type of memory) is an insignificant extra-solution activity under MPEP 2106.05(g).
Claim 1 does not explicitly recite any feature of “enforcing a timing constraint by ignoring solvers that miss the prediction deadline”. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. On page 12, lines 2-3, the Applicant argues that a practical application includes using the stored intermediate results and predicted next intermediate results to rank solvers. This is a judgement and evaluation mental process abstract idea. It is noted that the judicial exception alone cannot provide the improvement, and an improvement in the abstract idea itself is not an improvement in technology. See MPEP 2106.05(a) and (a)(II).
With regard to the arguments on page 12 starting at line 5, generating intermediate results by an instruction/solver at intermediate stages of an ongoing task are mere instructions for applying the abstract ideas under MPEP 2106.05(f). Nothing in the claim demonstrates how generating a series of results for an ongoing task provides a technical improvement, even in combination with the other additional elements. Furthermore, claim 1 does not explicitly recite any feature related to a “timing enforcement mechanism [that] dynamically removes non-performing solvers from the competition.”
Applicant’s Arguments Under 35 U.S.C. 101 – Step 2B: On pages 13-14, the Applicant argues that storing intermediate results as defined checkpoints in the ongoing processing of a task as recited is not well-understood, routine, and conventional activity. The Applicant argues that viewed as an ordered combination, the additional elements amount to significantly more than any abstract idea they may implement.
Examiner’s Response: Applicant's arguments have been fully considered but they are not persuasive. As explained above, every computer elements of claim 1 is recited at a high level of generality such that it amounts to a generic computer component under MPEP 2106.05(f). The solver input buffer stores an intermediate result and task data, and it performs the function of a generic computer storage component. The controller controls dataflow to and from the solver input buffer, and it performs the function of a generic computer processing component. The controller transferring data into and out of the solver input buffer (a type of memory) amounts to well-understood, routine, conventional activity of reading and writing data to a memory under MPEP 2106.05(d)(II). The claim is not patent eligible.
Applicant’s First Arguments Under 35 U.S.C. 103: On pages 15-19, the Applicant argues that Volodarskiy and Bardy do not teach at least the limitations in pending claim 1, lines 10-15. On page 15 the Applicant argues that the Final Office Action relied on Volodarskiy and Bardy for rejecting “a solver input buffer provided by a controller and populated with task data supplied to the solver” of claim 1.
On page 16, Applicant submits that Volodarskiy at [0031] teaches generic computer memory used in the normal operation of the platform, not a dedicated solver input buffer provided by a controller and populated with separately supplied task data.
On page 17, the Applicant submits that the cited art fails to teach intermediate results as checkpoints in the processing of a single ongoing task. Applicant argues that claim 1 requires that intermediate results are stored at an intermediate stage while solving the task, i.e., partway through a single, ongoing execution. On page 18, the Applicant argues that Bardy’s test result for a given sample is not an intermediate result at an intermediate stage of solving the task of classifying that sample; it is the final, completed output of the model for that sample. The Applicant argues that Bardy’s model does not checkpoint its own processing partway through handling any single sample; each sample is processed to completion independently. On page 19, the Applicant argues that a checkpoint in the processing of a task is a partially completed result produced during an ongoing, single execution, not a completed result of one instance in a series of independent model evaluations.
Examiner’s Response: Applicant's arguments have been fully considered but they are not persuasive. First, it is noted that the limitation “a solver input buffer provided by a controller and populated with task data supplied to the solver” was absent from the previous claim set. The Final Office Action did not provide any rejection for this limitation because it was absent.
The Examiner respectfully disagrees with the Applicant’s argument that Volodarskiy fails to teach the limitations in pending claim 1, lines 10-15. It is noted that the claimed features of solving a task, an intermediate result, an intermediate stage, and a final result are all broadly recited.
Volodarskiy teaches “at least one memory coupled to the at least one processor”. [0019], lines 1-7 and 11-13 discloses platform 110 including servers for executing functions, and the platform comprises databases 114. The databases are memory.
Claim 1, lines 8-20 is taught by Volodarskiy in paragraphs [0019], lines 1-7 and 11-13; [0023], lines 1-8, [0052], lines 1 and 3-6 and [0053], lines 1-3; [0055], [0056], lines 1-5, [0057], lines 1-6, [0059], lines 1-3, [0064], lines 7-11 (disclosing that step 405 may be part of step 340, and step 412 may be part of step 350), and [0066]-[0070], [0072]. The feature of a solver input buffer populated with task data is taught by Volodarskiy’s database 114 for storing input data.
The feature of an intermediate result by the selected set of instructions at an intermediate stage while solving the task is taught by Volodarskiy’s trials executed for a plurality of models at step 412 based on preprocessed input data. Its results are stored in database 114. The trials are an intermediate result because they happen before estimating model accuracy. The feature of a prediction of a next intermediate result by the selected set of instructions is taught by the estimated accuracy of the model from the trial. Since estimating an accuracy would require a model output, this step teaches generating a next intermediate result as the model output during accuracy estimation. The feature of using the intermediate result and predicted next intermediate result to rank the selected set of instructions is taught by evaluating and ranking models on a leaderboard based on their evaluations. A final result of the task would be a model prediction made during deployment.
The Applicant’s arguments on pages 17-18 regarding Bardy are moot because the rejection of claim 1 does not rely on this reference. Additionally, the claim does not explicitly recite that a model checkpoints its own processing partway through handling a single data sample before reaching a final prediction for said data sample, and it is unclear where the specification provides support for this interpretation. Similarly, in response to the Applicant’s arguments from pages 19, the claims are broadly recited in that only “an intermediate stage” is tied to the execution of the task, and it must be completed before reaching some final result. A final result of the task includes any final result of solving the task, such as executing the task in step 380 at prediction service. A “prediction of a next intermediate result” is also not directly tied to the execution of the task.
Applicant’s Second Arguments Under 35 U.S.C. 103: On pages 20-21, the Applicant submits that Sun fails to teach “domain-specific solver” within the meaning of the claims (claim 2).
Examiner’s Response: Applicant’s arguments with respect to claim 2 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s Third Arguments Under 35 U.S.C. 103: On pages 21-22, with respect to claim 10, the Applicant argues that Ho’s architecture is designed to solve the specific problem of maintaining content protection while applying neural networks to encrypted video. The applicant argues this problem is entirely foreign to the context of Volodarskiy, and the previous Office Action fails to articulate any motivation that would have led a skilled artisan to incorporate Ho’s DRM-protected video buffer infrastructure into Volodarskiy’s general ML model evaluation and selection platform.
Examiner’s Response: Applicant's arguments have been fully considered but they are not persuasive. Claim 10 recites that the system of claim 1 operates in “an execution environment including an encrypted memory buffer”. Claim 10 is broad because it does not explain how an encrypted memory buffer fits into the infrastructure of the evaluation and selection system of claim 1. Any arguments directed toward the different fields of endeavor addressed by Volodarskiy and Ho, and any arguments directed toward insufficient motivation to incorporate Ho’s DRM-protected video buffer infrastructure into Volodarskiy, stem from the breadth of claim 10.
Conclusion
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/A.H.J./Examiner, Art Unit 2127
/ABDULLAH AL KAWSAR/Supervisory Patent Examiner, Art Unit 2127
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