DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other Refs: Goel (US 20150199272) – concurrent store and load operation.
Sankaran (20150178202 – 0079, 0069).
Shuf (US 6886085)
Bradbury (US 20170220475)
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-13,15-22, 26-27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no showing of support for the amended limitations, from the original disclosure. Support is required otherwise, the limitations must be removed.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1,3,4,11,12,13,15,16,26, 27 are rejected under 35 U.S.C. 103 as being unpatentable over Doi (US 10671550) and in view of Kim (US 20050289300) and further in view of Hooker (US 20040158681)
Claim 1. Doi discloses An apparatus (e.g., computing node 200; col 5:23-26 Fig. 2) comprising:
a cache to store a buffer (e.g., temporary buffer 342/352 is prepared on each of the device memories 234., col 7:1-5; Fig. 3); and
execution circuitry to execute an instruction, (e.g., CPU 210, col 5:23-26 Fig. 2).
the execution of the instruction to cause cachelines in the buffer to be modified, at least in part, on (e.g., the whole of the units 320 can be allocated onto the device memories 234 of the GPUs 230. On the other hand, when the number of the qubits n is relatively large, only a part of the units 320 (Σn.sub.gi<2.sup.(n-u)) can be allocated onto the device memories 234 and a remaining part of the units 320 (2.sup.(n-u)−Σn.sub.gi) is allocated onto the system memory 220., col 6:42-48; temporary buffers 332, 342, 352 may have the same size as the unit 2.sup.u , col 7:4-5),
Doi does not disclose, but Kim discloses
wherein a marked cacheline in the buffer is to be prevented from being written back to memory (e.g., keeping the reserved line in the cache, instead of writing back to memory , 0026).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, providing the benefit of by keeping the reserved line in the cache, instead of writing back to memory and bring it back, is better in performance (see Kim, 0026) for managing an atomic facility cache write back controller. A reservation pointer pointing to the reserved line in the atomic facility cache data array (0015).
Doi in view of Kim does not disclose, but Hooker discloses
at least having an indication of a start address of the buffer and an indication of two or more cachelines of the buffer to modify a state for,; a state of two or more .. modified… at least in part, on the start address for the buffer (eg., 0027 - a single macro instruction, to direct a microprocessor to write back and invalidate a specified number of cache lines; 0029 - to perform operations which are specified by the macro instructions 121-123; 0058 - where the addresses of the specified number of cache lines includes an address; [0066] Fig 8 At block 808, the macro instruction is translated into a corresponding micro instruction sequence directing the microprocessor to perform a specified operation.);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, with Hooker, providing the benefit of enable a programmer to direct a microprocessor to perform write back and invalidate operations to flush a specified number of cache lines from its internal cache (see Hooker, 0002).
Claim 3. Doi does not disclose, but Kim discloses
the state is to be modified the to an Exclusive state (e.g., Modified, Exclusive, Shared, and Invalid (MESI) system. In MESI, data in a cache in a multiprocessor system is marked as one of the above, to ensure data coherency., 0007; read-exclusive, 0032) .
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, providing the benefit of by keeping the reserved line in the cache, instead of writing back to memory and bring it back, is better in performance (see Kim, 0026) for managing an atomic facility cache write back controller. A reservation pointer pointing to the reserved line in the atomic facility cache data array (0015).
Claim 4. Doi does not disclose, but Kim discloses
wherein the one or more cachelines as are to be indicatd victim candidates to allow early eviction of the one or more cachelines based on the modified state (e.g., the victim line for write back is selected by LRU algorithm and the reservation line is not selected by skipping over this pointer., 0026; the victim pointer denotes which information is to be written back out of the atomic cache, 0040 Fig. 5).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, providing the benefit of by keeping the reserved line in the cache, instead of writing back to memory and bring it back, is better in performance (see Kim, 0026) for managing an atomic facility cache write back controller. A reservation pointer pointing to the reserved line in the atomic facility cache data array (0015).
Claim 11. Doi discloses wherein a processor core comprises the execution circuitry and the cache (e.g., computing node 200 that includes a CPU (Central Processing Unit) 210 as the general-purpose processor, a system memory 220, and one or more GPUs (Graphical Processing Units) 230 as the accelerators., col 5:23-27).
Claim 12. Doi discloses wherein the processor core comprises a Graphics Processing Unit (GPU) core (e.g., GPUs, col 5:25-27).
Claim 26. Doi in view of Kim does not disclose, but Hooker discloses
wherein the state is to be modified to an Invalid state. (eg., 0011 - invalidate contents of a single cache line. );
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, with Hooker, providing the benefit of enable a programmer to direct a microprocessor to perform write back and invalidate operations to flush a specified number of cache lines from its internal cache (see Hooker, 0002).
Claim 13. Doi discloses One or more non-transitory computer-readable media comprising an instance of an instruction that when executed on at least one processor is to cause the at least one processor to perform (e.g., computing node 200; col 5:23-26 Fig. 2; CPU 210, col 5:23-26 Fig. 2) a method comprising:
executing the instance of the instruction to cause cachelines in the buffer to be modified, at least in part, on (e.g., the whole of the units 320 can be allocated onto the device memories 234 of the GPUs 230. On the other hand, when the number of the qubits n is relatively large, only a part of the units 320 (Σn.sub.gi<2.sup.(n-u)) can be allocated onto the device memories 234 and a remaining part of the units 320 (2.sup.(n-u)−Σn.sub.gi) is allocated onto the system memory 220., col 6:42-48; temporary buffers 332, 342, 352 may have the same size as the unit 2.sup.u , col 7:4-5),
Doi does not disclose, but Kim discloses
wherein a marked cacheline in the cache is to be prevented from being written back to memory (e.g., keeping the reserved line in the cache, instead of writing back to memory , 0026).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, providing the benefit of by keeping the reserved line in the cache, instead of writing back to memory and bring it back, is better in performance (see Kim, 0026) for managing an atomic facility cache write back controller. A reservation pointer pointing to the reserved line in the atomic facility cache data array (0015).
Doi in view of Kim does not disclose, but Hooker discloses
decoding the instance of the instruction at least having an indication of a start address of a buffer in cache and an indication of two or more cachelines of the buffer to modify a state for,; a state of two or more .. modified… at least in part, on the start address for the buffer (eg., 0027 - a single macro instruction, to direct a microprocessor to write back and invalidate a specified number of cache lines; 0029 - to perform operations which are specified by the macro instructions 121-123; 0058 - where the addresses of the specified number of cache lines includes an address; [0066] Fig 8 At block 808, the macro instruction is translated into a corresponding micro instruction sequence directing the microprocessor to perform a specified operation.);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, with Hooker, providing the benefit of enable a programmer to direct a microprocessor to perform write back and invalidate operations to flush a specified number of cache lines from its internal cache (see Hooker, 0002).
Claim 15 is rejected for reasons similar to Claim 3 above.
Claim 16 is rejected for reasons similar to Claim 4 above.
Claim 27 is rejected for reasons similar to Claim 26 above.
8. Claims 5, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Doi (US 10671550) and in view of Kim (US 20050289300) , Hooker (US 20040158681) and further in view of Jiao (US 20080282034)
Claim 5. Doi in view of Kim, Hooker does not disclose, but Jiao discloses
wherein the instruction is to cause a look up of the one or more cachelines in the cache based on a mask (e.g., a mask that flags that data as being dirty, 0099).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, Hooker, with Jiao providing the benefit of the data is locally kept on the L2 cache 210 (0099) improved configurations may be useful for modern stream graphics data processing applications where the memory subsystem supports a virtual stream processing pipeline in addition to conventional functions (0006).
Claim 17 is rejected for reasons similar to Claim 5 above.
9. Claims 6, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Doi (US 10671550) and in view of Kim (US 20050289300), Hooker (US 20040158681) and further in view of Hanley (US 20180165097)
Claim 6. Doi in view of Kim , Hooker does not disclose, but Hanley discloses
wherein an accelerator is to utilize the buffer as a scratchpad, wherein the instruction is to cause the accelerator to reclaim the scratchpad (e.g., FIG. 3, a distinct computing system, such as CPU architecture 300 is illustrated which provides increased security by reclaiming the silicon area of the former L2 cache, and using it for an equally or other sized static register file scratchpad 302, 0042).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, Hooker with Hanley providing the benefit of to eliminate or decrease vulnerability of multi-core multi-tenant environments, and for such a revised CPU architecture to provide techniques that allow such computing systems to rapidly do useful work, even with the presence of high read latency components (see Hanley, 0007).
Claim 18 is rejected for reasons similar to Claim 6 above.
10. Claims 7, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Doi (US 10671550) and in view of Kim (US 20050289300) Hooker (US 20040158681) and further in view of Hayter (US 20020174255)
Claim 7. Doi in view of Kim , Hooker does not disclose, but Hayter discloses
wherein the cache is a Level 2 (L2) cache, wherein the instruction is to cause a look up of the one or more cachelines in the L2 cache, and upon a miss in the L2 cache, no further operations associated with the instruction are to be performed (e.g., if the cache block is a miss in the L2 cache 14 and the L9CA signal is deasserted, the L2 cache 14 may not allocate storage for the cache block. , 0063).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, Hooker with Hayter providing the benefit of avoiding cache pollution (see Hayter, 0063).
Claim 19 is rejected for reasons similar to Claim 7 above.
11. Claims 8-10, 21, 22 are rejected under 35 U.S.C. 103 as being unpatentable over Doi (US 10671550) and in view of Kim (US 20050289300) Hooker (US 20040158681) and further in view of Godard (US 20150106567)
Claim 8. Doi in view of Kim , Hooker does not disclose, but Godard discloses
further comprising decode circuitry to decode the instruction into a plurality of store operations, wherein each of the plurality of store operations is to invalidate a corresponding cacheline in the cache (e.g., . Store operations are decoded by the decode stage 107 and issued for execution by the store unit 403, which issues a store request corresponding to the decoded store operation to the L1 Data Cache 115. , 0067 Fig. 4; store requests can be configured to store the cache line in the victim buffer (possibly newly allocated for the purpose), and then only later as capacity permits is the cache line as stored in the victim buffer moved to or merged into the cache arrays (banks). This can occur when a dirty cache line already in the cache arrays (banks) is written to. The new data is written to a cache line allocated in the victim buffer, with the rest of that cache line invalid., 0078).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, Hooker with Godard providing the benefit of a store unit that executes store operations. The store operations can be specified by instructions processed by the processor. The execution of a given store operation involves the generation of a store request communicated to the hierarchical memory system (see Godard, 0045).
Claim 9. Doi in view of Kim , Hooker does not disclose, but Godard discloses
wherein the memory comprises a main memory or a dynamic random access memory (e.g., main memory (or physical memory), which is typically implemented by DRAM memory , 0008).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, Hooker with Godard providing the benefit of a store unit that executes store operations. The store operations can be specified by instructions processed by the processor. The execution of a given store operation involves the generation of a store request communicated to the hierarchical memory system (see Godard, 0045).
Claim 10. Doi in view of Kim , Hooker does not disclose, but Godard discloses
wherein the cache comprises one or more of a level 1 cache, a level 2 cache, and a last level cache (e.g., FIG. 6 is a schematic high level diagram of an exemplary L1 Data Cache 115 , 0076).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, Hooker with Godard providing the benefit of a store unit that executes store operations. The store operations can be specified by instructions processed by the processor. The execution of a given store operation involves the generation of a store request communicated to the hierarchical memory system (see Godard, 0045).
Claim 21 is rejected for reasons similar to Claim 9 above.
Claim 22 is rejected for reasons similar to Claim 10 above.
12. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Doi (US 10671550) and in view of Kim (US 20050289300) and Hooker (US 20040158681) and Hanley (cited above) and further in view of Godard (US 20150106567)
Claim 20. Doi in view of Kim , Hooker and Hanley not disclose, but Godard discloses
further comprising decode circuitry to decode the instruction into a plurality of store operations, wherein each of the plurality of store operations is to invalidate a corresponding cacheline in the cache (e.g., . Store operations are decoded by the decode stage 107 and issued for execution by the store unit 403, which issues a store request corresponding to the decoded store operation to the L1 Data Cache 115. , 0067 Fig. 4; store requests can be configured to store the cache line in the victim buffer (possibly newly allocated for the purpose), and then only later as capacity permits is the cache line as stored in the victim buffer moved to or merged into the cache arrays (banks). This can occur when a dirty cache line already in the cache arrays (banks) is written to. The new data is written to a cache line allocated in the victim buffer, with the rest of that cache line invalid., 0078).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, , Hooker and Hanley, with Godard providing the benefit of a store unit that executes store operations. The store operations can be specified by instructions processed by the processor. The execution of a given store operation involves the generation of a store request communicated to the hierarchical memory system (see Godard, 0045).
Response to Arguments
Applicant's arguments filed 7/7/2025 have been fully considered but they are not persuasive.
For Claims 1 and 13, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
Doi discloses
the execution of the instruction to cause cachelines in the buffer to be modified, at least in part, on (e.g., the whole of the units 320 can be allocated onto the device memories 234 of the GPUs 230. On the other hand, when the number of the qubits n is relatively large, only a part of the units 320 (Σn.sub.gi<2.sup.(n-u)) can be allocated onto the device memories 234 and a remaining part of the units 320 (2.sup.(n-u)−Σn.sub.gi) is allocated onto the system memory 220., col 6:42-48; temporary buffers 332, 342, 352 may have the same size as the unit 2.sup.u , col 7:4-5),
Doi does not disclose, but Kim discloses
wherein a marked cacheline in the buffer is to be prevented from being written back to memory (e.g., keeping the reserved line in the cache, instead of writing back to memory , 0026).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the temporary buffer allocated on memory as disclosed by Doi, with Kim, providing the benefit of by keeping the reserved line in the cache, instead of writing back to memory and bring it back, is better in performance (see Kim, 0026) for managing an atomic facility cache write back controller. A reservation pointer pointing to the reserved line in the atomic facility cache data array (0015).
Applicant’s arguments for dependent claims are based on their respective base independent claims 1 and 13, which are addressed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135