DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 21 September 2026.
Applicant's election with traverse of Claims 1-7, drawn to a method in the reply filed on 21 September 2026 is acknowledged. The traversal is on the ground(s) that “the Office Action has not established that examination of both groups would impose the serious search and/or examination burden necessary to support restriction”. This is not found persuasive because the product as claimed can be made by another and materially different process (MPEP 806.05(f)) and therefore the method and product inventions are distinct.
The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to because:
Figures 1 and 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
The sheets of drawings should be numbered in consecutive Arabic numerals, starting with 1. The drawing sheet numbering must be clear and larger than the numbers used as reference characters to avoid confusion. The number of each sheet should be shown by two Arabic numerals placed on either side of an oblique line, with the first being the sheet number and the second being the total number of sheets of drawings, with no other marking. See Page(s) 1-7.
The view numbering format is improper because non-partial independent views are inexplicably designated alphanumerically instead of being consecutively numbered using Arabic numerals, leading to a confusing numbering scheme. Only partial views intended to form one complete view, on one or several sheets, must be identified by the same number followed by a capital letter. The different views must otherwise be numbered in consecutive Arabic numerals, starting with 1, independent of the numbering of the sheets and, if possible, in the order in which they appear on the drawing sheet(s). Refer to 37 CFR 1.84(u). See Figure(s) 3a-3b.
The reference characters are improperly and unnecessarily underlined. Reference characters (numerals are preferred), sheet numbers, and view numbers must be plain and legible, and must not be used in association with brackets or inverted commas, or enclosed within outlines, e.g., encircled. When necessary, such as indicating a surface or cross section, a reference character may be underlined and a blank space may be left in the hatching or shading where the character occurs so that it appears distinct. Lead lines must be executed in the same way as lines in the drawing. Refer to 37 CFR 1.84(p(1)), 1.84(p(3)), and 1.84(q). See Figure(s) 1-6.
The drawings contain lead lines of deficient line quality. All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. Lead lines must be executed in the same way as lines in the drawing. Refer to 37 CFR 1.84(l) and 1.84(q). See Figure(s) 1, 3a, 3b.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Method for Simultaneously Overmolding and Underfilling a Multi-Chip Package.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 and therefore depending claims 2-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites the limitations of “assembling at least two chips on a layer” and “applying mold compound…between the at least two chips and a redistribution layer in a single step”. The claim introduces two separate elements, “a layer” and “a redistribution layer”. However, there is only disclosure in the specification for either a layer or a redistribution layer for the chips to be mounted on and have mold compound flowed around interconnects between the chips and it ([0027-0029] “Similar to the method of FIG. 2, the method of FIG. 4 includes assembling 402 at least two chips onto a layer…The method of FIG. 5 differs from FIG. 4 in that the method includes assembling 502 the at least two chips on a redistribution layer”). For purposes of examination, the claim will be read as “assembling at least two chips on a redistribution layer” and “applying mold compound…between the at least two chips and the redistribution layer in a single step”
Claim 7 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites the limitation of “wherein the at least two chips are on a die-first wafer-level fanout package” and the parent claim recites the limitation of “applying mold compound…between the at least two chips and a redistribution layer in a single step”. The originally filed disclosure defines die-first wafer-level fanout packages to be chips encapsulated on a temporary carrier and then having a redistribution layer formed thereon, meaning that the mold compound is not applied between the chips and the redistribution layer in a single step ([0016] “In die-first fan-out wafer level packaging, the dies are singulated then placed face-down or face-up on a temporary carrier and secured by underfill and encapsulated by molding. The die-first fan-out wafer level packaging then includes forming a reconstituted carrier, and building the redistribution layer, releasing from the temporary carrier, and dicing the reconstituted carrier into individual packages.”).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 and therefore depending claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “efficient chip manufacturing” in claim 1 is a relative term which renders the claim indefinite. The term “efficient chip manufacturing” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claim recites the limitation of “wherein the at least two chips are on a die-first wafer-level fanout package” and the parent claim recites the limitation of “applying mold compound…between the at least two chips and a redistribution layer in a single step”. The originally filed disclosure defines die-first wafer-level fanout packages to be chips encapsulated on a temporary carrier and then having a redistribution layer formed thereon, meaning that the mold compound is not applied between the chips and the redistribution layer in a single step ([0016] “In die-first fan-out wafer level packaging, the dies are singulated then placed face-down or face-up on a temporary carrier and secured by underfill and encapsulated by molding. The die-first fan-out wafer level packaging then includes forming a reconstituted carrier, and building the redistribution layer, releasing from the temporary carrier, and dicing the reconstituted carrier into individual packages.”). Therefore, the limitations of the parent claim 1 are drawn to a different embodiment than that of the child claim 7.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al. (U.S. 2021/0335753).
Regarding Claim 1, Hsu et al., Figure 13 discloses a method of efficient chip manufacturing, the method comprising:
assembling at least two chips on a redistribution layer (chip 50a, chip 50b, redistribution layer 120, layer 140); and
applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the redistribution layer in a single step, thereby leaving a top of each of the at least two chips exposed, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer (mold compound 150. Please note that the Applicant does not provide a special definition to the term “envelops” and further, does not use the term in the originally filed disclosure. The definition of “envelops” is “surrounds”).
Regarding Claim 2, Hsu et al., Figure 19 further discloses the method of claim 1, further comprising: attaching a substrate (substrate 200).
Regarding Claim 3, Hsu et al. further discloses the method of claim 1, wherein the at least two chips are heterogenous chips ([0049]).
Regarding Claim 4, Hsu et al. further discloses the method of claim 1, wherein the at least two chips are chips of a same type ([0049]).
Regarding Claim 5, Hsu et al., Figure 19, further discloses the method of claim 1, wherein the at least two chips are a two dimensional (2.5d) package (chip 50a, chip 50b, package 100).
Regarding Claim 6, Hsu et al., Figure 19, further discloses the method of claim 1, wherein the at least two chips are a die-last wafer-level fanout package (RDL 120 is formed before chips 50a/b are mounted thereon, [0049],[0053]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (U.S. 2021/0335753) as applied to claim 1 above, and further in view of Pu et al. (U.S. 2009/0020864).
Regarding Claim 7, Hsu et al. does not explicitly disclose that the at least two chips are a die-first wafer-level fanout package. In the same field of endeavor, Pu et al. discloses applying mold compound to at least two chips on a layer including flowing around interconnects between the at least two chips and said layer in a single step, wherein the at least two chips are a die-first wafer-level fanout package (Pu et al., chips 20, layer 30, interconnects 26, mold compound 40, Figures 5 and 6,[0020][0031]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the at least two chips in a die-first wafer-level fanout package in Hsu et al. in view of Pu et al. in order to reduce via/trace misalignment from chip bumps and to provide robust copper interconnections (Pu et al., [0032]).
Response to Arguments
Applicant's arguments filed 16 January 2026 have been fully considered but they are not persuasive.
Regarding Claim 1, the Applicant argues that the Hsu ‘753 reference fails to disclose “a mold compound that envelops at least two lateral side surfaces of each of the at least two chips" because the "underfill material [of the Hsu reference] at most partially overlaps a single lateral side surface of each chip". However, the underfill material 150 of the Hsu reference completely envelops two lateral side surfaces of each the chips 50a/b (the two side surfaces facing each other and the bottom side surfaces facing the RDL 120) and partially envelops a third lateral side surface of each said chip (the chip lateral side surfaces that face away from each other). Furthermore, the term “envelop” is defined to mean “to surround”. Lastly, the term “envelop” does not appear in the originally filed disclosure and there is no special definition given to said term. Therefore the arguments are not persuasive.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Eguchi et al. (U.S. 2003/0071348) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, thereby leaving a top of each of the at least two chips exposed, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Eguchi et al. (U.S. 6,627,997) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, thereby leaving a top of each of the at least two chips exposed, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Chen et al. (8,093,722) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Ahn et al. (2012/0282735) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Meyer et al. (20130175686) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Lin et al. (8779599) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Mahajan et al. (2015/0171015) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Liou et al. (2015/0221577) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Lee et al. (2015/0311182) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Mehta et al. (2019/0279938) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Bhagavat et al. (2019/0326221) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Hsiung et al. (U.S. 2019/0181092) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Chen et al. (U.S. 2019/0131273) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Ganesan et al. (U.S. 2019/0363052) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Lin et al. (U.S. 2021/0035936) discloses assembling at least two chips on a layer; and applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and the layer in a single step, wherein the mold compound envelops at least two lateral side surfaces of each of the at least two chips and is disposed between the at least two chips and the redistribution layer.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance form a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Abbigale Boyle
Examiner, Art Unit 2899
/ABBIGALE A BOYLE/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
