Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responsive to the amendment filed on 01/21/2026. As directed by the amendments claims 10-12, 15, and 17-20 are amended. Claims 1-3, 5-20 are pending for examination.
Response to Arguments
Regarding the 35 U.S.C § 101 Rejection:
Applicant's further arguments see pg. 15, filed 01/21/2026, have been fully considered but they are not persuasive.
APPLICANT ARGUMENT:
Applicant argues, “the §101 rejections should be withdrawn in view of the amendments and the technological improvement of tiered re-evaluation to identify test escapes as coverage gaps undermining downstream fault coverage for an applied deployment”. Further, applicant argues, the new limitations of claims 10-11 and 11 and 20 “are not an abstract idea in the mental-process sense; they recite a particularized, hardware-test-oriented machine-learning workflow that improves circuit fault assessment and testing outcomes”. Therefore, applicant request withdrawal of the §101 rejection of claims 10-11, 15-16, and 18-20.
EXAMINER RESPONSE: Examiner respectfully disagree, applicant argument is not persuasive. Claims 10-11, 15-16, and 18-20 are not eligible under 35 U.S.C. §101. For example, under Step 2A, Prong 1, amended independent claim 10 is rejected under 35 US.C. § 101 because the claim recites the limitation of:
generate a graph from a netlist of a target hardware architecture having an applied domain-specific use-case, wherein a logic gate is represented in the graph as a node and a signal path between two logic gates is represented in the graph as an edge; and
evaluate functional criticality of unlabeled nodes of the graph for the applied domain-specific use-case
re-evaluate nodes classified as benign by the first tier of the k-tier GCN
recites a mental process of evaluation and judgement that can be all performed by the human mind with the aid of pen and paper. For example, a human can manually evaluate a netlist of a target hardware architecture and convert it to a graph and a human can manually evaluate nodes classified as benign and determine whether they are identified as test escapes/misclassified. Therefore, the additional elements of:
A system for fault criticality assessment comprising:
a storage device; and
a graph convolutional network (GCN) module comprising one or more processors configured to execute instructions stored in the storage device to implement a k-tier GCN having at least two tiers comprising a first tier and a second tier arranged in sequence, the execution of the instructions of the GCN module being configured to:
...using the first tier of the k-tier GCN...
... using the second tier of the k-tier GCN...
as disclosed above alone or in combination of the abstract idea are not sufficient to amount to significantly more than the judicial exception as they are mere generic computer functions being implemented with generic computer elements in a high level of generality to perform the disclosed abstract idea above.
Additionally, under Step 2A - Prong 2, amended claim 10 as presented does not integrate into a practical application under the second prong of the two-prong analysis since the claimed invention do not improves the functioning of a computer or improves another technology or technical field. Rather the claim recites the words "apply it" (or an equivalent) with the judicial exception, as discussed in MPEP § 2106.05(f), which the courts have identified such limitations do not integrate a judicial exception into a practical application (see MPEP 2106.04(d)(I)).
Lastly, under Step 2B amended claim 10 as presented include limitations that the courts have identified not to be enough to qualify as “significantly more” when recited in a claim with a judicial exceptions this includes: adding the words “apply it” (or equivalent) with the judicial exception; simply appending well-understood, routine, conventional activities previously known to the industry, specified at high level of generality, to the judicial exception; adding insignificant extra solution activity to the judicial exception and generally linking the use of the judicial exception to a particular environment or field of use (see MPEP 2106.05 (I)(A)).
Therefore for the above reason, claims 10-11, 15-16 and 18-20 are not directed to patent-eligible subject matter under 35 U.S.C § 101.
Regarding the 35 U.S.C § 112(f):
Applicant’s arguments, see pg. 15-16, filed 01/21/2026, with respect to claims 10 and 12 being interpreted under 35 U.S.C § 112(f) have been fully considered and are persuasive. The claim interpretation of claims 10 and 12 has been withdrawn.
Regarding the 35 U.S.C § 112(b):
Applicant's arguments pg. 16-17 filed 01/21/2026, have been fully considered but they are not persuasive. Claim 1 as presented for examination recites selecting nodes and performing a functional fault simulation test which does not disclose how these will reduce the computational simulation requirements as claimed. While applicant states “the specification provides concrete implementation detail explaining how computational cost is reduce” examiner will like to remind applicant that it is improper to import claim limitation from the specification, “though understanding the claim language may be aided by explanation contained in the written description, it is important not to import a claim limitations that are not part of the claim” (see MPEP 2111.01(II)).
Claims 2-3,5-9 are dependent on claim 1, and thus are rejected for reasons set forth in the rejection of claim 1. Claim 17, recites similar limitation to those of claim 1, and thus is rejected for reasons set forth in the rejection of claim 1. Accordingly, claims 1-3, 5-9 and 17 are not patent eligible under 35 U.S.C § 102(b) for the reason stated above.
Regarding the 35 U.S.C § 102:
Applicant’s arguments with respect to claims 10-11,15-16, and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding the 35 U.S.C § 103:
APPLICANT ARGUMENTS (Claim 1 & 5 pg. 18-23):
Applicant traverses the rejection under 103 for claim 1 and 5. Specifically applicant argues, the combination of reference is improper and the claimed limitation are not thought. Applicant states Ma teaches DTN not functional failure, Gebregiorgis doesn’t “fix” Ma’s label space problem (and actuality highlight it), and Guo does not reconcile the mismatch (even if Guo is about simulation/defect modeling). Further applicant argues Stuck at Fault for "performing a functional fault simulation of each node of the first set of nodes to determine functional criticality of stuck-at faults in that node" is not present in the Art.
EXAMINER RESPONSE: Examiner respectfully disagree. Under the broasted reasonable interpretation Ma teaching can be applied for fault criticality as Ma performs evaluation across full sets of node [0092] and Ma observability and controllability ([0027]) can be used to generate a modified graph/netlist for a circuit that can then be applied to manufacture the circuit with improved testability, and hence improved reliability (see Ma [0029]). In addition, examiner does not agree with applicant argument that “Gebregiorgis doesn’t “fix” Ma’s label space problem (and actuality highlight it)”, other than stating Gebregiorgis “underscores that Ma's DTN/non-DTN (testability difficulty) label is not a reliable substitute for functional criticality: DTN is about detectability/controllability/observability and test infrastructure, whereas "important fault" is about functional output degradation relative to an accuracy margin” applicant does not provide further details. Nonetheless, Gebregiorgis Abstract, Fig. 3 and pg. 6, right column, paras. 2-3 provide a method for fault injection based functional test methodology of neuromorphic circuits that "allow to significantly reduce the number of faults to be tested, and test time accordingly, without sacrificing the output accuracy or fault coverage", thus enabling to determine fault criticality in a node. Further, Guo reference was applied to teach performing a functional fault simulation to determine how malfunctioning transistors (i.e., nodes) could impact functionality of the overall cell design (i.e., performing a functional fault simulation), thereby requiring less exhaustive testing criteria “to accurately and precisely identify the root cause of defects within a cell” such that “production yields may be increased over time, as the cell fault analysis requires less time for completion” thus enabling “rectification of systemic defects within cells that decrease fabrication yields with minimal processing-resource utilization for testing cells and identifying defects” (Guo [0023-24] and [0026-27]). Therefore, it would be obvious to combine Gebregiorgis and Guo with Ma, so that the simulation in Ma to perform a functional fault simulation of each node with minimal testing thereby reducing computational simulation requirements by eliminating full fault simulation of all potential faults. Lastly, regarding the arguments “Stuck at Fault for "performing a functional fault simulation of each node of the first set of nodes to determine functional criticality of stuck-at faults in that node" is not present in the Art” examiner, disagree. Guo [0024] teaches “"stuck-at" fault models (e.g., identifying defects that do not permit a transistor to change output values)”.
Therefore for the above reason, claims 1 and 5 are not directed to patent-eligible subject matter under 35 U.S.C § 103.
APPLICANT ARGUMENTS (Claim 2 pg. 23-24):
Applicant argues claim 2 rejection, “even accepting Guo2's end-of-pipeline negative labeling, the Office has not identified where Guo2 teaches the claimed netlist-derived graph and k-tier GCN node-level workflow-i.e., converting a netlist to a graph with gates as nodes and signal paths as edges, and evaluating unlabeled nodes of that graph with a GCN trained on labels derived from functional fault simulation. Thus, Guo2's statement about how remaining samples may be treated at the end of an evaluation process does not supply the missing teachings needed to transform Ma's DTN/non-DTN predictor into the claimed functional-failure criticality predictor, nor does it cure the claim's specific netlist-graph / GCN limitations. Further, applicant submit the rejection to be evaluated on the actual applied references and their articulated motivation to combine.
EXAMINER RESPONSE: Examiner respectfully disagree. Regarding claim 2, Ma [0052], Lines 18-21 teaches using the trained GCN to make DTN/non-DTN label predictions for an input netlist, which implies that the input netlist-graph nodes are unlabeled. Further, Ma [0092] teaches a multi-stage graph convolutional network (i.e., a k-tier GCN) may be utilized to make the predictions, thus Ma teaches “evaluating functional criticality of unlabeled nodes of a graph using the k-tier GCN, wherein the graph is generated from a corresponding netlist, wherein nodes of the graph classified as critical by GCNs of the k-tier GCN are labeled as critical nodes and nodes not labeled as critical nodes are labeled as benign”. While Ma does not explicitly teach “nodes not labeled as critical nodes after completing all evaluations are labeled as benign” (emphasis added). Nonetheless, Guo L. para. [0050-0051] teaches that remaining unlabeled samples without risk labels may be classified as negative sample. Therefore, Guo L. is relied upon to teach nodes not labeled as critical nodes may be label as beginning.
Accordingly, claim 2 is not patent eligible under 35 U.S.C § 103 for the reason stated above.
APPLICANT ARGUMENTS (Claim 2 pg. 23-24):
Applicant argues claim 3, , specially applicant argues “the Office still must show why Kunal's general teaching would be applied in this specific context and in combination with Ma/Gebregiorgis/Guo to arrive at the claimed dependent limitation-especially where Ma itself teaches a directed graph representation aligned with signal flow and levelization. Accordingly, claim 3 remains unpatentable only by hindsight reconstruction, and withdrawal of the rejection of claim 3 is respectfully requested.”
EXAMINER RESPONSE: Ma claim 16 teaches “generating a levelized netlist of a circuit from a graph representation of the levelized netlist” while Ma does not explicitly teaches “wherein the graph is an undirected netlist-graph” as recited in claim 3 of the instant application; Kunal analogous in the art explicitly disclose representing an element-level circuit netlist as an undirected bipartite graph (emphasis added - see Kunal pg. 2, right col., sec: C. Graph representation of the netlist, para 1). Further, examiner demonstrated that Ma/Gebregiorgis/Guo/ Guo L./Kunal are analogues art, and clearly emphasize how it would been obvious to a person ordinary skill in the art before the effective filling date of the claimed invention to have modified the invention of Ma with the teaching of Gebregiorgis/Guo/ Guo L./Kunal because doing so, it’s possible to reduce the testable fault by more than 2X on average, while maintaining high fault coverage (Gebregiorgis pg. 2, left colm., para.2), it would lead to an expected reduction in the amount of processing resources and time required to perform defect/fault analysis (Guo, [0023]), it would lead to an expected improvement in classification accuracy of the trained model (Guo L. [0021]) and it would lead to an expected improvement in the scalability of circuit classification (Kunal, pg. 6, right col., para. 1). Furthermore, examiner respectfully disagree, the combination of Ma/Gebregiorgis/Guo/ Guo L./Kunal does not represent “impermissible hindsight”, because Ma/Gebregiorgis/Guo/ Guo L./Kunal are all in the same field of endeavor (i.e., machine learning). Applicants may argue that the examiner’s conclusion of obviousness is based on improper hindsight reasoning. However, “[a]ny judgment on obviousness is in a sense necessarily a reconstruction based on hindsight reasoning, but so long as it takes into account only knowledge which was within the level of ordinary skill in the art at the time the claimed invention was made and does not include knowledge gleaned only from applicant’s disclosure, such a reconstruction is proper.” (See MPEP 2145 subsection X.A).
Accordingly, claim 3 is not patent eligible under 35 U.S.C § 103 for the reason stated above.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-3, 5-9 and 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, recites “thereby reducing computational simulation requirements by eliminating full fault simulation of all potential faults”. However, it’s not clear how the computational cost is being reduces since the claim as presented disclose selecting a set and testing without providing further details into how these are used to reduce the computational cost as claimed. Further, the claim as presented does not teach/suggest the set is only limited to the selected set, testing being performed on the rest of the circuit, evaluating the nodes to find the critical ones or only simulating the critical nodes which will in the end save computational is never claimed. For purpose of examination examiner interprets the limitation as performing functional simulation in order to reduce resource consumptions during testing.
Claims 2-3 and 5-9 are dependent on claim 1, and thus are rejected for reasons set forth in the rejection of claim 1.
Claim 17, recites similar limitation to those of claim 1, and thus is rejected for reasons set forth in the rejection of claim 1.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 10-11, 15-16 and 18-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1:
Claims 10-14 are a system type claim. Claim 15-16 and 18-20 are a method type claim. Therefore, claims 10-16 and 18-20 are directed to either a process, machine, manufacture or composition of matter.
Regarding claim 10: 2A Prong 1:
generate a graph from a netlist of a target hardware architecture having an applied domain-specific use-case, wherein a logic gate is represented in the graph as a node and a signal path between two logic gates is represented in the graph as an edge; and (mental process – of generating a graph from a netlist can be performed by the human mind with the help of pen and paper (e.g., evaluation & judgment). For example, a human can manually evaluate a netlist of a target hardware architecture and convert it to a graph).
evaluate functional criticality of unlabeled nodes of the graph for the applied domain-specific use-case (mental process – of performing evaluation in two tier to evaluate the functional criticality of nodes can be performed by the human mind with the help of pen and paper (e.g., evaluation & judgment). For example, a human can manually evaluate nodes classified as benign and determine whether they are identified as test escapes/misclassified).
re-evaluate nodes classified as benign by the first tier of the k-tier GCN (mental process – of performing evaluation in two tier to evaluate the functional criticality of nodes can be performed by the human mind with the help of pen and paper (e.g., evaluation & judgment). For example, a person could manually evaluate nodes classified as benign and determine whether they are identified as test escapes/misclassified).
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
A system for fault criticality assessment comprising: (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
a storage device; and (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
a graph convolutional network (GCN) module comprising one or more processors configured to execute instructions stored in the storage device to implement a k-tier GCN having at least two tiers comprising a first tier and a second tier arranged in sequence, the execution of the instructions of the GCN module being configured to: (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
...using the first tier of the k-tier GCN... (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
... using the second tier of the k-tier GCN... (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
The additional elements as disclosed above alone or in combination do not integrate the judicial exception into practical application as they are mere insignificant extra solution activity in combination of generic computer functions being implemented with generic computer elements in a high level of generality to perform the disclosed abstract idea above.
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
A system for fault criticality assessment comprising: (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
a storage device; and (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
a graph convolutional network (GCN) module comprising one or more processors configured to execute instructions stored in the storage device to implement a k-tier GCN having at least two tiers comprising a first tier and a second tier arranged in sequence, the execution of the instructions of the GCN module being configured to: (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
...using the first tier of the k-tier GCN... (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
... using the second tier of the k-tier GCN... (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
The additional elements as disclosed above in combination of the abstract idea are not sufficient to amount to significantly more than the judicial exception as they are mere insignificant extra solution activity in combination of generic computer functions being implemented with generic computer elements in a high level of generality to perform the disclosed abstract idea above.
Regarding claim 11: the rejection on claim 10 is incorporated. 2A Prong 1:
perform a topological sorting of the graph; (mental process – of perform a topological sorting of a graph can be performed by the human mind with the help of pen and paper (e.g., evaluation and judgement ). For example, person could manually evaluate the netlist-graph and then generate a sorted list).
select a root node; (mental process – of select a root node can be performed by the human mind with the help of pen and paper (e.g., evaluation and judgement). For example, a person could manually evaluate the netlist-graph and then select the root node).
traverse nodes in topological order; and (mental process – of traverse nodes in topological order can be performed by the human mind with the help of pen and paper (e.g., evaluation and judgement). For example, a person could traverse nodes in a graph in topological order).
select candidate nodes whose minimum hop-count distance along edges of the graph from the root node exceeds a predetermined radius of coverage, wherein the selected candidate nodes are selected for ground-truth collection used to train the k-tier GCN, and wherein the selected candidate nodes include nodes classified as benign by the first tier and provided to the second tier for the re-evaluation (mental process – of select candidate nodes whose minimum hop-count distance along edges of the graph from the root node exceeds a predetermined radius of coverage, wherein the selected candidate nodes are selected for ground-truth collection used to train the k-tier GCN, and wherein the selected candidate nodes include nodes classified as benign by the first tier and provided to the second tier for the re-evaluation can be performed by the human mind with the help of pen and paper (e.g., evaluation and judgement)).
2A Prong 2 and 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
wherein the execution of the instructions of the GCN module is further configured to: (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
Regarding claim 15: 2A Prong 1:
A method for fault criticality assessment, comprising: generating a graph from a netlist of a target hardware architecture having an applied domain-specific use-case, wherein a logic gate is represented in the graph as a node and a signal path between two logic gates is represented in the graph as an edge; and (mental process – of generating a graph from a netlist can be performed by the human mind with the help of pen and paper (e.g., evaluation & judgment). For example, a human can manually evaluate a netlist of a target hardware architecture and convert it to a graph).
evaluating functional criticality of unlabeled nodes of the graph for the applied domain-specific use-case and (mental process – of performing evaluation in two tier to evaluate the functional criticality of nodes can be performed by the human mind with the help of pen and paper (e.g., evaluation & judgment). For example, a human can manually evaluate nodes classified as benign and determine whether they are identified as test escapes/misclassified).
re-evaluating nodes classified as benign by the first tier of the k-tier GCN (mental process – of performing evaluation in two tier to evaluate the functional criticality of nodes can be performed by the human mind with the help of pen and paper (e.g., evaluation & judgment). For example, a person could manually evaluate nodes classified as benign and determine whether they are identified as test escapes/misclassified).
2A Prong 2 and 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
...using a first tier of a k-tier graph convolutional network (GCN) having at least two tiers comprising the first tier and a second tier arranged in sequence... (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
...using the second tier of the k-tier GCN to... (This is directed to using computers or other machinery merely as a tool to perform an existing process. See MPEP 2106.05(f)).
Regarding claim 16: the rejection on claim 15 is incorporated.2A Prong 1:
further comprising extracting dataflow features and functional features from the netlist and providing the dataflow features and functional features as inputs to the k-tier GCN (mental process – of extracting dataflow features and functional features from the netlist and providing the dataflow features and functional features as inputs to the k-tier GCN can be performed by the human mind with the help of pen and paper (e.g., evaluation & judgment ). For example, a human can evaluate a netlist and extract dataflow features and functional features and provide the dataflow features and functional features as inputs to a machine learning model).
2A Prong 2 and 2B: None.
Regarding claim 18: the rejection on claim 16 is incorporated.2A Prong 1: None.
2A Prong 2 and 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
wherein the netlist-graph used for providing the dataflow features and functional features is the same graph as the graph generated from the netlist of the target hardware architecture having the applied domain-specific use-case (This is directed to restricting the abstract idea to a particular technological environment. See MPEP 2106.05(h)).
Regarding claim 19: the rejection on claim 15 is incorporated.2A Prong 1: None.
2A Prong 2 and 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
wherein the k-tier GCN is trained using a netlist-graph generated from a different netlist than the netlist-graph generated from the netlist and used for evaluating the functional criticality of nodes (This is directed to restricting the abstract idea to a particular technological environment. See MPEP 2106.05(h)).
Regarding claim 20: the rejection on claim 15 is incorporated.2A Prong 1:
Wherein the method further comprises: performing a topological sorting of the graph; (mental process – of perform a topological sorting of a graph can be performed by the human mind with the help of pen and paper (e.g., evaluation and judgement ). For example, person could manually evaluate the netlist-graph and then generate a sorted list).
selecting a root node; (mental process – of select a root node can be performed by the human mind with the help of pen and paper (e.g., evaluation and judgement). For example, a person could manually evaluate the netlist-graph and then select the root node).
traversing nodes in topological order; and (mental process – of traverse nodes in topological order can be performed by the human mind with the help of pen and paper (e.g., evaluation and judgement). For example, a person could traverse nodes in a graph in topological order).
selecting candidate nodes whose minimum hop-count distance along edges of the graph from the root node exceeds a predetermined radius of coverage, wherein the selected candidate nodes are selected for ground-truth collection used to train the k-tier GCN, and wherein the selected candidate nodes include nodes classified as benign by the first tier and provided to the second tier for the re-evaluation (mental process – of select candidate nodes whose minimum hop-count distance along edges of the graph from the root node exceeds a predetermined radius of coverage, wherein the selected candidate nodes are selected for ground-truth collection used to train the k-tier GCN, and wherein the selected candidate nodes include nodes classified as benign by the first tier and provided to the second tier for the re-evaluation can be performed by the human mind with the help of pen and paper (e.g., evaluation and judgement)).
2A Prong 2 and 2B: None.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable Ma et al. US 2020/0151288 A1 (herein after Ma) in view of Gebregiorgis et al. “Testing of Neuromorphic Circuits: Structural vs Functional” as disclosed in the Information Disclosure Statement (IDS) dated 01/29/2021 in further view of Guo et al. US 2021/0240905 A1 (hereinafter Guo).
Regarding claim 1:
Ma teaches A method for fault criticality assessment, comprising: converting a netlist of a target hardware architecture having an applied domain-specific use-case to a netlist-graph, wherein a logic gate is represented in the netlist-graph as a node and a signal path between two logic gates is represented in the netlist-graph as an edge (Ma [0050] teaches the GCN designed to work directly on graphs and leverage their structural information. Further, claim 1 and [0052] teaches forming/generating a graph representation from a netlist for the circuit, where “each logic block is represented as a node and the edges of the graph represent signal paths between logic blocks” and [0028] teaches the generated graph “for a circuit that can then be applied to manufacture the circuit with improved testability”, thus having an applied domain-specific use case within the domain of Electronic Design Automation (see [0003][0097][0149])).
selecting nodes for a first set of nodes from the netlist-graph,
performing a functional simulation of each node of the first set of nodes to determine functional criticality in that node,
evaluating, with a k-tier graph convolutional network (GCN) having at least two tiers arranged in sequence, the functional criticality of nodes, wherein a first tier of the k-tier GCN classifies nodes as critical or benign and a second tier of the k-tier GCN identifies test escapes to identify misclassified nodes; (Ma [0092] teaches evaluating the functionality criticality of the nodes using a multi-stage graph convolutional network (i.e., a k-tier graph convolutional network). Specifically, Ma teaches how at each stage (i.e., first tier of the k-tier GCN) the multi-stage graph convolutional network filter out negative cases with high confidence, and passes the remaining nodes to the next stage (i.e., second tier of the k-tier GCN). Further, Ma teaches [0052] teaches using a trained GCN to make predictions about whether nodes in the input netlist are difficult to test nodes (i.e., critical) or not (i.e., benign) and [0092] teaches the next stage (i.e., second tier of the k-tier GCN) is used to filter out some of the negative classified nodes and address the undesirable performance effects associated with data imbalance to reduce bias toward the majority class, thereby imposing a larger penalty for misclassifying positive nodes).
labeling the first set of nodes of the netlist-graph based on the functional simulation, each node of the first set of nodes being labeled with a label indicating the functional criticality for that node is benign or critical; and ([0052] teaches that graph nodes may be assigned a label indicating that the node is “hard” to test (i.e., a label indicating the functional criticality for that node is benign or critical) for training purposes based on a simulation (i.e., a functional simulation)).
training a k-tier graph convolutional network (GCN), where k ≥2, the k-tier GCN learning from the labels of the first set of nodes to predict labels of unlabeled nodes of the netlist-graph, wherein a first GCN of the k-tier GCN is trained to identify criticality of nodes and a second GCN of the k-tier GCN is trained to identify test escapes (Ma [0052] teaches using the labeled nodes of the netlist graph to train a graph convolutional network to make predictions about whether unlabeled netlist graph nodes are difficult to test or not (i.e., to identify criticality of nodes); [0090] and [0092] teach using a multi-stage graph convolutional network (i.e., a k-tier graph convolutional network where k ≥ 2) to filter out some of the negative classified nodes and address the undesirable performance effects associated with data imbalance to reduce bias toward the majority class, thereby imposing a larger penalty for misclassifying positive nodes (i.e., a second model is trained to identify and reduce test escapes that were classified by a first model)).
Ma does not explicitly teach: …the first set of nodes having a fewer number of nodes than that of the netlist-graph; performing a functional fault simulation of … nodes to determine functional criticality of stuck-at faults in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality,fault simulation.
Nevertheless, Gebregiorgis analogues in the art teaches:
…the first set of nodes having a fewer number of nodes than that of the netlist-graph (Fig. 2(a) teach selecting a submodule having a fewer number of nodes of a DUT Gate-level netlist graph for which fault injection simulation is to be performed).
performing a functional fault simulation of …nodes to determine functional criticality in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality, thereby reducing computational simulation requirements, thereby reducing computational simulation requirements by eliminating full fault simulation of all potential faults (Gebregiorgis Fig. 3 and pg. 6, left column, para. 2-3, teaches fault injection based functional test methodology of neuromorphic circuits. Para. 2 specifically teaches detect and classify “important faults” in a neuromorphic circuit (NC) by utilizing “real input image dataset” in order to reduce the “search space for test patterns able to detect the important faults and hence, reduces the associated test cost”, and para. 2 teaches the overall flow of the functional testing methodology. Further, Gebregiorgis emphasizes, “The proposed test methodologies allow to significantly reduce the number of faults to be tested, and test time accordingly, without sacrificing the output accuracy or fault coverage” (see Gebregiorgis Abstract, line 11-14).
Gebregiorgis is also in the same field of endeavor as Ma (machine learning). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the functionality of testing important and non-important faults that reduce resource consumption as being disclosed and taught by Gebregiorgis, in the system taught by Ma to yield the predictable results of reducing “the testable faults by more than 2X on average, while maintaining high fault coverage” (see Gebregiorgis pg. 2, left colm., para. 2).
Gebregiorgis does not teach performing a functional fault simulation of …nodes to determine functional criticality of stuck-at faults in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality... and labeling the first set of nodes … based on the functional fault simulation…
However, Guo analogues in the art teaches:
performing a functional fault simulation of …nodes to determine functional criticality of stuck-at faults in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality, thereby reducing computational simulation requirements of functionality of the target hardware architecture); [0024] teaches the use of stuck-at fault models. To add, [0023] Lines 35- 39 teaches the advance cell aware fault model requires less exhaustive testing criteria “to accurately and precisely identify the root cause of defects within a cell” such that “production yields may be increased over time, as the cell fault analysis requires less time for completion” and [0027] lines 3-6 further teaches the advance cell aware fault model enables “rectification of systemic defects within cells that decrease fabrication yields with minimal processing-resource utilization for testing cells and identifying defects” this suggest, the cell aware fault model enables to perform functional simulation with minimal testing which could lead to reduction of computational simulation requirements).
labeling the first set of nodes … based on the functional fault simulation … (Guo [0023] and [0026] teach pinpointing (i.e., labeling) a candidate defect as a particular transistor (i.e., node) or a particular region within a cell design (i.e., a set of nodes) based on the fault model’s simulation).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Ma and Gebregiorgis with the above teaching of Guo because doing so would lead to an expected reduction in the amount of processing resources and time required to perform defect/fault analysis (Guo, [0023]).
Regarding claim 5:
Ma, Gebregiorgis and Guo teach The method of claim 1. Ma specifically teaches wherein selecting nodes for the first set of nodes comprises randomly selecting the nodes for the first set of nodes (Ma [0032] and [0058] teach randomly selecting nodes (i.e., to form a first set of nodes) to be used for the GCN training process).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ma, Gebregiorgis, Guo in further view of Guo, L. US 2020/0210899 A1 (hereinafter Guo, L.).
Regarding claim 2:
Ma, Gebregiorgis, and Guo teach The method of claim 1. Ma specifically teaches evaluating functional criticality of unlabeled nodes of a graph using the k-tier GCN, wherein the graph is generated from a corresponding netlist, wherein nodes of the graph classified as critical by GCNs of the k-tier GCN are labeled as critical nodes and nodes not labeled as critical nodes are labeled as benign (Ma [0052], Lines 18-21 teach using the trained GCN to make DTN/non-DTN label predictions for an input netlist, which implies that the input netlist-graph nodes are unlabeled; [0092] teaches that a multi-stage graph convolutional network (i.e., a k-tier GCN) may be utilized to make the predictions).
The combination of Ma, Gebregiorgis, and Guo does not explicitly teach: … and nodes not labeled as critical nodes after completing all evaluations are labeled as benign.
However, in the analogous art, Guo, L. teaches: …and nodes not labeled as critical nodes after completing all evaluations are labeled as benign ([0050-0051] teaches that remaining unlabeled samples without risk labels (i.e., nodes not labeled as critical nodes) may be classified as negative samples (i.e., labeled as benign)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Ma, Gebregiorgis and Guo with the above teaching of Guo, L. because doing so would lead to an expected improvement in classification accuracy of the trained model (Guo, L., [0021]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ma, Gebregiorgis, Guo, Guo, L., in further view of Kunal et al. “GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits” (hereinafter Kunal).
Regarding claim 3:
Ma, Gebregiorgis, Guo, and Guo, L., teach The method of claim 2. Ma specifically teaches wherein the corresponding netlist is the netlist of the target hardware architecture having the applied domain-specific use-case, [0028] teaches the corresponding netlist is the netlist “for a circuit that can then be applied to manufacture the circuit with improved testability”, thus having an applied domain-specific use case within the domain of Electronic Design Automation (see [0003])).
The combination of Ma, Gebregiorgis, Guo, and Guo, L., does not explicitly teach: …wherein the graph is an undirected netlist-graph.
However, in the analogous art, Kunal teaches that it was well known at the time of the invention to represent a netlist as a graph wherein the graph is an undirected netlist-graph (Page 2, Right column, Section C, Paragraph 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Ma, Gebregiorgis, Guo, and Guo, L., with the above teaching of Kunal because doing so would lead to an expected improvement in the scalability of circuit classification (Kunal, Page 6, Right column, Paragraph 1).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ma, Gebregiorgis, Guo in further view of Deo et al. US 2019/0147371 A1 (hereinafter Deo), and Taherkhani et al. “AdaBoost-CNN: An adaptive boosting algorithm for convolutional neural networks to classify multi-class imbalanced datasets using transfer learning” (hereinafter Taherkhani).
Regarding claim 7:
Ma, Gebregiorgis, and Guo teach The method of claim 1. Ma specifically teaches wherein training the k-tier GCN comprises: partitioning the first set of nodes into at least two training sets and a validation set; (Ma [0069-0070] teaches that the training data nodes may be partitioned into batches (i.e., at least two training sets) with a different batch used for validation (i.e., a validation set))
extracting dataflow features and functional features from the netlist (Ma [0055-0056] teach that the node embeddings extracted from a netlist-derived graph preserve the relevant properties of the node (i.e., functional features), which includes connectivity (i.e., dataflow features);
generating a first GCN for the netlist-graph (Ma [0003] Lines 35-38 and [0052]);
training the first GCN to predict criticality of nodes using the training set, the dataflow features, and the functional features (Ma [0055-0056] teaches inputting the node embeddings (i.e., embeddings extracted from a netlist-derived graph that preserve the relevant properties of the node (i.e., functional features), which includes connectivity (i.e., dataflow features)) as features to a GCN model for training and that the model is trained based on the set of training data).
The combination of Ma, Gebregiorgis and Guo does not explicitly teach: for each training set of the at least two training sets: generating a first GCN for the netlist-graph; training the first GCN to predict criticality of nodes using the training set, …; evaluating the first GCN using the validation set to determine a number of test escapes; store the test escapes as part of a set of test escape nodes; and after evaluating a first generated first GCN, when the number of test escapes is less than a lowest number of test escapes of a previously generated first GCN, store the first GCN as a best first GCN.
However, in the analogous art, Deo teaches:
wherein training the k-tier GCN comprises: partitioning the first set of nodes into at least two training sets and a validation set ( Deo [0022] and [0030]);
for each training set of the at least two training sets:
generating a first GCN for the netlist-graph (Deo [0030] teaches that multiple models are generated from corresponding to different portions of training data);
training the first GCN to predict criticality of nodes using the training set, … (Deo [0030] teaches training a model with different portions of training data to generate multiple trained models);
evaluating the first GCN using the validation set to determine a number of test escapes (Deo [0035]; [0037] teaches that the evaluation is based on a recall score, which conveys the number of false negatives (i.e., test escapes));
after evaluating a first generated first GCN, when the number of test escapes is less than a lowest number of test escapes of a previously generated first GCN, store the first GCN as a best first GCN (Deo [0037] teaches selecting a model based on evaluation metrics which include a recall score, which implies selecting a model that minimizes the number of false negatives (i.e., test escapes); [0017]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Ma, Gebregiorgis and Guo with the above teaching of Deo because doing so would lead to an expected improvement in system prediction performance (Deo, [0037]).
The combination of Ma, Gebregiorgis, Guo and Deo does not explicitly teach: store the test escapes as part of a set of test escape nodes.
However, in the analogous art, Taherkhani teaches: store the test escapes as part of a set of test escape nodes (Taherkhani Page 353, Left column, Section 3, Paragraph 3 teaches that the training sample weights (i.e., which include the higher weights for incorrectly predicted samples, such as the test escapes) are stored in a data weight vector D (i.e., a set of test escape nodes)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Ma, Gebregiorgis, Guo and Deo with the above teaching of Taherkhani because doing so would lead to an expected improvement in the ability to deal with large imbalanced datasets with high accuracy (Taherkhani, Abstract).
Regarding claim 8:
Ma, Gebregiorgis, Guo, Deo and Taherkhani teach The method of claim 7. Ma specifically teaches Ma further teaches: training the second GCN to identify the test escapes using a set of benign nodes from the first set of nodes, , the dataflow features, and the functional features; ( Ma [0055-0056] teaches inputting the node embeddings (i.e., embeddings extracted from a netlist-derived graph that preserve the relevant properties of the node (i.e., functional features), which includes connectivity (i.e., dataflow features)) as features to a GCN model for training and that the model is trained based on the set of training data; ); [0092] teaches training a multi-stage GCN where in each stage one GCN is trained to filter out some of the negative classified nodes and thereby impose a larger penalty for misclassifying positive nodes (i.e., a second model is trained to identify and reduce test escapes that were classified by a first model)).
Neither Ma, Gebregiorgis , Guo or Deo teach wherein training the k-tier GCN further comprises: after completing a specified number of iterations for the first GCN, assigning the best first GCN as a second GCN and training the second GCN to identify the test escapes using a set of benign nodes from the first set of nodes, the set of test escape nodes,…
Nevertheless, Taherkhani further teaches:
wherein training the k-tier GCN further comprises: after completing a specified number of iterations for the first GCN, assigning the best first GCN as a second GCN; and (Page 354, Figure 1; Page 353, Left column, Section 3, Paragraph 4 teaches training the first model for one or more epochs (i.e., a specified number of iterations); Page 353, Right Column, Paragraph 2 teaches transferring the parameters of the trained model to the subsequent model (i.e., assigning the best first model parameters as the second model) such that it learns using the transferred parameters).
training the second GCN to identify the test escapes using a set of benign nodes from the first set of nodes, the set of test escape nodes, … (Page 354, Figure 1 and Table 1, and Page 353, Right column, Paragraph 3 teach training the subsequent models using the updated data weights from the previous model (i.e., which includes the weights of the negative data samples (i.e., the set of benign nodes from the first set of nodes) and the subset of incorrectly classified positive training samples (i.e., the set of test escape nodes))).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ma, Gebregiorgis , Guo, Deo, Taherkhani, in further view of Kunal.
Regarding claim 9:
Ma, Gebregiorgis, Guo, Deo, and Taherkhani teach The method of claim 7. Ma specifically teaches training the second GCN to identify the test escapes using , the dataflow features, and the functional features (Ma [0055-0056] teaches inputting the node embeddings (i.e., embeddings extracted from a netlist-derived graph that preserve the relevant properties of the node (i.e., functional features), which includes connectivity (i.e., dataflow features)) as features to a GCN model for training and that the model is trained based on the set of training data; ); [0092] teaches training a multi-stage GCN where in each stage one GCN is trained to filter out some of the negative classified nodes and thereby impose a larger penalty for misclassifying positive nodes (i.e., a second model is trained to identify and reduce test escapes that were classified by a first model));
training the third GCN to identify the second test escapes using a set of benign nodes from the first set of nodes, , the dataflow features, and the functional features (Ma [0055-0056] teaches inputting the node embeddings (i.e., embeddings extracted from a netlist-derived graph that preserve the relevant properties of the node (i.e., functional features), which includes connectivity (i.e., dataflow features)) as features to a GCN model for training and that the model is trained based on the set of training data); [0092] and Figure 13 teach training a multi-stage GCN (i.e., including a third GCN) where in each stage one GCN is trained to filter out some of the negative classified nodes and thereby impose a larger penalty for misclassifying positive nodes (i.e., a third model is trained to identify and reduce test escapes that were classified by the previous model));
Taherkhani further teaches: wherein training the k-tier GCN further comprises:
after completing a specified number of iterations for the first GCN, assigning the best first GCN as a second GCN (Taherkhani Page 354, Figure 1; Page 353, Left column, Section 3, Paragraph 4 teaches training the first model for one or more epochs (i.e., a specified number of iterations); Page 353, Right column, Paragraph 2 teaches transferring the parameters of the trained model to the subsequent model (i.e., assigning the best first model parameters as the second model) such that it learns using the transferred parameters);
training the second GCN to identify the test escapes using the set of test escape nodes,… (Taherkhani Page 354, Figure 1 and Table 1, and Page 353, Right column, Paragraph 3 teach training the subsequent models using the updated data weights from the previous model to improve the predictions (i.e., which includes the subset of weights for the incorrect training samples and those weighted as test escapes));
evaluating the second GCN using the validation set to determine a second number of second test escapes (Taherkhani Page 353, Right column, Paragraph 2 teaches using the output vector of the subsequent model to update the data weights using Equation 1. Page 353, Left column, Section 3, Paragraph 4 teaches using Equation 1 to evaluate each trained model using the training samples (i.e., also acting as the validation set) and increasing the weight of training samples that have an incorrect prediction by the model (i.e., determine a second number of second test escapes));
storing the second test escapes as part of a second set of test escape nodes (Taherkhani Page 353, Left column, Section 3, Paragraph 3 teaches that the training sample weights (i.e., which includes the subset of higher weights for incorrectly predicted samples, such as the test escapes) are stored in a data weight vector D); and
after evaluating a first generated second GCN, when the second number of second test escapes is less than a lowest number of second test escapes of a previously generated second GCN, store the second GCN as the best second GCN, after completing a specified number of iterations for the second GCN, assigning the best second GCN as a third GCN; and (Taherkhani Page 353, Right column, Paragraph 2 teaches transferring the parameters of the previous trained model to generate a first subsequent model; Page 353, Right column, Paragraph 3 and Page 354, Figure 1 teach retraining this first model (i.e., a first generated second GCN) to generate a second model (i.e., a second generated second GCN) using the data item weights that were calculated based on the output of the previous model (i.e., the first generated second GCN) in order to reduce the number of incorrect predictions (i.e., including the number of test escapes) and then assigning this improved model as the first model of the next stage (i.e., assigning the best second GCN as a third GCN after completing a specified number of iterations)).
training the third GCN to identify the second test escapes using a set of benign nodes from the first set of nodes, the second set of second test escape nodes, … (Taherkhani Page 353, Right column, Paragraph 2 and Page 354, Figure 1 teach training the third model using the updated data weights in order to correct the incorrect predictions of the previous model (i.e., including the subset of test escapes) using the entire training set with accompanying data item weights (i.e., including the subset of benign nodes and the second subset of second test escape nodes weighted based on the previous model output)).
The combination of Ma, Gebregiorgis, Guo Deo, and Taherkhani does not explicitly teach: wherein the first set of nodes are further partitioned into a second validation set; evaluating the second GCN using the second validation set […].
However, in the analogous art, Kunal teaches: wherein the first set of nodes are further partitioned into a second validation set (Kunal Page 5, Left column, Paragraph 1, Lines 16-24 teaches using a five-fold cross validation for the GCN (i.e., the data is partitioned into a second validation set in the second fold and is evaluated by the GCN));
evaluating the GCN using the second validation set … (Kunal Page 5, Left column, Paragraph 1, Lines 16-24 teaches using a five-fold cross validation for the GCN (i.e., the data is partitioned into a second validation set in the second fold and is evaluated by the GCN).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Ma, Gebregiorgis, Guo Deo, and Taherkhani with the above teaching of Kunal because doing so would lead to an expected improvement in the ability to reduce the sensitivity to data partitioning (Kunal, Page 5, Left column, Paragraph 1, Lines 23-24).
Claims 10,15-16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Butler et al. US 2009/0210830 A1 (hereinafter Butler).
Regarding claim 10:
Ma teaches: A system for fault criticality assessment comprising: a storage device (Ma [0147]); and
a graph convolutional network (GCN) module comprising one or more processors configured to execute instructions stored in the storage device to implement a k-tier GCN having at least two tiers comprising a first tier and a second tier arranged in sequence, the execution of the instructions of the GCN module being configured to: (Ma [0050] teaches applying a graph convolutional network (GCN) module and [0096] teaches a processor being implemented. Further, Ma [0092] teaches a multi-stage graph convolutional network (i.e., a k-tier graph convolutional network) comprising first stage and a second stage arranged in sequence).
generate a graph from a netlist of a target hardware architecture having an applied domain-specific use-case, wherein a logic gate is represented in the graph as a node and a signal path between two logic gates is represented in the graph as an edge; and (Ma [0050] teaches the GCN designed to work directly on graphs and leverage their structural information. Further, claim 1 and [0052] teaches forming/generating a graph representation from a netlist for the circuit, where “each logic block is represented as a node and the edges of the graph represent signal paths between logic blocks” and [0028] teaches the generated graph “for a circuit that can then be applied to manufacture the circuit with improved testability”, thus having an applied domain-specific use case within the domain of Electronic Design Automation (see [0003][0097][0149])).
evaluate functional criticality of unlabeled nodes of the graph for the applied domain-specific use-case using the first tier of the k-tier GCN, wherein the first tier of the k-tier GCN classifies unlabeled nodes of the graph for the applied domain-specific use-case as critical or benign based on functional failure for the applied domain-specific use-case, and (Ma [0052] Lines 18-21 teach using the trained GCN to make DTN/non-DTN label predictions for an input netlist, which implies that the input netlist-graph nodes are unlabeled and teaches using a trained GCN to make predictions about whether nodes in the input netlist are difficult to test nodes (i.e., critical) or not (i.e., benign). Further, Ma [0092] teaches evaluating the functionality criticality of the nodes using the multi-stage graph convolutional network (i.e., a k-tier graph convolutional network) where at each stage (i.e., first tier of the k-tier GCN) the multi-stage graph convolutional classifies nodes as positive (i.e., critical) or negative (i.e., benign) such that negative classified nodes are filtered out with high confidence and positive classified nodes are retained).
re-evaluate nodes classified as benign by the first tier of the k-tier GCN using the second tier of the k-tier GCN to identity test escapes comprising nodes that are critical for the applied domain-specific use case but misclassified as benign by the first tier, ( Ma [0092] teaches using a multi-stage graph convolutional network (i.e., a k-tier graph convolutional network where k ≥ 2) to filter out some of the negative classified nodes and address the undesirable performance effects associated with data imbalance to reduce bias toward the majority class, thereby imposing a larger penalty for misclassifying positive nodes (i.e., a second model is trained to identify and reduce test escapes that were classified by a first trained model). To be specific, Ma [0092] teaches one graph convolutional network (i.e., first tier of the k-tier GCN) is trained to filtering out some of the negative classified nodes (i.e., nodes classified as benign ) with high confidence. The filtered set (i.e., nodes classified as benign ) is passed to the next stage (i.e., second tier of the k-tier GCN). That is, positive nodes and negative nodes (i.e., begin nodes) that were not classified with high confidence by the first stage (i.e., first tier of the k-tier GCN) will be used for re-evaluation by the second stage (i.e., second tier of the k-tier GCN). Thus, in the second stage the graph convolutional neural network ( i.e., second tier of the k-tier GCN) will be re-evaluating all remaining nodes from the first stage (i.e., first tier of the k-tier GCN) except the high confidence nodes. Further, Ma [0052] teaches making predictions about whether nodes in an input netlist (i.e., the graph generated from a corresponding netlist having an applied domain-specific use-case [0028]) are difficult to test nodes or not and assigning a label of DTN (i.e., critical nodes) or non-DTN (i.e., benign nodes) to each node).
Ma does not specifically teaches ...the test escapes corresponding to coverage gaps that would otherwise undermine fault coverage in downstream hardware testing of the target hardware architecture.
Nonetheless, Butler teaches the following:
...the test escapes corresponding to coverage gaps that would otherwise undermine fault coverage in downstream hardware testing of the target hardware architecture ( Butler [0016] teaches test escape correspond to fault coverage gaps that undermine the fault coverage in hardware testing of the target integrated circuit (i.e., the target hardware architecture)).
Butler is also in the same field of endeavor as Ma (machine learning). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the functionality of test escape correspond to fault coverage gaps that undermine the fault coverage in hardware testing of the target integrated circuit, as being disclosed and taught by Butler, in the system taught by Ma to yield the predictable results of “ to improve the accuracy of test escape” (Butler [0016]).
Regarding claim 15:
Ma teaches A method for fault criticality assessment, comprising: generating a graph from a netlist of a target hardware architecture having an applied domain-specific use-case, wherein a logic gate is represented in the graph as a node and a signal path between two logic gates is represented in the graph as an edge; and (Ma [0050] teaches the GCN designed to work directly on graphs and leverage their structural information. Further, claim 1 and [0052] teaches forming/generating a graph representation from a netlist for the circuit, where “each logic block is represented as a node and the edges of the graph represent signal paths between logic blocks” and [0028] teaches the generated graph “for a circuit that can then be applied to manufacture the circuit with improved testability”, thus having an applied domain-specific use case within the domain of Electronic Design Automation(see [0003][0097][0149])).
evaluating functional criticality of unlabeled nodes of the graph for the applied domain-specific use-case using a first tier of, a k-tier graph convolutional network (GCN) having at least two tiers comprising the first tier and a second tier arranged in sequence wherein a first tier of the k-tier GCN classifies unlabeled nodes of the graph for the applied domain- specific use-case as critical or benign based on functional failure for the applied domain- specific use-case and (Ma [0052] Lines 18-21 teach using the trained GCN to make DTN/non-DTN label predictions for an input netlist, which implies that the input netlist-graph nodes are unlabeled and teaches using a trained GCN to make predictions about whether nodes in the input netlist are difficult to test nodes (i.e., critical) or not (i.e., benign). Further, [0092] teaches evaluating the functionality criticality of the nodes using the multi-stage graph convolutional network (i.e., a k-tier graph convolutional network) where at each stage (i.e., first tier of the k-tier GCN) the multi-stage graph convolutional classifies nodes as positive (i.e., critical) or negative (i.e., benign) such that negative classified nodes are filtered out with high confidence and positive classified nodes are retained).
re-evaluate nodes classified as benign by the first tier of the k-tier GCN using the second tier of the k-tier GCN to identity test escapes comprising nodes that are critical for the applied domain-specific use case but misclassified as benign by the first tier, (Ma [0092] teaches using a multi-stage graph convolutional network (i.e., a k-tier graph convolutional network where k ≥ 2) to filter out some of the negative classified nodes and address the undesirable performance effects associated with data imbalance to reduce bias toward the majority class, thereby imposing a larger penalty for misclassifying positive nodes (i.e., a second model is trained to identify and reduce test escapes that were classified by a first trained model). To be specific, Ma [0092] teaches one graph convolutional network (i.e., first tier of the k-tier GCN) is trained to filtering out some of the negative classified nodes (i.e., nodes classified as benign ) with high confidence. The filtered set (i.e., nodes classified as benign ) is passed to the next stage (i.e., second tier of the k-tier GCN). That is, positive nodes and negative nodes (i.e., begin nodes) that were not classified with high confidence by the first stage (i.e., first tier of the k-tier GCN) will be used for re-evaluation by the second stage (i.e., second tier of the k-tier GCN). Thus, in the second stage the graph convolutional neural network ( i.e., second tier of the k-tier GCN) will be re-evaluating all remaining nodes from the first stage (i.e., first tier of the k-tier GCN) except the high confidence nodes. Further, Ma [0052] teaches making predictions about whether nodes in an input netlist (i.e., the graph generated from a corresponding netlist having an applied domain-specific use-case [0028]) are difficult to test nodes or not and assigning a label of DTN (i.e., critical nodes) or non-DTN (i.e., benign nodes) to each node).
Ma does not specifically teaches ...the test escapes corresponding to coverage gaps that would otherwise undermine fault coverage in downstream hardware testing of the target hardware architecture.
Nonetheless, Butler teaches the following:
...the test escapes corresponding to coverage gaps that would otherwise undermine fault coverage in downstream hardware testing of the target hardware architecture ( Butler [0016] teaches test escape correspond to fault coverage gaps that undermine the fault coverage in hardware testing of the target integrated circuit (i.e., the target hardware architecture)).
Regarding claim 16:
Ma and Butler teach The method of claim 15. Ma specifically teaches further comprising extracting dataflow features and functional features from the netlist and providing the dataflow features and functional features as inputs to the k-tier GCN (Ma [0055-0056] teach that the node embeddings extracted from a netlist-derived graph preserve the relevant properties of the node (i.e., functional features), which includes connectivity (i.e., dataflow features. Further, Ma [0055-0056] teaches inputting the node embeddings (i.e., embeddings extracted from a netlist-derived graph that preserve the relevant properties of the node (i.e., functional features), which includes connectivity (i.e., dataflow features)) as features to a GCN model for training and that the model is trained based on the set of training data).
Regarding claim 18:
Ma and Butler teach The method of claim 16. Ma specifically teaches wherein the netlist-graph used for providing the dataflow features and functional features is the same graph as the graph generated from the netlist of the target hardware architecture having the applied domain-specific use-case (Ma [0069-0070] teaches that the training data nodes (i.e., the nodes of the netlist-graph) may be split into different batches for validation and training. This implies that the validation batch of netlist-graph nodes (i.e., the graph being evaluated by the GCN) are from a same graph as the netlist-graph nodes used for training (i.e., the graph being used to train the GCN)).
Regarding claim 19:
Ma and Butler teach The method of claim 15. Ma specifically teaches wherein the k-tier GCN is trained using a netlist-graph generated from a different netlist than the netlist-graph generated from the netlist and used for evaluating the functional criticality of nodes ( Ma [0052] teaches that after training/validation, the graph convolutional network may make predictions about whether nodes in an input netlist are DTN or non-DTN (i.e., an input netlist that is different from the already converted acyclic netlist-graph used for training/validation)).
Claim 12-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ma, Butler in further view of Gebregiorgis, in further view of Guo.
Regarding claim 12:
Ma and Butler teaches The method of claim 10. Ma specifically teaches a training module configured to ([0148]):
generate a netlist-graph, wherein a logic gate is represented in the netlist-graph as a node and a signal path between two logic gates is represented in the netlist-graph as an edge (Ma [0003] Lines 35-38 and [0052]);
select nodes for a first set of nodes from the netlist-graph,
perform a functional simulation of each node of the first set of nodes to determine functional criticality in that node,
label the first set of nodes of the netlist-graph based on the functional simulation, each node of the first set of nodes being labeled with a label indicating the functional criticality for that node is benign or critical; and (Ma [0052] teaches that graph nodes may be assigned a label indicating that the node is “hard” to test (i.e., a label indicating whether the functional criticality for that node is benign or critical) for training purposes based on a simulation (i.e., a functional simulation)).
train a k-tier GCN, including the trained first GCN and the trained second GCN, where k >2, the k-tier GCN learning from the labels of the first set of nodes to predict labels of unlabeled nodes of the netlist-graph (Ma [0052] teaches using the labeled nodes of the netlist graph to train a graph convolutional network to make predictions about whether unlabeled netlist graph nodes are difficult to test or not (i.e., to identify criticality of nodes); [0090] and [0092] teach that a multi-stage graph convolutional network (i.e., a k-tier graph convolutional network where k ≥ 2) may be trained and utilized).
Ma and Butler does not teaches ...the first set of nodes having a fewer number of nodes than that of the netlist-graph; perform a functional fault simulation of … nodes to determine functional criticality of stuck-at faults in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality; label the first set of nodes… based on the functional fault simulation;
However, Gebregiorgis analogues in the art teaches:
…the first set of nodes having a fewer number of nodes than that of the netlist-graph; (Fig. 2(a) teach selecting a submodule having a fewer number of nodes of a DUT Gate-level netlist graph for which fault injection simulation is to be performed).
performing a functional fault simulation of …nodes to determine functional criticality in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality; (Gebregiorgis Fig. 3 and pg. 6, left column, para. 2-3, teaches fault injection based functional test methodology of neuromorphic circuits. Para. 2 specifically teaches detect and classify “important faults” in a neuromorphic circuit (NC) by utilizing “real input image dataset” in order to reduce the “search space for test patterns able to detect the important faults and hence, reduces the associated test cost”, and para. 2 teaches the overall flow of the functional testing methodology).
Gebregiorgis is also in the same field of endeavor as Ma and Butler (machine learning). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the functionality of testing important and non-important faults that reduce resource consumption as being disclosed and taught by Gebregiorgis, in the system taught by Ma and Butler to yield the predictable results of reducing “the testable faults by more than 2X on average, while maintaining high fault coverage” (see Gebregiorgis pg. 2, left colm., para. 2).
Gebregiorgis does not teach or suggest perform a functional fault simulation of … nodes to determine functional criticality of stuck-at faults in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality; and label the first set of nodes …based on the functional fault simulation…
Nevertheless, Guo teaches the following:
perform a functional fault simulation of … nodes to determine functional criticality of stuck-at faults in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality; ( Guo [0023] Lines 1-23 and [0026] teach using a cell aware fault model to simulate a defect and predict how malfunctioning transistors (i.e., nodes) could impact the functionality of the overall cell design (i.e., performing a functional fault simulation) and to pinpoint a candidate defect as a particular transistor or a particular region (i.e., to determine functionally critical nodes that lead to a loss of functionality of the target hardware architecture); [0024] teaches the use of stuck-at fault models);
label the first set of nodes …based on the functional fault simulation… (Guo [0023] and [0026] teach pinpointing (i.e., labeling) a candidate defect as a particular transistor (i.e., node) or a particular region within a cell design (i.e., a set of nodes) based on the fault model’s simulation).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Ma, Butler and Gebregiorgis with the above teaching of Guo because doing so would lead to an expected reduction in the amount of processing resources and time required to perform defect/fault analysis (Guo, [0023]).
Regarding claim 13:
Ma, Butler, Gebregiorgis and Guo teach The method of claim 12. Ma specifically teaches wherein the netlist-graph is a same graph as the graph generated from the netlist of the target hardware architecture having the applied domain-specific use-case (Ma [0069-0070] teaches that the training data nodes (i.e., the nodes of the netlist-graph) may be split into different batches for validation and training. This implies that the validation batch of netlist-graph nodes (i.e., the graph being evaluated by the GCN) are from a same graph as the netlist-graph nodes used for training (i.e., the graph being used to train the GCN)).
Regarding claim 14:
Ma, Butler, Gebregiorgis and Guo teach The method of claim 12. Ma specifically teaches wherein the netlist-graph is generated from a different netlist than that of the graph ( Ma [0052] teaches that after training/validation, the graph convolutional network may make predictions about whether nodes in an input netlist are DTN or non-DTN (i.e., an input netlist that is different from the already converted acyclic netlist-graph used for training/validation)).
Regarding claim 17:
Ma and Butler teaches The method of claim 15. Ma specifically teaches further comprising: selecting nodes for a first set of nodes from the netlist-graph
performing a functional simulation of each node of the first set of nodes to determine functional criticality of in that node,
labeling the first set of nodes based on the functional simulation; and (Ma [0052] teaches that graph nodes may be assigned a label indicating that the node is “hard” to test (i.e., a label indicating the functional criticality for that node is benign or critical) for training purposes based on a simulation (i.e., a functional simulation)).
training the k-tier GCN using the labeled first set of nodes to predict labels for unlabeled nodes of the netlist-graph,
Ma and Butler does not specifically teach …the first set of nodes having a fewer number of nodes than that of the netlist-graph; performing a functional fault simulation of … nodes to determine functional criticality of stuck-at faults in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality; labeling the first set of nodes of the netlist-graph based on the functional fault simulation; and reducing computational simulation requirements by eliminating full fault simulation of all potential faults.
Nevertheless, Gebregiorgis analogues in the art teaches:
…the first set of nodes having a fewer number of nodes than that of the netlist-graph (Gebregiorgis Fig. 2(a) teach selecting a submodule having a fewer number of nodes of a DUT Gate-level netlist graph for which fault injection simulation is to be performed).
performing a functional fault simulation of …nodes to determine functional criticality in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality; (Gebregiorgis Fig. 3 and pg. 6, left column, para. 2-3, teaches fault injection based functional test methodology of neuromorphic circuits. Para. 2 specifically teaches detect and classify “important faults” in a neuromorphic circuit (NC) by utilizing “real input image dataset” in order to reduce the “search space for test patterns able to detect the important faults and hence, reduces the associated test cost”, and para. 2 teaches the overall flow of the functional testing methodology.
training the [neural network] to predict labels for unlabeled nodes of the netlist-graph, thereby reducing computational simulation requirements by eliminating full fault simulation of all potential faults (Gebregiorgis Fig. 3 and pg. 6, left column, para. 2-3, teaches fault injection based functional test methodology of neuromorphic circuits where a neural network is trained to predict labels such as “important fault” and “non-important fault” for the node/neuron injected with a fault. Further, para. 2 specifically teaches detect and classify “important faults” in a neuromorphic circuit (NC) by utilizing “real input image dataset” in order to reduce the “search space for test patterns able to detect the important faults and hence, reduces the associated test cost” and Gebregiorgis emphasizes how the proposed test methodologies presented allows to “significantly reduce the number of faults to be tested, and test time accordingly, without sacrificing the output accuracy or fault coverage” (see Gebregiorgis Abstract, line 11-14).
Gebregiorgis is also in the same field of endeavor as Ma and Butler (machine learning). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the functionality of testing important and non-important faults that reduce resource consumption as being disclosed and taught by Gebregiorgis, in the system taught by Ma and Butler to yield the predictable results of reducing “the testable faults by more than 2X on average, while maintaining high fault coverage” (see Gebregiorgis pg. 2, left colm., para. 2).
Gebregiorgis does not explicitly teach performing a functional fault simulation of …nodes to determine functional criticality of stuck-at faults in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality; and labeling the first set of nodes based on the functional fault simulation; and
However, in the analogous art, Guo teaches:
performing a functional fault simulation of …nodes to determine functional criticality of stuck-at faults in that node, wherein a fault is considered functionally critical if the fault leads to a functional failure of the target hardware architecture corresponding to degradation of circuit performance or loss of functionality; (Guo teaches [0023] Lines 1-23 and [0026] using a cell aware fault model to simulate a defect and predict how malfunctioning transistors (i.e., nodes) could impact the functionality of the overall cell design (i.e., performing a functional fault simulation) and to pinpoint a candidate defect as a particular transistor or a particular region (i.e., to determine functionally critical nodes that lead to a loss of functionality of the target hardware architecture); [0024] teaches the use of stuck-at fault models).
labeling the first set of nodes based on the functional fault simulation; and (Guo [0023] and [0026] teach pinpointing (i.e., labeling) a candidate defect as a particular transistor (i.e., node) or a particular region within a cell design (i.e., a set of nodes) based on the fault model’s simulation).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Ma, Butler and Gebregiorgis with the above teaching of Guo because doing so would lead to an expected reduction in the amount of processing resources and time required to perform defect/fault analysis (Guo, [0023]).
Allowable Subject Matter
Claim 6 has been searched, but no prior art has been uncovered which anticipates nor renders the claim obvious. Claim 6, would be allowable if rewritten to include all the limitation of the base claim and any intervening claims.
Claims 11 and 20 have been searched, but no prior art has been uncovered which anticipates nor renders the claim obvious. Claims 11 and 20, would be allowable if rewritten to overcome the rejections under 35 USC § 101 and to include all the limitation of the base claim and any intervening claims.
Conclusion
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/G.G.F./Examiner, Art Unit 2127
/TEWODROS E MENGISTU/Primary Examiner, Art Unit 2127
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