DETAILED ACTION
1. This action is in response to the amendment filed on 2/9/26.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1, 7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwata et al. (US 20170351285).
Regarding claim 1: Iwata et al. disclose a voltage regulator circuit (i.e. figure 2) comprising:
a first transistor (i.e. 20) having first and second current terminals and a first control terminal (i.e. gate of 20), wherein the first current terminal (i.e. top terminal of 20) is connected to a voltage input terminal (i.e. at Vin), and the second current terminal (i.e. bottom terminal of 20) is coupled (i.e. electrically coupled) to a ground terminal (i.e. ground);
a second transistor (i.e. 10) having third and fourth current terminals and a second control terminal (i.e. gate of 10), wherein the third current terminal (i.e. top terminal of 10) is connected to the first current terminal (i.e. top terminal of 20), and the fourth current terminal (i.e. bottom terminal of 10) is coupled (i.e. electrically coupled) to a regulator output terminal (i.e. terminal of Vout);
a diode (i.e. ZD2) coupled between the first control terminal (i.e. gate of 20) and the ground terminal (i.e. ground);
a comparison circuit (i.e. circuit includes P1, DS1, ZD1) having a comparison input, a first comparison output (i.e. output at V1 of circuit includes P1, DS1, ZD1), and a second comparison output (i.e. output from P1), wherein the comparison input (i.e. input for Vin) is coupled (i.e. electrically coupled) to the voltage input terminal (i.e. at Vin), and the comparison output (i.e. output at V1 of circuit includes P1, DS1, ZD1) is coupled to the second control terminal (i.e. ¶ 50), the comparison circuit (i.e. circuit includes P1, DS1, ZD1) configurable to enable or disable (i.e. by turn on/off of transistor N1) a first charge path (i.e. first charge path through P3) between the voltage input terminal (i.e. at Vin) and the second control terminal (i.e. gate of 10) via the first comparison output (i.e. output at V1 of circuit includes P1, DS1, ZD1) responsive to a state (i.e. function state of comparison circuit P1, DS1, ZD1) of the comparison input (i.e. ¶ 49-52 and 62); and
a pullup circuit (i.e. P3, P4) having first and second pullup inputs (i.e. inputs of P3, P4) and a pullup output (i.e. output to G1), wherein the first pullup input is coupled (i.e. electrically coupled) to the voltage input terminal (i.e. at Vin), the second pullup input is coupled (i.e. electrically coupled) to the second comparison output (i.e. output from P1), and the pullup output (i.e. output to G1) is coupled (i.e. electrically coupled) to the first comparison output (i.e. output at V1 of circuit includes P1, DS1, ZD1) and the second control terminal (i.e. gate of 10), the pullup circuit (i.e. P3, P4) configurable to enable or disable (i.e. by turn on/off of transistor N1 to allow the current Ith flowing through P3) a second charge path (i.e. second charge path through transistor P4 by the configuration of the transistor P4 having its gate connected to the gate G1 of transistor 10) between the voltage input terminal (i.e. at Vin) and the second control terminal (i.e. gate of 10) via the pullup output (i.e. output to G1) responsive to a state of the second pullup input (i.e. inputs of P3, P4), the first charge path (i.e. first charge path through P3) being separate from the second charge path (i.e. ¶ 48, 55, 59-60).
Regarding claim 7: (i.e. figure 2) the diode element is a zener diode (i.e. ZD2).
Regarding claim 9: Iwata et al. disclose (i.e. figure 2) an integrated circuit comprising:
a first transistor (i.e. 20) having first and second current terminals and a first control terminal (i.e. gate of 20), wherein the first current terminal (i.e. top terminal of 20) is connected to a voltage input terminal (i.e. at Vin), and the second current terminal (i.e. bottom terminal of 20) is coupled to a ground terminal (i.e. ground);
a second transistor (i.e. 10) having third and fourth current terminals and a second control terminal (i.e. gate of 10), wherein the third current terminal (i.e. top terminal of 10) is connected to the first current terminal (i.e. top terminal of 20), and the fourth current terminal (i.e. bottom terminal of 10) is coupled (i.e. electrically coupled) to a pre-regulated output terminal (i.e. terminal of Vout);
a diode (i.e. ZD1) coupled between the first control terminal (i.e. gate of 20) and the ground terminal (i.e. ground);
a comparison circuit (i.e. circuit includes P1, DS1, ZD1) having a first comparison input, and a comparison output, wherein the comparison input (i.e. input for Vin) is coupled (i.e. electrically coupled) to the voltage input terminal (i.e. at Vin), and the first comparison output (i.e. output at V1 of circuit includes P1, DS1, ZD1) is coupled (i.e. electrically coupled) to the second control terminal (i.e. gate of 10), the comparison circuit (i.e. circuit includes P1, DS1, ZD1) configurable to enable or disable (i.e. by turn on/off of transistor N1) a first charge path (i.e. first charge path through P3) between the voltage input terminal (i.e. at Vin) and the second control terminal (i.e. gate of 10) via the first comparison output (i.e. output at V1 of circuit includes P1, DS1, ZD1) responsive to a state (i.e. function state of comparison circuit P1, DS1, ZD1) of the comparison input (i.e. ¶ 49-52 and 62);
a low dropout regulator circuit (i.e. 1) having an LDO input (i.e. input of 1) coupled to the pre-regulated output terminal (i.e. terminal of Vout), and having an LDO output (i.e. output of 1).
a pullup circuit (i.e. P3, P4) having a first input (i.e. inputs of P3) coupled (i.e. electrically coupled) to the second comparison output (i.e. output from P1) of the comparison circuit (i.e. circuit includes P1, DS1, ZD1), a second input coupled to the voltage input terminal (i.e. input of P4), and an output (i.e. output of P3 or P4) coupled the second control terminal (i.e. gate of 10), the pullup circuit (i.e. P3, P4) configurable to enable or disable (i.e. by turn on/off of transistor N1 to allow the current Ith flowing through P3) a second charge path (i.e. second charge path through transistor P4 by the configuration of the transistor P4 having its gate connected to the gate G1 of transistor 10) between the voltage input terminal (i.e. at Vin) and the second control terminal (i.e. gate of 10) via the pullup output (i.e. output to G1) responsive to a state of the second pullup input (i.e. inputs of P3, P4), the first charge path (i.e. first charge path through P3) being separate from the second charge path (i.e. ¶ 48, 55, 59-60).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Iwata et al. (US 20170351285) in view of Wachter et al. (US 5744878).
Regarding claim 3: Iwata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a current source and a capacitor coupled in series between the voltage input terminal and the ground terminal, wherein a terminal connecting the current source to the capacitor is coupled to the diode and the first control terminal.
Wachter et al. disclose circuit comprising (i.e. figure 1) a current source (i.e. I1) and a capacitor (i.e. Ch) coupled (i.e. electrically coupled) in series between the voltage input terminal (i.e. Udd) and the ground terminal (i.e. ground), wherein a terminal (i.e. terminal of I1) connecting the current source (i.e. I1) to the capacitor is coupled (i.e. electrically coupled) to the diode (i.e. D1 or D2) and the first control terminal (i.e. control terminal of M1).
Therefore, it would have been obvious to one with ordinary skill in the art at the time the invention was made to modify the circuit of Iwata et al.’s invention with the circuit as disclose by Wachter et al. to attain a higher switching speed, a third switching device is used to impose the supply voltage on the second terminal of the bootstrap capacitor.
7. Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Iwata et al. (US 20170351285) in view of Patterson et al. (US 5218235).
Regarding claim 4: Iwata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a capacitor coupled between the regulator output terminal and the ground terminal.
Patterson et al. disclose a power circuit comprising a capacitor (i.e. 120) coupled between the regulator output terminal (i.e. 118) and the ground terminal (i.e. Vss).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Iwata et al.’s invention with circuit as disclose by Patterson et al. to provide an efficient power stealing circuit for generating a supply voltage.
Regarding claim 5: Iwata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose in which the first transistor is an N-type field effect transistor (FET).
Patterson et al. disclose a power circuit comprising (i.e. figure 8) in which the first transistor (i.e. 260) is an N-type field effect transistor (FET).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Iwata et al.’s invention with circuit as disclose by Patterson et al. to provide an efficient power stealing circuit for generating a supply voltage.
Regarding claim 6: Iwata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose in which the second is a P-type FET
Patterson et al. disclose a power circuit comprising in which the second transistor (i.e. 236) is a P-type FET
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Iwata et al.’s invention with circuit as disclose by Patterson et al. to provide an efficient power stealing circuit for generating a supply voltage.
8. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Iwata et al. (US 20170351285).
Regarding claim 8: Iwata et al. discloses the claimed invention except for the diode includes stacked diode-connected N-type FETs. It would have been an obvious matter of design choice to modified Iwata et al.’s invention with the diode includes stacked diode-connected N-type FETs to improve the circuit efficiency, since applicant has not disclosed that the diode element includes stacked diode-connected N-type field effect transistors solve any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the diode as disclosed by Patterson et al.
9. Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Iwata et al. (US 20170351285) in view of Wang et al. (US 10146240).
Regarding claim 10: Iwata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a data core and analog circuit blocks.
Wang et al. disclose a power supply (i.e. figures 1, 11 and 14) comprising a data core (i.e. 158) and analog circuit blocks (i.e. figure 1: load circuit 111).
Therefore, it would have been obvious to one with ordinary skill in the art at the time the invention was made to modify the circuit of Iwata et al.’s invention with power supply as disclose by Wang et al. to have the pre-regulator circuit is coupled to provide a dynamic supply voltage to the current buffer. The dynamic supply voltage depends at least in part on a fixed supply voltage provided thereto, as well as the output voltage provided by the LDO voltage regulator.
Regarding claim 11: Iwata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the data core and the analog circuit blocks include a carbon monoxide detection circuit, a photo-detection circuit, and an ion detection circuit.
Gonzales et al. discloses a power management unit a detection circuit comprising the data core and the analog circuit blocks include a carbon monoxide detection circuit, a photo-detection circuit, and an ion detection circuit (i.e. ¶ 160, 162, 180).
Therefore, it would have been obvious to one with ordinary skill in the art at the time the invention was made to modify the circuit of Iwata et al.’s invention with the unit as disclose by Gonzales et al., because there is a need for a system is provided for designing improved intelligent.
10. Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Iwata et al. (US 20170351285) in view of Applicant admitted prior art (hereafter AAPA).
Regarding claim 12: Iwata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the voltage input terminal is coupled to an output of an AC/DC converter.
AAPA discloses a power supply (i.e. figure 9A) comprising the voltage input terminal is coupled to an output of an AC/DC converter (i.e. 904).
Therefore, it would have been obvious to one with ordinary skill in the art at the time the invention was made to modify the circuit of Iwata et al.’s invention with the power supply as disclose by AAPA, because the power supply provides an alternative supply voltage.
Regarding claim 13: Iwata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the integrated circuit is a smoke detector integrated circuit.
AAPA discloses a power supply (i.e. figure 9A) comprising the integrated circuit is a smoke detector integrated circuit (i.e. 912).
Therefore, it would have been obvious to one with ordinary skill in the art at the time the invention was made to modify the circuit of Iwata et al.’s invention with the power supply as disclose by AAPA, because the power supply provides an alternative supply voltage.
Response to Arguments
11. Applicant's arguments filed 9/5/15 have been fully considered but they are not persuasive.
Applicant argues that “Iwata fails to disclose at least these claim elements. As best understood by Applicant, in FIG. 2 of Iwata, P1, DS1, and ZD1 (the alleged comparison circuit) pulls up the gate of transistor 10 (the alleged second control terminal) via P3 (the alleged pullup circuit). P1, DSI, and ZD1 does not provide a charge path to the gate of transistor 10 separate from the charge path provided by P3. In contrast, claim 1 recites that the comparison circuit and the pullup circuit provide separate charge paths to the second control terminal.”
The Examiner disagrees, because Iwata disclose (i.e. equivalents show in parentheses)
the comparison circuit (i.e. circuit includes P1, DS1, ZD1) configurable to enable or disable (i.e. by turn on/off of transistor N1) a first charge path (i.e. first charge path through P3) between the voltage input terminal (i.e. at Vin) and the second control terminal (i.e. gate of 10) via the first comparison output (i.e. output at V1 of circuit includes P1, DS1, ZD1) responsive to a state (i.e. function state of comparison circuit P1, DS1, ZD1) of the comparison input (i.e. ¶ 49-52 and 62)…
the pullup circuit (i.e. P3, P4) configurable to enable or disable (i.e. by turn on/off of transistor N1 to allow the current Ith flowing through P3) a second charge path (i.e. second charge path through transistor P4 by the configuration of the transistor P4 having its gate connected to the gate G1 of transistor 10) between the voltage input terminal (i.e. at Vin) and the second control terminal (i.e. gate of 10) via the pullup output (i.e. output to G1) responsive to a state of the second pullup input (i.e. inputs of P3, P4), the first charge path (i.e. first charge path through P3) being separate from the second charge path (i.e. ¶ 48, 55, 59-60).
Conclusion
12. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nguyen Tran/Primary Examiner, Art Unit 2838
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