Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 3, 2025 has been entered.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 7-12, and 15-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea with significantly more.
Regarding Claim 1,
Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 1 is directed to a method for compressing a deep neural network (DNN), which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“(a) performing an intra-convolution kernel pruning of the DNN model wherein a fixed number of weights are pruned in each convolution kernel of the DNN model to generate sparse convolution patterns”
“(b) performing inter-convolution kernel pruning of the DNN model to generate connectivity sparsity, wherein inter-convolution kernel pruning comprises removing at least one kernel corresponding to an input channel and an output channel to cut connections between the input channel and the output channel of the DNN model”
“performing filter kernel reordering to organize filters together according to their similarity such that kernels that are identical in a filter are ordered together thereby improving intra-thread parallelization thereby improving inter-thread parallelization, wherein the similarity between filters is based on the number of non-empty kernels in each filter and the number of kernels at identical positions with identical pattern identifiers”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)).
The limitations:
“(c) training the DNN model compressed in steps (a) and (b)”
“(d) applying a compiler-assisted DNN acceleration framework to the DNN model trained in (c) to generate code to be executed on the mobile device, wherein step (d) comprises removing memory-level input load redundancy corresponding to the DNN model trained in (c)”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f).
The limitations:
“storing, in a memory, weights of the DNN model in a compact format that supports branch-less DNN execution”
As drafted, are additional elements that amount to no more than insignificant extra-solution activity. See MPEP 2106.05(g).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” and “insignificant extra-solution activity”. Furthermore, the “storing” limitation recites the well-understood, routine, and conventional activity of storing and retrieving information in memory. MPEP 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Mere instructions to apply an exception and insignificant extra-solution activity cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 2,
Claim 2 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 2 is directed to a method for compressing a deep neural network (DNN), which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein step (d) includes converting the DNN model trained in (c) into one or more computational graphs”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)).
The limitations:
“performing one or more compiler optimizations based on the sparse convolution patterns for compressed DNN execution”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception. Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 3,
Claim 3 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 3 is directed to a method for compressing a deep neural network (DNN), which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 2.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)).
The limitations:
“wherein the one or more compiler optimizations are applicable to a CPU or a GPU of the mobile device”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception”. Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 4,
Claim 4 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 4 is directed to a method for compressing a deep neural network (DNN), which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the one or more compiler optimizations includes performing a fine-grained Layerwise Representation (LR) to capture the sparse convolution patterns and the connectivity sparsity from (a) and (b)”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: See corresponding analysis of claim 2.
Step 2B Analysis: See corresponding analysis of claim 2.
Regarding Claim 7,
Claim 7 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 7 is directed to a method for compressing a deep neural network (DNN), which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 2.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)).
The limitations:
“wherein the one or more compiler optimizations includes performing load redundancy elimination in the DNN model.”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception”. Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 8,
Claim 8 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 8 is directed to a method for compressing a deep neural network (DNN), which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the one or more compiler optimizations includes automatically tuning configuration parameters”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: See corresponding analysis of claim 2.
Step 2B Analysis: See corresponding analysis of claim 2.
Regarding Claim 9,
Claim 9 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 9 is directed to a computer system for compressing a deep neural network (DNN), which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“(a) perform an intra-convolution kernel pruning of the DNN model wherein a fixed number of weights are pruned in each convolution kernel of the DNN model to generate sparse convolution patterns”
“(b) perform inter-convolution kernel pruning of the DNN model to generate connectivity sparsity, wherein inter-convolution kernel pruning comprises removing at least one kernel corresponding to an input channel and an output channel to cut connections between the input and the output channel of the DNN model”
“performing filter kernel reordering to organize filters together according to their similarity such that kernels that are identical in a filter are ordered together thereby improving intra-thread parallelization thereby improving inter-thread parallelization, wherein the similarity between filters is based on the number of non-empty kernels in each filter and the number of kernels at identical positions with identical pattern identifiers”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)).
The limitations:
“A computer system, comprising: at least one processor; memory associated with the at least one processor; and a program supported in the memory for compressing a deep neural network (DNN) model by DNN weight pruning and accelerating DNN execution in a mobile device to achieve real-time inference, the program containing a plurality of instructions which, when executed by the at least one processor, cause the at least one processor to”
“train the DNN model compressed in steps (a) and (b)”
“apply a compiler-assisted DNN acceleration framework to the DNN model trained in (c) to generate code to be executed on the mobile device, wherein step (d) comprises removing memory-level input load redundancy corresponding to the DNN model trained in (c)”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f).
The limitations:
“storing, in a memory, weights of the DNN model in a compact format that supports branch-less DNN execution”
As drafted, are additional elements that amount to no more than insignificant extra-solution activity. See MPEP 2106.05(g).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” and “insignificant extra-solution activity”. Furthermore, the “storing” limitation recites the well-understood, routine, and conventional activity of storing and retrieving information in memory. MPEP 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Mere instructions to apply an exception and insignificant extra-solution activity cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 10,
Claim 10 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 10 is directed to a computer system for compressing a deep neural network (DNN), which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein step (d) includes converting the DNN model trained in (c) into one or more computational graphs.”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)).
The limitation:
“performing one or more compiler optimizations based on the sparse convolution patterns for compressed DNN execution”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception”. Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 11,
Claim 11 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 11 is directed to a computer system for compressing a deep neural network (DNN), which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 10.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)).
The limitations:
“wherein the one or more compiler optimizations are applicable to a CPU or a GPU of the mobile device”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception”. Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 12,
Claim 12 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 12 is directed to a computer system for compressing a deep neural network (DNN), which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the one or more compiler optimizations includes performing a fine-grained Layerwise Representation (LR) to capture the sparse convolution patterns and the connectivity sparsity from (a) and (b)”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: See corresponding analysis of claim 10.
Step 2B Analysis: See corresponding analysis of claim 10.
Regarding Claim 15,
Claim 15 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 15 is directed to a computer system for compressing a deep neural network (DNN), which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: See corresponding analysis of claim 10.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)).
The limitations:
“wherein the one or more compiler optimizations includes performing load redundancy elimination in the DNN model.”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception”. Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 16,
Claim 16 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 16 is directed to a computer system for compressing a deep neural network (DNN), which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the one or more compiler optimizations includes automatically tuning configuration parameters”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: See corresponding analysis of claim 10.
Step 2B Analysis: See corresponding analysis of claim 10.
Regarding Claim 17,
Claim 17 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 17 is directed to a computer program product for compressing a deep neural network (DNN), which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“(a) perform an intra-convolution kernel pruning of the DNN model wherein a fixed number of weights are pruned in each convolution kernel of the DNN model to generate sparse convolution patterns”
“(b) perform inter-convolution kernel pruning of the DNN model to generate connectivity sparsity, wherein inter-convolution kernel pruning comprises removing at least one kernel corresponding to an input channel and an output channel to cut connections between the input channel and the output channel of the DNN model”
“performing filter kernel reordering to organize filters together according to their similarity such that kernels that are identical in a filter are ordered together thereby improving intra-thread parallelization thereby improving inter-thread parallelization, wherein the similarity between filters is based on the number of non-empty kernels in each filter and the number of kernels at identical positions with identical pattern identifiers”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)).
The limitations:
“A computer program product for compressing a deep neural network (DNN) model by DNN weight pruning and accelerating DNN execution in a mobile device to achieve real-time inference, said computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a computer processor, cause that computer processor to”
“train the DNN model compressed in steps (a) and (b)”
“apply a compiler-assisted DNN acceleration framework to the DNN model trained in (c) to generate code to be executed on the mobile device, wherein step (d) comprises removing memory-level input load redundancy corresponding to the DNN model trained in (c)”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f).
The limitations:
“storing, in a memory, weights of the DNN model in a compact format that supports branch-less DNN execution”
As drafted, are additional elements that amount to no more than insignificant extra-solution activity. See MPEP 2106.05(g).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” and “insignificant extra-solution activity”. Furthermore, the “storing” limitation recites the well-understood, routine, and conventional activity of storing and retrieving information in memory. MPEP 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Mere instructions to apply an exception and insignificant extra-solution activity cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 18,
Claim 18 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 18 is directed to a computer program product for compressing a deep neural network (DNN), which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein (d) includes converting the DNN model trained in (c) into one or more computational graphs”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)).
The limitations:
“and performing one or more compiler optimizations based on the sparse convolution patterns for compressed DNN execution”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f).
Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception”. Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 19,
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 19 is directed to a computer program product for compressing a deep neural network (DNN), which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the one or more compiler optimizations includes performing a fine-grained Layerwise Representation (LR) to capture the sparse convolution patterns and the connectivity sparsity from (a) and (b)”
As drafted, under their broadest reasonable interpretations, cover mental processes, i.e., concepts performed in the human mind (including an observation, evaluation, judgement, opinion). The above limitations in the context of this claim correspond to mental processes, e.g., evaluation and judgement with assistance of pen and paper.
Step 2A Prong Two Analysis: See corresponding analysis of claim 18.
Step 2B Analysis: See corresponding analysis of claim 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 7-12, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (U.S. Patent Publication No. 2019/0362235) (“Xu”) in view of Jain et al. (U.S. Patent Publication No. 2021/0158131) (“Jain”) in further view of Udupa et al. (U.S. Patent Publication No. 2021/0027151) (“Udupa”) in further view of Kopinsky (U.S. Patent Publication No. 2020/0218978) (“Kopinsky”).
Regarding claim 1, Xu teaches a computer-implemented method for compressing a deep neural network (DNN) model by DNN weight pruning and accelerating DNN execution in a mobile device to achieve real-time inference (Xu [0057] “As discussed above, an improved approach to neural network pruning can enable efficient pruning of network models to allow the model size, related computation consumption, and power consumption to drop, thereby allowing large modern networks to be adapted for and deployed onto limited-resource mobile devices, wearable devices, embedded devices, and other computing systems without significant degradation of the network accuracy.”; [0119] “FIG. 16 is a simplified block diagram 1600 illustrating an example architecture of an example implementation of a vision processing unit (VPU) configured to accelerate machine vision operations and other machine learning applications. A VPU may be implemented as a system on chip with multiple vector processor cores (e.g., 1601-1612). The VPU may be configured specifically for handling neural network inferencing workloads, capable of handling trillions of deep neural network operations per second.” Xu provides a computer-implemented method for compressing a deep neural network (DNN) model by DNN weight pruning and accelerating DNN execution in a mobile device to achieve real-time inference.), the method comprising the steps of: (a) performing an intra-convolution kernel pruning of the DNN model wherein a fixed number of weights are pruned in each convolution kernel of the DNN model to generate sparse convolution patterns (Xu [0028] “In one example implementation, a network pruner tool 205 may support and provide functionality to perform both coarse-grained neural network pruning (e.g., to prune channels, kernels, or nodes from the neural network model) (using coarse-grained pruning module 220), as well as more surgical, fine-grained neural network pruning (e.g., to prune individual weights from the model) (using fine-grained pruning module 225). In some implementations, the network pruner tool 205 can utilize both coarse-grained and fine-grained pruning to generate a sparse, pruned, or thinned version of a particular neural network.”; [0031] “In some implementations, a fine-grained pruning logic block 225 may automatically detect weights with values falling below a threshold absolute value and may prune these weights to further reduce the size and computationally complexity of the neural network” Xu provides fine-grained pruning, which prunes weights based on a threshold absolute value to generate sparse neural networks, corresponding to intra-convolutional kernel pruning of the DNN model wherein a fixed number of weights are pruned in each convolution kernel of the DNN model to generate sparse convolution patterns.); (b) performing inter-convolution kernel pruning of the DNN model to generate connectivity sparsity, wherein inter-convolution kernel pruning comprises removing at least one kernel corresponding to an input channel and an output channel to cut connections between the input channel and the output channel of the DNN model (Xu [0028] “In one example implementation, a network pruner tool 205 may support and provide functionality to perform both coarse-grained neural network pruning (e.g., to prune channels, kernels, or nodes from the neural network model) (using coarse-grained pruning module 220), as well as more surgical, fine-grained neural network pruning (e.g., to prune individual weights from the model) (using fine-grained pruning module 225). In some implementations, the network pruner tool 205 can utilize both coarse-grained and fine-grained pruning to generate a sparse, pruned, or thinned version of a particular neural network.” [0030] “In some implementations, a coarse-grained pruning logic block 220 of an example network pruner tool 205 may identify the relative importance of various channels, kernels, and/or nodes of a neural network and iteratively prune the model to first remove those portions of the neural network determined to be less important.” Xu provides coarse-grained pruning, which removes kernels/channels from a neural network, which corresponds to performing inter-convolution kernel pruning of the DNN model to generate connectivity sparsity, wherein inter-convolution kernel pruning comprises removing at least one kernel corresponding to an input channel and an output channel to cut connections between the input channel and the output channel of the DNN model, since specification paragraph [0056] defines the removal of kernels as equivalent to cutting connections between an input channel and an output channel of a DNN model.); (c) training the DNN model compressed in steps (a) and (b) (Xu [0037] “Turning to FIG. 3, a simplified block diagram is shown illustrating the example pruning, or thinning, of an example neural network model 305. The neural network model 305 (or simply “neural network”) may be originally developed and trained on a system (e.g., 105) with robust computing resources, making the size and computational complexity of the neural network of small concern when used on such systems (e.g., 105).” [0053] “In one example, fine-grained pruning may be performed in connection with the training or fine-tuning of the pruned network resulting from a preceding coarse-grained prune.” Xu provides training in connection with pruning corresponding to training the pruned model.);
Xu fails to teach and (d) applying a compiler-assisted DNN acceleration framework to the DNN model trained in (c) to generate code to be executed on the mobile device, wherein step (d) comprises: removing memory-level input load redundancy corresponding to the DNN model trained in (c) a performing filter kernel reordering to organize filters together according to their similarity such that kernels that are identical in a filter are ordered together thereby improving intra-thread parallelization thereby improving inter-thread parallelization, wherein the similarity between filters is based on the number of non-empty kernels in each filter and the number of kernels at identical positions with identical pattern identifiers, and storing, in a memory, weights of the DNN model in a compact format that supports branch-less DNN execution.
However, Jain teaches (d) applying a compiler-assisted DNN acceleration framework to the DNN model trained in (c) to generate code to be executed on the mobile device (Jain [0009] “In order for processing operations to be performed by the accelerator, neural network operators are compiled into executable code for the accelerator. Neural network operators may be referred to herein as simply “operators.” A neural network sequentially executes different operators. An operator can be, for example, convolution, where computations are performed over an input image.”; [0047] “In various examples, the host system 300 can be implemented as a server in a data center, a desktop computer, a laptop computer, a tablet computer, or a smartphone, among other examples.”; [0056] “In the example of FIG. 3, the compiler 330 includes a first stage 336 and a second stage 340, which each perform different operations to produce compiled code.”; [0080] “In some examples, the accelerator 402 can implement a neural network processing engine. In these examples, the accelerator 402, for a set of input data 450, can execute a neural network to perform a task for which the neural network was trained.” Jain provides a compiler assisted acceleration frame for a trained DNN that generates code to be executed on a mobile device.), wherein step (d) comprises: removing memory-level input load redundancy corresponding to the DNN model trained in (c) (Jain [0056] “In the example of FIG. 3, the compiler 330 includes a first stage 336 and a second stage 340, which each perform different operations to produce compiled code.”; [0060] “The second stage 340 can compile the operators partitioned to the second stage 340 by the first stage 336, and perform various operations for producing the instructions that are to be executed by the processor 303. These operations can include, for example, removing redundant dependencies, resolving or handling dependencies between nodes by inserting synchronization instructions into the code, identifying possibly optimizations in memory usage or memory bandwidth usage, and other operations.”; [0059] “The output can be represented, for example, as a data flow graph, where the nodes in the graph represent memory operations, computations, and other operations, and the edges or connections between the nodes represent dependencies between the nodes, such as data dependencies, memory dependencies, or operational dependencies, among other examples.” Jain provides removing redundant dependencies for a compiler for a trained DNN model corresponding to removing memory-level input load redundancy corresponding to the DNN model.)…
Xu and Jain are both considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically convolutional neural networks. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu with the above teachings of Jain. Doing so would allow for optimization in memory usage or memory bandwidth usage, and other operations (Jain [0060] “These operations can include, for example, removing redundant dependencies, resolving or handling dependencies between nodes by inserting synchronization instructions into the code, identifying possibly optimizations in memory usage or memory bandwidth usage, and other operations.”).
Further, Udupa teaches performing filter kernel reordering to organize filters together according to their similarity such that kernels that are identical in a filter are ordered together thereby improving intra-thread parallelization thereby improving inter-thread parallelization (Udupa [0067] “For example, the processor 301 may determine the numbers of weights of kernel 0 that are identical to the weights of the kernels 1-15. The processor 301 may thus accumulate the numbers to obtain a score of comparison for kernel 0. In an example, 3 weights in kernel 0 and kernel 1 may be identical, 5 weights in kernel 0 and kernel 2 may be identical, 4 weights in kernel 0 and kernel 15 may be identical, and so on. In such an example, the processor 301 may accumulate 3, 5, . . . , 4, and so on, and may determine the score of comparison of kernel 0, accordingly. Similarly, the processor 301 may obtain the scores of comparison for the kernels 1-15 in a like manner.”; [0094] “The processor 601 may also generate encoded S/I-IKW streams, based on the comparison of the weights of the pivot kernel, for example, kernel 0, with the weights of each of the non-pivot kernels, for example, kernels 1-15. The generation of the S/I-IKW stream may be similar to the generation of the I-IKW stream. The S/I-IKW stream may also be considered as an extension of the I-IKW stream. The number of generated S/I-IKW streams may be based on the number of non-pivot kernels, in that the S/I-IKW streams may be based on the comparison of the weights of the pivot kernel and the non-pivot kernels. If the kernels have a single channel, then the number of generated S/I-IKW streams may be equal to the number of kernels in the MAA that operate in parallel.” Udupa provides determining kernel/filter similarity and generating Similar or Identical Inter-Kernel Weight (S/I-IKW) streams therefrom ,corresponding to organizing filters together according to their similarity such that kernels that are identical in a filter are ordered together thereby improving intra-thread parallelization thereby improving inter-thread parallelization.), wherein the similarity between filters is based on the number of non-empty kernels in each filter and the number of kernels at identical positions with identical pattern identifiers (Udupa [0067] “For example, the processor 301 may determine the numbers of weights of kernel 0 that are identical to the weights of the kernels 1-15. The processor 301 may thus accumulate the numbers to obtain a score of comparison for kernel 0. In an example, 3 weights in kernel 0 and kernel 1 may be identical, 5 weights in kernel 0 and kernel 2 may be identical, 4 weights in kernel 0 and kernel 15 may be identical, and so on. In such an example, the processor 301 may accumulate 3, 5, . . . , 4, and so on, and may determine the score of comparison of kernel 0, accordingly. Similarly, the processor 301 may obtain the scores of comparison for the kernels 1-15 in a like manner.”; [0111] “The score of kernel 0 may be determined by accumulating a number of weights of kernel 0 that are identical with or similar to the weights of kernel 1, and a number of weights of kernel 0 that are identical with or similar to the weights of kernel 2. The score of kernel 1 may be determined by accumulating the number of weights of kernel 1 that are identical with or similar to the weights of kernel 0 and a number of weights of kernel 1 that are identical with or similar to the weights of kernel 2.” Udupa provides kernel/filter similarity based on non-empty kernels/filters 1-15, corresponding to the similarity between filters is based on the number of non-empty kernels in each filter and the number of kernels at identical positions with identical pattern identifiers.).
Xu, Jain and Udupa are all considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically convolutional neural networks. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu in view of Jain with the above teachings of Udupa. Doing so would optimize convolution operations by reducing the total number of multiplication operations performed in each layer of the CNN (Udupa [0056] “An aspect of the examples presented herein is to optimize convolution operations by reducing the total number of multiplication operations performed in each layer of the CNN, by transforming the multiplication operations to addition operations.”).
Further, Kopinsky teaches storing, in a memory, weights of the DNN model in a compact format that supports branch-less DNN execution (Kopinsky [0046] “Additionally, as elaborated herein (e.g., in relation to FIG. 6), embodiments of the invention may compress the activation-sparse input data to a compressed format that may be devoid of zero-value input data elements, and may thus avoid branching or testing of input data elements at run time. The term “compressed convolution” may therefore be used herein to refer to executing a convolution operation in a layer of a NN, wherein at least one input data structure or element of the convolution operation has a compressed format, devoid of zero-value input data elements.”; [0048] “Embodiments of the invention may include computing a direct convolution when the input is given as a compressed sparse matrix, and the weights are given as a dense matrix with a standard representation.”; [0088] “As elaborated herein, each kernel element of the vector of kernel elements may correspond to a different kernel filter. According to some embodiments, the kernel matrix or tensor data element K may be pre-ordered (e.g., prior to inferring the NN on incoming data) such that the kernel vector may be sequentially stored in a memory device (e.g., RAM device 4A of FIG. 2) associated with the at least one processor (e.g., element 2 of FIG. 2). Thus, processor 2 may be able to contiguously read the kernel vector from the memory device (e.g., 4A) during execution or inference of the NN.” Kopinsky provides avoiding branching during execution of a deep neural network and compressing weights/kernels for storing in memory, corresponding to storing, in a memory, weights of the DNN model in a compact format that supports branch-less DNN execution.).
Xu, Jain, Udupa and Kopinsky are all considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically convolutional neural networks. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu in view of Jain in further view of Udupa with the above teachings of Kopinsky. Doing so would allow for fast matrix multiplication algorithms to aid the performance of neural networks (Kopinsky [0009] “As known in the art, NNs can be described by having their weights and inputs represented as matrices. Computation (e.g., inference) of the represented NN may include a sequential multiplications of these matrices. Thus, fast matrix multiplication algorithms may aid the performance of neural networks.”).
Regarding claim 2, Xu in view of Jain in further view of Udupa and Kopinsky teaches the method of claim 1 as discussed above in the rejection of claim 1, where Xu teaches …performing one or more compiler optimizations based on the sparse convolution patterns for compressed DNN execution (Xu [0058] “Further, in this example, channel rounding is applied during coarse-grained pruning such that the surviving channels in each layer are a multiple of 4 for optimal hardware utilization… Hybrid pruning, in this example, is only applied on the convolutional layers to boost the model to 78% sparsity and it can be further pruned by applying weight pruning on the fully connected layer(s), among other examples”; [0108] “Code 1204, which may be one or more instructions to be executed by processor 1200, may be stored in memory 1202, or may be stored in software, hardware, firmware, or any suitable combination thereof, or in any other internal or external component, device, element, or object where appropriate and based on particular needs. In one example, processor 1200 can follow a program sequence of instructions indicated by code 1204. Each instruction enters a front-end logic 1206 and is processed by one or more decoders 1208. The decoder may generate, as its output, a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals that reflect the original code instruction.” Xu provides hardware optimizations based on sparsity, wherein the hardware includes a decoder 1208 which translates source code into machine readable code to be executed by the processor, which corresponds to a compiler.), but fails to teach wherein step (d) includes converting the DNN model trained in (c) into one or more computational graphs.
However, Jain teaches wherein step (d) includes converting the DNN model trained in (c) into one or more computational graphs (Jain [0051] “For example, the acceleration engine 312 can be a neural network accelerator, and, as such, may be able to perform the large scale, parallel computations of a neural network more efficiently than when the computations are performed by the processors 302, 303.”; [0059] “The first stage 336 may generate a compiled model that includes the various operations of the supported operators to be performed by the components of the acceleration engine 312, in the order that the operations are to be performed. The output can be represented, for example, as a data flow graph, where the nodes in the graph represent memory operations, computations, and other operations, and the edges or connections between the nodes represent dependencies between the nodes, such as data dependencies, memory dependencies, or operational dependencies, among other examples.” Jain provides acceleration engine 312 which is a neural network accelerator that utilizes a data flow graph corresponding to a neural network, corresponding to converting the DNN model trained in (c) into one or more computational graphs.)
Xu, Jain, Udupa and Kopinsky are all considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically convolutional neural networks. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu, Jain, Udupa and Kopinsky with the above teachings of Xu and Jain. Doing so would allow for optimization in memory usage or memory bandwidth usage, and other operations (Jain [0060] “These operations can include, for example, removing redundant dependencies, resolving or handling dependencies between nodes by inserting synchronization instructions into the code, identifying possibly optimizations in memory usage or memory bandwidth usage, and other operations.”).
Regarding claim 3, Xu in view of Jain further view of Udupa and Kopinsky teaches the method of claim 2 as discussed above in the rejection of claim 2, wherein the one or more compiler optimizations are applicable to a CPU or a GPU of the mobile device (Xu [0057] “As discussed above, an improved approach to neural network pruning can enable efficient pruning of network models to allow the model size, related computation consumption, and power consumption to drop, thereby allowing large modern networks to be adapted for and deployed onto limited-resource mobile devices, wearable devices, embedded devices, and other computing systems without significant degradation of the network accuracy.”; [0027] “The preprocessing system 105 may include one or more data processing devices (e.g., a central processing units (CPUs), graphics processing unit (GPUs), tensor processing units (TPUs)) and corresponding hardware accelerators (e.g., machine learning accelerators, matrix arithmetic accelerators, etc.) co-functioning with the processors 210” Xu provides compiler optimizations, which are applicable to a mobile device comprising both CPUs and GPUs.).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu, Jain, Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 2.
Regarding claim 4, Xu in view of Jain further view of Udupa and Kopinsky teaches the method of claim 2 as discussed above in the rejection of claim 2, wherein the one or more compiler optimizations includes performing a fine-grained Layerwise Representation (LR) to capture the sparse convolution patterns and the connectivity sparsity from (a) and (b) (Xu [0028] “In some implementations, the network pruner tool 205 can utilize both coarse-grained and fine-grained pruning to generate a sparse, pruned, or thinned version of a particular neural network”; [0031] “In other cases, multiple different layer-specific threshold weight values may be determined for a neural network model, and fine-grained pruning at any given layer within the neural network model may be pruned based on the corresponding layer-specific value, among other example implementations.”; [0056] “This binary mask is dynamically updated in each iteration of training based on the threshold that is computed from the mean and standard deviation of the weights in each layer with sparsity level controlling factor σ (σ is the same for all the layers).” Xu provides fine-grained pruning by layer to generate sparse neural networks with a sparsity level controlling factor, corresponding to performing a fine-grained Layerwise Representation (LR) to capture the sparse convolution patterns and the connectivity sparsity.).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu, Jain, Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 2.
Regarding claim 7, Xu in view of Jain further view of Udupa and Kopinsky teaches the method of claim 2 as discussed above in the rejection of claim, wherein the one or more compiler optimizations includes performing load redundancy elimination in the DNN model (Jain [0056] “In the example of FIG. 3, the compiler 330 includes a first stage 336 and a second stage 340, which each perform different operations to produce compiled code.”; [0060] “The second stage 340 can compile the operators partitioned to the second stage 340 by the first stage 336, and perform various operations for producing the instructions that are to be executed by the processor 303. These operations can include, for example, removing redundant dependencies, resolving or handling dependencies between nodes by inserting synchronization instructions into the code, identifying possibly optimizations in memory usage or memory bandwidth usage, and other operations.”; [0059] “The output can be represented, for example, as a data flow graph, where the nodes in the graph represent memory operations, computations, and other operations, and the edges or connections between the nodes represent dependencies between the nodes, such as data dependencies, memory dependencies, or operational dependencies, among other examples.” Jain provides removing redundant dependencies for a compiler for a trained DNN model corresponding to performing load redundancy elimination in the DNN model.).
Xu, Jain, Udupa and Kopinsky are all considered to be analogous to the claimed invention because they are in the same field of artificial intelligence and more specifically convolutional neural networks. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu, Jain, Udupa and Kopinsky with the above teaching of Jain. Doing so would allow for optimization in memory usage or memory bandwidth usage, and other operations (Jain [0060] “These operations can include, for example, removing redundant dependencies, resolving or handling dependencies between nodes by inserting synchronization instructions into the code, identifying possibly optimizations in memory usage or memory bandwidth usage, and other operations.”).
Regarding claim 8, Xu in view of Jain further view of Udupa and Kopinsky teaches the method of claim 2 as discussed above in the rejection of claim 2, wherein the one or more compiler optimizations includes automatically tuning configuration parameters (Xu [0054] “For instance, during training pruning and splicing 575 may be performed. After each training iteration, the weight parameters may be updated 580, and the next iteration of training performed with corresponding pruning and splicing 575, and so on until the network stabilizes.” Xu provides automatically updating weight parameters after training, corresponding to automatically tuning configuration parameters.).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu, Jain, Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 2.
Regarding claim 9, it is the system embodiment of claim 1 with similar limitations to claim 1 and is rejected using the same reasoning found above in the rejection of claim 1. Further, Xu teaches a computer system, comprising: at least one processor (Xu [0027] “The preprocessing system 105 may include one or more data processing devices (e.g., a central processing units (CPUs), graphics processing unit (GPUs), tensor processing units (TPUs)) and corresponding hardware accelerators (e.g., machine learning accelerators, matrix arithmetic accelerators, etc.) co-functioning with the processors 210.” Xu provides a system comprising a processor); memory associated with the at least one processor (Xu [0027] “The preprocessing system 105 may further include one or more computer memory elements 215 to store software code (e.g., to implement all or a portion of the network pruner tool 205 and other tools (e.g., 230, 235) of the preprocessing system) as well as data (e.g., 230b, 240, etc.) used in operation of the preprocessing system 105 generally, including the network pruner tool 205 specifically.” Xu provides memory associated with a processor.); and a program supported in the memory (Xu [0027] “The preprocessing system 105 may further include one or more computer memory elements 215 to store software code (e.g., to implement all or a portion of the network pruner tool 205 and other tools (e.g., 230, 235) of the preprocessing system) as well as data (e.g., 230b, 240, etc.) used in operation of the preprocessing system 105 generally, including the network pruner tool 205 specifically.” Xu provides software code corresponding to a program supported in the memory.).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu, Jain, Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 1.
Regarding claim 10, the rejection of claim 9 is incorporated herein. Further, the limitations in this claim are taught by Xu in view of Jain in further view of Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 2.
Regarding claim 11, the rejection of claim 10 is incorporated herein. Further, the limitations in this claim are taught by Xu in view of Jain in further view of Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 3.
Regarding claim 12, the rejection of claim 10 is incorporated herein. Further, the limitations in this claim are taught by Xu in view of Jain in further view of Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 4.
Regarding claim 15, the rejection of claim 10 is incorporated herein. Further, the limitations in this claim are taught by Xu in view of Jain in further view of Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 7.
Regarding claim 16, the rejection of claim 10 is incorporated herein. Further, the limitations in this claim are taught by Xu in view of Jain in further view of Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 8.
Regarding claim 17, it is the computer program product of claim 1 with similar limitations to claim 1 and is rejected using the same reasoning found above in the rejection of claim 1. Further, Xu teaches said program product residing on a non-transitory computer readable medium have a plurality of instructions stored thereon which, when executed by a computer processor, cause that computer processor to (Xu [0104] “In an example, the instructions 1182 provided via the memory 1154, the storage 1158, or the processor 1152 may be embodied as a non-transitory, machine readable medium 1160 including code to direct the processor 1152 to perform electronic operations in the IoT device 1150.” Xu provides a non-transitory computer readable medium have a plurality of instructions stored thereon that causes the processor to perform operations.).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xu, Jain, Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 1.
Regarding claim 18, the rejection of claim 17 is incorporated herein. Further, the limitations in this claim are taught by Xu in view of Jain in further view of Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 2.
Regarding claim 19, the rejection of claim 18 is incorporated herein. Further, the limitations in this claim are taught by Xu in view of Jain in further view of Udupa and Kopinsky for the same reasons disclosed above in the rejection of claim 4.
Response to Arguments
Regarding the rejection applied under 35 U.S.C. 101, Applicant firstly asserts that the present claims are similar to those in Example 39 (“Remarks”, Page 8). Specifically, Applicant asserts that steps (a)-(d) of independent claim 1 are similar to the “applying one or more transformations…” and “training the neural network” steps of Example 39 and therefore the limitations of amended independent claim 1 do not recite any abstract ideas (“Remarks”, Page 8). Applicant further asserts that the “pruning” steps of independent claim 1 are not mentally performable, and are more similar to the “applying one or more transformations…” limitation of Example 39 (“Remarks”, Page 9).
Applicant further asserts that even assuming the claims do recite abstract ideas, any such abstract ideas are integrated into a practical application (“Remarks”, Page 10). Specifically, Applicant asserts that the claimed embodiments provide an improvement “that can generate highly accurate DNN models using pattern-based pruning methods and guarantee execution efficiency with compiler optimizations.” (“Remarks”, Page 10). Applicant further asserts that the “applying a compiler-assisted DNN acceleration framework to the DNN model” comprising removing memory-level input load redundancy provides a solution to inefficient memory access (“Remarks”, Page 10).
However, Example 39 recites applying one or more transformations to digital facial images, including mirroring, rotating, smoothing, or contrast reduction to create a modified set of digital facial images, which was deemed to not recite an abstract idea. The present claims recite “performing an intra-convolution kernel pruning…” and “performing inter-convolution kernel pruning”, which is not the same as applying transformations to digital facial images. Therefore, the present claims are not similar to those of Example 39. Thus, the present claims recite at least the abstract ideas of “performing an intra-convolution kernel pruning…” and “performing inter-convolution kernel pruning”, which merely involves removing values from a matrix, therefore being mentally performable with the assistance of pen and paper.
Further, regarding a solution to inefficient memory accesses, as discussed in MPEP 2106.05(f), “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Further, even assuming the claims do recite an improvement, it would be in the abstract idea of “performing an intra-convolution kernel pruning…” and “performing inter-convolution kernel pruning”. As recited in the MPEP, an improvement in the abstract idea itself is not an improvement in technology. MPEP 2106.05(a).
Therefore, as written, the claims remain rejected under 35 U.S.C. 101.
Regarding the rejection applied under 35 U.S.C. 103, Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/KURT NICHOLAS PRESSLY/Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125