DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 6, 11-13, 21-22 previously pending.
Claims 1, 6, 11-13, 23 currently pending.
Response to Amendments and Remarks
Remarks filed November 5, 2025 have been fully considered.
Rejections under 35 U.S.C. § 112 have not been fully overcome. See rejections under 35 U.S.C. § 112 below for detailed analysis.
Applicant’s arguments regarding the rejections under 35 U.S.C. § 103 with regards to an external host processor have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant further submits that Caffee does not teach “a state controller” as required by claim 1 because it does not issue a distinct loopback-mode command. Examiner respectfully disagrees. Caffee teaches (Fig. 3, element 302 – close switch 122 for near-end loopback; [0025] – “For example, digital logic 104 generates control signals that cause switch 122 to be closed, switch 120 (if present) to remain open, and attenuator 128 to apply a zero-delay loopback attenuation for a near-end loopback mode (302).”). The control signal that causes switch 122 to be closed corresponds to a loopback-mode command by a state controller.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 23 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Namely, the limitation “compensate for the loopback delays when the integrated circuit operates in a ranging mode” lacks sufficient written description in the specification. None of a compensation operation or a ranging mode are mentioned in the instant application specification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 6, 11-13, 21-22 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “sends the plurality of loopback delay measurements to the external host processor for calculation of a time-of-flight value for a UWB channel, wherein the external host processor;” renders the claim indefinite. The phrase “wherein the external host processor” implies additional limitation / description of the external host processor, but no additional limitation / description is recited. The indentation of the last two limitations of the claim further render the claim indefinite. One of ordinary skill in the art at the effective filing date of the invention would not be apprised of the metes and bounds of the claim. Examiner’s best interpretation is that the last two limitations further recite functions of the digital transceiver and should therefore each be indented.
Regarding claim 6, the limitation “non-volatile memory comprising the ultrawideband integrated circuit” renders the claim indefinite. It is unclear how a non-volatile memory could comprise the entire integrated circuit. The integrated circuit described by the claim comprises, e.g., RF transmitter, RF receiver, switch network, and a state controller. It is not clear how a non-volatile memory may comprise these components. Instant application Fig. 2 further shows the non-volatile memory 16 as separate from, not comprising, the RF transmitter, receiver, switch network, and state controller. One of ordinary skill in the art at the effective filing date of the invention would not be apprised of the metes and bounds of the claim. Further, the limitation “coupling the transmitter output to the receiver input by way of a switch network, thereby establishing a direct path between the RF transmitter and the RF receiver” renders the claim indefinite. The recitation “coupling the transmitter output to the receiver input by way of a switch network” requires a switch between the RF transmitter and receiver. However, the recitation “establishing a direct path between the RF transmitter and the RF receiver” in light of instant application specification [0015] – “when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present” appears to recite that the RF transmitter and RF receiver are required to be directly connected and therefore there requires that there are no intervening elements between the transmitter and receiver. These two recitations appear to contradict each other, as it is unclear how the transmitter and receiver may be both coupled by a switch and also not have intervening elements between them. One of ordinary skill in the art at the effective filing date of the invention would not be apprised of the metes and bounds of the claim. Claim 11 recites similar limitations to claim 6 and is indefinite for similar reasons.
Regarding claim 23, the limitation “compensate for the loopback delays when the integrated circuit operates in a ranging mode” renders the claim indefinite. Because none of a compensation operation or a ranging mode are described in the instant application specification, it is unclear, e.g., what is being ranged or how the loopback delays are being compensated for. See rejection under 35 U.S.C. § 112(a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 6, 11-13, 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Caffee (US 2017 /0019269 A1) in view of Hochdorf (US 2011/0205121 A1) and further in view of Jun (US 2005/0136868 A1) and further in view of Malone (US 20060244595 A1).
Regarding claim 1,
Caffee (‘269) teaches:
An ultra-wideband integrated circuit comprising:
a (lined through limitations correspond to limitations not taught by reference) transmitter having a transmitter output; ([0025] – “drive a pulse (or other suitable signal) on node TXA, at the input of analog transmitter 110. The pulse triggers time-to-digital converter 114 to start a time-to-digital conversion. Analog transmitter 110 drives a signal on node TXOUTA”)
an ([0025] – “Analog receiver 112 may amplify, filter, and/or perform other analog signal operations on the pulse signal received from node RXINA, and provides an output analog signal to node RXA (304).”)
a digital interface configured to communicate with an external ([0020] – “Digital logic 104 and digital logic 154 may each be implemented as a single microprocessor circuit, a digital signal processor (DSP), or a plurality of separate dedicated or programmable integrated or other electronic circuits or devices, e.g., hardwired electronic or logic circuits such as discrete element circuits or programmable logic devices” Examiner’s broadest reasonable interpretation of “external processor” in light of the specification includes any processor external to the integrated circuit recited in the preamble of the claim. Therefore, when logic 104/154 is implemented as, e.g., a plurality of integrated circuits, the integrated circuits are external to one another with a digital interface for communication between them.)
a non volatile memory; ([0020] – “storage 132 may be… non-volatile”)
a switch network operably coupled between the transmitter output and the receiver input, the switch network being configured to selectively couple the transmitter output to the receiver input to establish a signal path between the RF transmitter and RF receiver; (Fig. 1 – switch 122 or 172; Fig. 3, element 302 – close switch 122 for near-end loopback, element 304 – transmit pulse from TXA to RXA over near-end loopback path. Examiner notes that instant application specification para 15 recites “when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.”)
a state controller configured to generate a control signal that indicates when, in a loopback mode, the transmitter output is to be coupled to the receiver input; (Fig. 3, element 302 – close switch 122 for near-end loopback; [0025] – “For example, digital logic 104 generates control signals that cause switch 122 to be closed, switch 120 (if present) to remain open, and attenuator 128 to apply a zero-delay loopback attenuation for a near-end loopback mode (302).”) and
a digital transceiver operably coupled to the state controller such that in response to receiving from the state controller the control signal indicating the loopback mode, to the digital transceiver:
controls the switch network to couple the transmitter output to the receiver input; (Fig. 3, element 302 – close switch 122 for near-end loopback; [0025] – “For example, digital logic 104 generates control signals that cause switch 122 to be closed, switch 120 (if present) to remain open, and attenuator 128 to apply a zero-delay loopback attenuation for a near-end loopback mode (302).”)
causes the ([0025] – “Digital logic 104 configures digital-to-analog converter 106 to drive a pulse (or other suitable signal) on node TXA, at the input of analog transmitter 110. The pulse triggers time-to-digital converter 114 to start a time-to digital conversion.”) a plurality of(lined through limitations correspond to limitations not taught by reference) frames ([0018] – “one or more time interval signals defined by a start indicator and a stop indicator of the time interval and are configured to generate digital value D.sub.OUT corresponding to the relative time elapsed during that time interval”) directly through the path to the(Fig. 1 – switch 122; Fig. 3, element 302 – close switch 122 for near-end loopback, element 304 – transmit pulse from TXA to RXA over near-end loopback path. Examiner notes that the recited signal path is established via coupling of the transmitter output to the receiver input. Examiner further notes that instant application specification 15 recites “when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.” Therefore, the broadest reasonable interpretation of “directly through the path” in light of the specification includes “directly through a path that includes intervening elements between the coupled elements.”)
measures a loopback delay for each of the plurality of ([0018] – “one or more time interval signals defined by a start indicator and a stop indicator of the time interval and are configured to generate digital value D.sub.OUT corresponding to the relative time elapsed during that time interval” [0014] – “node 102 periodically initiates transceiver calibration technique 200 to update distance measurements in response to a change in relative position of the nodes during steady-state communications.”) received by the ([0025] – “The pulse signal on node RXA triggers a stop to the time-to-digital conversion of time-to-digital converter 114. Time-to-digital converter 114 provides a resulting digital output code D.sub.OUT to digital logic 104, which may store digital output code D.sub.OUT as an indicator of the near-end transceiver latency t.sub.txrx1 (306).” [0019] – “relative time interval indicated by the corresponding digital value D.sub.OUT of TDC 114”) (Fig. 3, step 308 – “determine t.sub.txrx1. based on D.sub.out of TDC 114”; [0025] – “digital logic 104 determines and stores near-end transceiver latency t.sub.txrx1.”)
sends the plurality of loopback delay measurements to the ([0020] – “Digital logic 104 and digital logic 154 may each be implemented as a single microprocessor circuit, a digital signal processor (DSP), or a plurality of separate dedicated or programmable integrated or other electronic circuits or devices, e.g., hardwired electronic or logic circuits such as discrete element circuits or programmable logic devices” [0031] – “node 152 transmits far-end transceiver latency t.sub.t×r×2 or the one or more indicators of far-end transceiver latency τ.sub.t×r×2, as the case may be, to node 102” Examiner further notes that node 152 determines its own latency “far-end transceiver latency” in the same way that node 102 determines its own latency “near-end latency” and transmits its far-end latency to node 102 and its digital logic 104) for calculation of a time-of-flight value for a ([0031] – “Node 102 uses the latency information associated with node 102 and node 152 to determine a channel latency or time-of-flight t.sub.TOF (210): t.sub.TOF = (t.sub.roundtrip – t.sub.txrx1. – t.sub.txrx2) / 2”)
([0031] – “Node 102 uses the latency information associated with node 102 and node 152 to determine a channel latency or time-of-flight t.sub.TOF (210): t.sub.TOF = (t.sub.roundtrip – t.sub.txrx1. – t.sub.txrx2) / 2”) and
stores the time-of-flight value in the non-volatile memory. . ([0040-41] – “The resulting time-of-flight estimate accounts for the latencies of a near-end transceiver and the latencies of a far-end transceiver and may be used to determine an improved estimate of distance... (212)… transceiver calibration technique 200 to update distance measurements”)
Hochdorf teaches:
an interface configured to receive from the processor the time-of-flight value for the UWB channel calculated from the plurality of loopback delay measurements sent by the digital transceiver; (Figs. 3, 4 – storage; [0035-36] – “travel time of the signal in the space D.sub.sp=D.sub.measured-(D.sub.Tx+D.sub.Rx)… D.sub.sp'=D.sub.measured'-D.sub.Tx'-D.sub.Rx” [0044] – “based on the initial internal delays (e.g. D.sub.Tx, D.sub.RX) and the specified calculated change in time delays, the real time D.sub.Tx' and D.sub.Rx' internal delays can be determined and used for obtaining the D.sub.sp'” [0113-1118] - The latest delay shift estimation together with the initial delay can be regarded as the current real time travel time of the signal in the space D.sub.sp'. Now a set of measurements takes place where each direct signal previously stored is replaced with a new measured obstacle-influenced signal. Any change in direct signals henceforth will be referenced to these stored signals and the additional delay will be added or subtracted from D.sub.sp'. Examiner notes that the broadest interpretation of the claimed “interface” in light of the specification includes a storage unit configured such that data can be passed between a processor and the memory. See instant application specification [0021].)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Hochdorf’s known technique to Caffee’s ready for improvement to yield predictable results. Such a finding is proper because (1) Caffee teaches a base method of TOF calculation and using the calculated TOF for distance determination in digital logic comprising storage; (2) Hochdorf teaches a specific technique of storing TOF values in a storage unit configured such that TOF values pass between the processor and memory; (3) Caffee teaches [0020] – “Digital logic 104 and digital logic 154 may each be implemented as a single microprocessor circuit, a digital signal processor (DSP), or a plurality of separate dedicated or programmable integrated or other electronic circuits or devices, e.g., hardwired electronic or logic circuits such as discrete element circuits or programmable logic devices” one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an improved system; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Jun (‘868) teaches:
a radio frequency (RF) transmitter ([0011] – “Ultra Wide Band (UWB) transmitting and receiving device including a receiver and a transmitter” Examiner notes that UWB uses radio frequencies)
an RF receiver ([0011] – “Ultra Wide Band (UWB) transmitting and receiving device including a receiver and a transmitter”)
control the RF transmitter to transmit a plurality of ultra-wideband frames directly to the RF receiver; (Fig. 1; [0021] – “the UWB transmitting and receiving device is transmitting signals, a part of a transmission signal being transmitted to the antenna 80 is applied to the receiver via the coupler 100. The switch 100 is closed in order for the output of the coupler 100 to be input to the receiver amplifier 60, in response to a control signal from a controller (not shown).”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Jun’s known technique to Caffee’s base device ready for improvement to yield predictable results. Such a finding is proper because (1) Caffee teaches a base method using loopback configurations by coupling transmitter directly to receiver; (2) Jun teaches a specific technique of coupling transmitter directly to receiver in RF UWB devices; (3) Hochdorf teaches, e.g., at [0043-47], use of measured delays and time of flights for use in UWB ranging. Caffee teaches at [0043] - "For example, while the invention has been described in an embodiment in which nodes transmit pulse signals for evaluating latency, one of skill in the art will appreciate that the teachings herein can be utilized with other signal types that may be used to trigger evaluation of a time interval by a time-to-digital converter." One of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an improved system; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Malone (‘595) teaches:
external host processor ([0014] – “transceiver 12 is integrated in a circuit board card that is then coupled to a host computer, which processes the received data and controls some of the communication with transponder 20… ”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Malone’s known technique to Caffee’s ready for improvement to yield predictable results. Such a finding is proper because (1) Caffee teaches a base method of sending loopback delay measurements to external processors, e.g., from one IC to another IC of digital logic 104, or from digital logic 154 to digital logic 104; (2) Malone teaches a specific technique of using a host computer for processing; (3) Caffee teaches [0020] – “Digital logic 104 and digital logic 154 may each be implemented as a single microprocessor circuit, a digital signal processor (DSP), or a plurality of separate dedicated or programmable integrated or other electronic circuits or devices, e.g., hardwired electronic or logic circuits such as discrete element circuits or programmable logic devices” ([0031] – “node 152 transmits far-end transceiver latency t.sub.t×r×2 or the one or more indicators of far-end transceiver latency τ.sub.t×r×2, as the case may be, to node 102… Node 102 uses the latency information associated with node 102 and node 152 to determine a channel latency or time-of-flight t.sub.TOF (210): t.sub.TOF = (t.sub.roundtrip – t.sub.txrx1. – t.sub.txrx2) / 2”) one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an IC with decreased processing requirements due to performing processing at an external host; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Regarding claim 6,
Caffee (‘269) teaches:
A method of calibrating an ultra-wideband integrated circuit having a radio frequency (RF) transmitter, an RF receiver, and a switch network configured to selectively couple the RF transmitter to the RF receiver, a state controller configured to generate a control signal that indicates when, in a loopback mode, the switch network is to couple a transmitter output to a receiver input, and a digital transceiver operably coupled to the state controller to respond to the control signal by executing the method comprising:
receiving the control signal from the state controller; (Fig. 3, element 302 – close switch 122 for near-end loopback; [0025] – “For example, digital logic 104 generates control signals that cause switch 122 to be closed, switch 120 (if present) to remain open, and attenuator 128 to apply a zero-delay loopback attenuation for a near-end loopback mode (302).”)
coupling the transmitter output to the receiver input by way of a switch network, thereby establishing a direct path between the RF transmitter and the RF receiver (Fig. 3, element 302 – close switch 122 for near-end loopback; See rejection under 35 U.S.C. § 112(b).) and causing the ([0018] – “one or more time interval signals defined by a start indicator and a stop indicator of the time interval and are configured to generate digital value D.sub.OUT corresponding to the relative time elapsed during that time interval”) directly to the (Fig. 3, element 302 – close switch 122 for near-end loopback; [0025] – “For example, digital logic 104 generates control signals that cause switch 122 to be closed, switch 120 (if present) to remain open, and attenuator 128 to apply a zero-delay loopback attenuation for a near-end loopback mode (302).”)
measuring a loopback delay for each of the plurality of ([0018] – “one or more time interval signals defined by a start indicator and a stop indicator of the time interval and are configured to generate digital value D.sub.OUT corresponding to the relative time elapsed during that time interval” [0014] – “node 102 periodically initiates transceiver calibration technique 200 to update distance measurements in response to a change in relative position of the nodes during steady-state communications.”) received by the ([0025] – “The pulse signal on node RXA triggers a stop to the time-to-digital conversion of time-to-digital converter 114. Time-to-digital converter 114 provides a resulting digital output code D.sub.OUT to digital logic 104, which may store digital output code D.sub.OUT as an indicator of the near-end transceiver latency t.sub.txrx1 (306).” [0019] – “relative time interval indicated by the corresponding digital value D.sub.OUT of TDC 114”) (Fig. 3, step 308 – “determine t.sub.txrx1. based on D.sub.out of TDC 114”; [0025] – “digital logic 104 determines and stores near-end transceiver latency t.sub.txrx1.”)
sending the plurality of loopback delay measurements through an interface to an ([0020] – “Digital logic 104 and digital logic 154 may each be implemented as a single microprocessor circuit, a digital signal processor (DSP), or a plurality of separate dedicated or programmable integrated or other electronic circuits or devices, e.g., hardwired electronic or logic circuits such as discrete element circuits or programmable logic devices”)
([0031] – “Node 102 uses the latency information associated with node 102 and node 152 to determine a channel latency or time-of-flight t.sub.TOF (210): t.sub.TOF = (t.sub.roundtrip – t.sub.txrx1. – t.sub.txrx2) / 2”) and
([0020] – “storage 132 may be… non-volatile”)
Hochdorf teaches:
receiving from the processor the time-of-flight value for the (Figs. 3, 4 – storage; [0035-36] – “travel time of the signal in the space D.sub.sp=D.sub.measured-(D.sub.Tx+D.sub.Rx)… D.sub.sp'=D.sub.measured'-D.sub.Tx'-D.sub.Rx” [0044] – “based on the initial internal delays (e.g. D.sub.Tx, D.sub.RX) and the specified calculated change in time delays, the real time D.sub.Tx' and D.sub.Rx' internal delays can be determined and used for obtaining the D.sub.sp'” [0113-1118] - The latest delay shift estimation together with the initial delay can be regarded as the current real time travel time of the signal in the space D.sub.sp'. Now a set of measurements takes place where each direct signal previously stored is replaced with a new measured obstacle-influenced signal. Any change in direct signals henceforth will be referenced to these stored signals and the additional delay will be added or subtracted from D.sub.sp'.)
storing the time-of-flight value in memory; (Figs. 3, 4 – storage; [0035-36] – “travel time of the signal in the space D.sub.sp=D.sub.measured-(D.sub.Tx+D.sub.Rx)… D.sub.sp'=D.sub.measured'-D.sub.Tx'-D.sub.Rx” [0044] – “based on the initial internal delays (e.g. D.sub.Tx, D.sub.RX) and the specified calculated change in time delays, the real time D.sub.Tx' and D.sub.Rx' internal delays can be determined and used for obtaining the D.sub.sp'” [0113-1118] - The latest delay shift estimation together with the initial delay can be regarded as the current real time travel time of the signal in the space D.sub.sp'. Now a set of measurements takes place where each direct signal previously stored is replaced with a new measured obstacle-influenced signal. Any change in direct signals henceforth will be referenced to these stored signals and the additional delay will be added or subtracted from D.sub.sp'.) and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Hochdorf’s known technique to Caffee’s ready for improvement to yield predictable results. Such a finding is proper because (1) Caffee teaches a base method of TOF calculation and using the calculated TOF for distance determination in digital logic comprising storage; (2) Hochdorf teaches a specific technique of storing TOF values in a storage unit configured such that TOF values pass between the processor and memory; (3) Caffee teaches [0020] – “Digital logic 104 and digital logic 154 may each be implemented as a single microprocessor circuit, a digital signal processor (DSP), or a plurality of separate dedicated or programmable integrated or other electronic circuits or devices, e.g., hardwired electronic or logic circuits such as discrete element circuits or programmable logic devices” one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an improved system; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Jun (‘868) teaches:
a radio frequency (RF) transmitter ([0011] – “Ultra Wide Band (UWB) transmitting and receiving device including a receiver and a transmitter” Examiner notes that UWB uses radio frequencies)
an RF receiver ([0011] – “Ultra Wide Band (UWB) transmitting and receiving device including a receiver and a transmitter”)
control the RF transmitter to transmit a plurality of ultra-wideband frames directly to the RF receiver; (Fig. 1; [0021] – “the UWB transmitting and receiving device is transmitting signals, a part of a transmission signal being transmitted to the antenna 80 is applied to the receiver via the coupler 100. The switch 100 is closed in order for the output of the coupler 100 to be input to the receiver amplifier 60, in response to a control signal from a controller (not shown).”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Jun’s known technique to Caffee’s base device ready for improvement to yield predictable results. Such a finding is proper because (1) Caffee teaches a base method using loopback configurations by coupling transmitter directly to receiver; (2) Jun teaches a specific technique of coupling transmitter directly to receiver in RF UWB devices; (3) Hochdorf teaches, e.g., at [0043-47], use of measured delays and time of flights for use in UWB ranging. Caffee teaches at [0043] - "For example, while the invention has been described in an embodiment in which nodes transmit pulse signals for evaluating latency, one of skill in the art will appreciate that the teachings herein can be utilized with other signal types that may be used to trigger evaluation of a time interval by a time-to-digital converter." One of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an improved system; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Malone (‘595) teaches:
external host processor ([0014] – “transceiver 12 is integrated in a circuit board card that is then coupled to a host computer, which processes the received data and controls some of the communication with transponder 20… ”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Malone’s known technique to Caffee’s ready for improvement to yield predictable results. Such a finding is proper because (1) Caffee teaches a base method of sending loopback delay measurements to external processors, e.g., from one IC to another IC of digital logic 104, or from digital logic 154 to digital logic 104; (2) Malone teaches a specific technique of using a host computer for processing; (3) Caffee teaches [0020] – “Digital logic 104 and digital logic 154 may each be implemented as a single microprocessor circuit, a digital signal processor (DSP), or a plurality of separate dedicated or programmable integrated or other electronic circuits or devices, e.g., hardwired electronic or logic circuits such as discrete element circuits or programmable logic devices” ([0031] – “node 152 transmits far-end transceiver latency t.sub.t×r×2 or the one or more indicators of far-end transceiver latency τ.sub.t×r×2, as the case may be, to node 102… Node 102 uses the latency information associated with node 102 and node 152 to determine a channel latency or time-of-flight t.sub.TOF (210): t.sub.TOF = (t.sub.roundtrip – t.sub.txrx1. – t.sub.txrx2) / 2”) one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an IC with decreased processing requirements due to performing processing at an external host; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Regarding claim(s) 11,
Claim(s) 11 is a method of calibrating an ultra-wideband-based product corresponding to the method of calibrating an ultra-wideband integrated circuit claim 6. Accordingly, the Examiner’s remarks and application of the prior art with respect to claim(s) 11 are substantially the same as those made above with respect to claim(s) 6.
Regarding claim 12,
Caffee (‘269) in view of Hochdorf (‘121) and further in view of Jun (‘868) and further in view of Malone teaches the invention as claimed and discussed above.
Caffee (‘269) further teaches:
The method of calibrating the ultra-wideband-based product of claim 11 wherein the non-volatile memory of the ultra-wideband based product is a one-time-programmable memory. ([0020] – “Similarly, the non-alterable or fixed memory may be implemented using any one or more of ROM, PROM, EPROM, EEPROM, or other non-alterable memory known in the art.”)
Regarding claim 13,
Caffee (‘269) in view of Jun (‘868) and further in view of Hochdorf (‘121) and further in view of Malone teaches the invention as claimed and discussed above.
Caffee (‘269) further teaches:
The method of calibrating the ultra-wideband–based product of claim 11 further comprising an interface through which the transceiver sends the plurality of loopback delay measurements to the external host processor and receive the time-of-flight value from the external host processor. (Fig. 2; [0031] – “node 152 transmits far-end transceiver latency t.sub.t×r×2 or the one or more indicators of far-end transceiver latency τ.sub.t×r×2, as the case may be, to node 102.” [0020] – “Digital logic 104 and digital logic 154 may each be implemented as a single microprocessor circuit, a digital signal processor (DSP), or a plurality of separate dedicated or programmable integrated or other electronic circuits or devices”)
Regarding claim 23,
Caffee (‘269) in view of Hochdorf (‘121) and further in view of Jun (‘868) and further in view of Malone teaches the invention as claimed and discussed above.
Caffee (‘269) further teaches:
The ultra-wideband integrated circuit of claim 1, wherein the time-of-flight value stored in the non-volatile memory is used by the digital transceiver to compensate for the loopback delays when the integrated circuit operates in a ranging mode, thereby improving the accuracy of distance measurements. ([0040-41] – “The resulting time-of-flight estimate accounts for the latencies of a near-end transceiver and the latencies of a far-end transceiver and may be used to determine an improved estimate of distance... (212)… transceiver calibration technique 200 to update distance measurements” Time of flight estimate T.sub.TOF compensates for transceiver latency ranging errors and is dependent upon t.sub.roundtrip, which is measured based on loopback delays during a transmit/receive mode on the UWB channel. See also rejections under 35 U.S.C. § 112.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20230341541 A1 to Barratt teaches a system for detecting proximity between a first transceiver and a second transceiver via time-of-flight measurements. The first and the second transceivers are configured to estimate a primary communication distance between the primary radio module of the first transceiver and the primary radio module of the second transceiver, and estimate a secondary communication distance between the secondary radio module of the first transceiver and the secondary radio module of the second transceiver. According to one embodiment, the secondary radio module 130 may consist of or comprise a radio module with UWB. Via this type of secondary radio module, it is then possible to estimate a secondary distance value with a better accuracy than that obtained during the estimation of the primary distance value.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JULIANA CROSS/Examiner, Art Unit 3648
/William Kelleher/Supervisory Patent Examiner, Art Unit 3648