Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim status
Original claims 1-20 filed 3/15/2021 are pending.
Priority
This application filed 3/15/2021 is a continuation of 15/594627 filed 5/14/2017 (now US Patent 10990551) which is a continuation of 14/608414 (now US patent 9658977) filed 1/29/2015 which is a CIP of 14/213495 (now US patent 9740798) filed 3/14/2014 and claims benefit to US provisional applications 61/940472 filed 11/6/2014 and 61/940009 filed 2/14/2014; and
is related to several pending US applications 17/702785 filed 3/16/2021, 17/202962 filed 3/16/2021, 17/201243 filed 3/15/2021 (not docketed); and
to issued applications 15/669451 now US Patent 10911451, 15/669136 now US Patent 10983939, 15/670195 now US Patent 10977314, 14/608464 now US Patent 9727510 and 14/201824 now US Patent 97342284;
all through the claim of priority to US provisional applications and related inventors and assignee/Applicant.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 10990551 (continuation parent US Application 14/608414). Although the claims at issue are not identical, they are not patentably distinct from each other because the only difference between the claims is the limitation for the use a plurality of field programmable gate arrays (instantly claimed) versus one or more field programmable gate arrays (in 9658977).
The present claims fall completely inside the claims of ‘977, and ‘977 differs from the instant application with the possible use of only one field programmable gate array. A copy of the claims is provided below for comparison.
Instant application:
Claim 1 A method of configuring a computing system having a first configuration bit image for a first application stored in a memory circuit, the method comprising:
configuring a first configurable logic circuit with a communication functionality, the communication functionality provided in a second configuration bit image stored in a nonvolatile memory;
using a processor circuit, transmitting a first message to the first configurable logic circuit, the first message comprising a first memory address of the first configuration bit image in the memory circuit;
using a DMA engine of the first configurable logic circuit, accessing the memory circuit and obtaining the first configuration bit image; using the first configuration bit image, the first configurable logic circuit self-configuring for the first application; and u
sing the first field programmable gate array, transmitting the first configuration bit image to at least one second field programmable gate array of the plurality of field programmable gate arrays.
In 10990551:
Claim 1. A method of configuring a system having at least one host computing system and a plurality of field programmable gate arrays, the method comprising: 5 using a host processor, storing a first configuration bit image for a first application in a host memory; configuring one or more primary field programmable gate arrays, of the plurality of field programmable gate arrays, with a communication functionality, the communication functionality provided in a second configuration bit image stored in a 10 nonvolatile memory; using the host processor, transmitting a first message to the one or more primary field programmable gate arrays, the first message comprising a first memory address of the first configuration bit image in the host memory; using a DMA engine, for each primary field programmable gate array, 15 accessing the host memory and obtaining the first configuration bit image; and using the first configuration bit image, each primary field programmable gate array self-configuring for the first application.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 9658977 (US Application 14/608414). Although the claims at issue are not identical, they are not patentably distinct from each other because the only difference between the claims is the limitation for the use a plurality of field programmable gate arrays (instantly claimed) versus one or more field programmable gate arrays (in 9658977).
The present claims fall completely inside the claims of ‘977, and ‘977 differs from the instant application with the possible use of only one field programmable gate array. A copy of the claims is provided below for comparison.
In 9658977:
Claim 1. A method of configuring a system having at least one host computing system and one or more field programmable gate arrays, the method comprising: 10 using a host processor, storing a first configuration bit image for a first application in a host memory; configuring the one or more field programmable gate arrays with a communication functionality, the communication functionality provided in a second configuration bit image stored in a nonvolatile memory; 15 using the host processor, transmitting a first message to one or more primary field programmable gate arrays, the first message comprising a first memory address of the first configuration bit image in the host memory; using a DMA engine, each primary field programmable gate array accessing the host memory and obtaining the first configuration bit image; and 20 using the first configuration bit image, each primary field programmable gate array self-configuring for the first application.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 9740798 (US Application 14/213495). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims while varying slightly in structure of the recitation of the components, are drawn to the same system and method as presently claimed.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 9727510 (US Application14/608464). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims while varying slightly in structure of the recitation of the components, are drawn to the same system and method as presently claimed.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 9734284 (US Application14/201824). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims while varying slightly in structure of the recitation of the components, are drawn to the same system and method as presently claimed.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 9740798 (US Application 14/213495). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims while varying slightly in structure of the recitation of the components, are drawn to the same system and method as presently claimed.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 10911451 (US Application 15/669451). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims while varying slightly in structure of the recitation of the components, are drawn to the same system and method as presently claimed.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 10983939 (US Application 15/669136). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims while varying slightly in structure of the recitation of the components, are drawn to the same system and method as presently claimed.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 10977314 (US Application 15/670195). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims while varying slightly in structure of the recitation of the components, are drawn to the same system and method as presently claimed.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 9727510 (US Application 14/608464). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims while varying slightly in structure of the recitation of the components, are drawn to the same system and method as presently claimed.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 97342284 (US Application 14/201844). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims while varying slightly in structure of the recitation of the components, are drawn to the same system and method as presently claimed.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of copending Application Nos. 17/702785, 17/202962, 17/201243 (none docketed, in pre-exam). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims while varying slightly in structure of the recitation of the components, are drawn to the same system and method as presently claimed.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
No claim is allowed.
In review of the art of record at the time of filing, Peter Alfke (XAPP 091 Nov 24, 1997), Mueller et al. (VLDB Aug 24, 2009) and Matthew M. Hosler together provide evidence that PCIe communication networks, memory, switches in circuits and FPGAs were all well known in the art (note-Alfke, Mueller and Hosler provided in parent application). Moreover, the suggestion for using coupled FPGAs to replace CPUs for data analysis were also known prior to the filing date of the instant application. For example, Alfke teaches that different generations of FPGAs were known and that providing them in series could be designed and successfully configured to work together. Mueller et al provide suggestions and greater detail on using FPGA in a variety of architectures and specifically for FPGAs use in sorting networks and in parallel processing for specific data processing (versus the general use CPU) in computing systems. Mueller et al. provide various considerations in the design of the architecture for use of the FPGAs, memory, with the CPU and other circuits in which it may be used. Similar to Mueller et al., Hosler provides examples of architectures and advantages to the use of FPGAs (for example how the flexibility of the configuration can be modified through instruction to the SRAM bits). However, none of the cited references specifically state the use of PCIe (Peripheral Component Interconnect Express or PCI-E—which is broadly a serial expansion bus standard for connecting a computer to one or more peripheral devices) or nonblocking crossbar switches, these means of linking components were standard and well known and used at the time of filing. Clearly each of the cited references provide that the FPGA in a hardware setup that would be coupled to a circuit board and so providing a FPGA in communication to memory circuits using a PCI is obvious in light of the various configurations suggested in the teachings of the cited references since they are connected to a larger system for design testing of any of the various possible architectures.
While each of the hardware components were known and each of the components required of the claim were general known to provide FPGAs in an architecture to process data to free the host system CPU, there is no specific motivation nor does it appear obvious to provide a system comprising a plurality of PCIe, memory and FPGAs to for a configurable logic circuit which provided for by a second configuration bit image for an application to communicate configurations to a plurality of FPGA as recited and required by the final limitation of the claims. Further, it is noted that FPGAs in the cited references were configured by external devices, and not self-configuring as required by the claim and thus the cited references teach away from the instantly claimed invention.
While given the level of knowledge and understanding of the how the individual components operate and inter operate (for example details in Alfke), it might have been obvious to provide and test a variety of architectures and programing, it would not have been obvious to design specific architectures claimed even with the generally teaching and evidence of Hosler for the processing of different types of carry chain architecture to test and find optimal performance.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph T Woitach whose telephone number is (571)272-0739. The examiner can normally be reached Mon-Fri; 8:00-4:00.
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/Joseph Woitach/Primary Examiner, Art Unit 1687