Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Applicants Amendment
Applicant’s amendment filed 12/30/2025 has been received and entered. Claims 21-40 have been amended, claims 1-20 have been cancelled.
Claims 21-40 are pending.
Priority
This application filed 3/16/2021 is a continuation of applications 15/669451 now US Patent 10911451, which is a continuation of 14/201824 now US Patent 97342284 which claims benefit to four US provisional applications: 61/790407 filed 3/15/2013, 61/790720 filed 3/15/2013, 61/940009 filed 2/14/2014, and 61/9402014 filed 2/16/2014; and
is related to application 15/670195 filed 8/7/2017 now US Patent 10977314 which is a continuation of 14/213495 filed 3/14/2014, now US Patent 9740798; and is related to several pending US applications 17/702762 filed 3/16/2021, 17/202962 filed 3/16/2021, 17/201022 filed 3/15/2021 (not docketed); and to issued applications 15/669136 now US Patent 10983939, 14/608464 now US Patent 9727510; all through the claim of priority to US provisional applications and related inventors and assignee/Applicant.
There is no comment regarding the summary of priority in the instant response.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
Response to Applicants comments
The terminal disclaimers filed 12/30/2025 have been approved (see paper entered 1/16/2026). The terminal disclaimers have addressed the rejections regarding:
U.S. Patent No. 9734284 (US Application 14/201824);
U.S. Patent No. 10911452 (US Application 15/669451, parent of instant application);
U.S. Patent No. 10977314 (US Application 15/670195);
Application No. 17/201243 (foam mailed);
U.S. Patent No. 10990551 (US Application 14/608414);
U.S. Patent No. 9658977 (US Application 14/608414);
U.S. Patent No. 9740798 (US Application 14/213495);
U.S. Patent No. 9727510 (US Application14/608464);
U.S. Patent No. 9740798 (US Application 14/213495);
U.S. Patent No. 10983939 (US Application 15/669136);
U.S. Patent No. 9727510 (US Application 14/608464);
U.S. Patent No. 97342284 (US Application 14/201844);
Application No. 17/202962;
Application No. 17/202962 ; and
Application No. 17/201022.
Accordingly, the rejections are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
Response to Applicants comments
Applicants note the issue and point to several portions of the specification that provide various aspects for the structural features, and argue the skilled artisan would readily understand from the specification what was required of the claims.
In response, Examiner agrees with Applicants comments and notes the issue was raised under 112f only and was not an issue under 112b.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, with respect to claim 21 it has been amended to remove the intended purpose and inserted a method ‘at a system’ and it is unclear what this is meant to indicate. It is unclear if the claim is now directed to the method by itself at or on a system or if the method is implemented on the system. The structure of the system is provided, and then provides ‘using’ the FPGAs and it is unclear how they are used specifically, if they use the same or that each step requires a different FPGA, or how any the steps are specifically supposed to be performed at the system as now claimed. Dependent claims fail to clarify the issue and are included in the basis of the rejection.
Specifically, with respect to claim 33, it has been similarly amended and it is unclear how the system is configured and what the final outcome is required for ‘configured to’. It is unclear if the claims simply require the structure and a physical configuration, or if the method steps are integral to the system itself. The metes and bounds are unclear because there are alternative ways of interpreting the system and specific requirements of the claims.
Amending the claims to provide a clear requirement of the system and how the FPGA are configured to perform the steps would address the basis of the rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
Claims 21-40 stand rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Peter Alfke (XAPP 091 Nov 24, 1997), Mueller et al. (VLDB Aug 24, 2009)(each of record in parent application), Accolade Technology (2013), Renesas (2007) and Texas Instruments (2013).
Response to Applicants Arguments
Applicants provide an underlined version of the claims with steps of analyzing short read sequences for the method claim 21 and argue that while the references teach a FPGA, they fail to provide their use in gene sequencing.
In response, Examiner acknowledges that the method of analysis of sequence reads is not provided in the references, but the claims were interpreted to simply require a FPGA that can be configured or a system comprising FPGA that could perform the steps and did not necessarily require and specific coding and just ‘using’ the FPGA generically.
Rejection of record
The structural requirements of the system of the product claims for a system as set forth in claims 33-40 claim comprises using field programmable gate arrays coupled by communication lines to memory circuits and logic circuits, and claim 21 sets forth the same limitations in the context of a method which where the use is comparing sequence data for protein sequence analysis Dependent claims provide more details on the configurable function of the system, such as designations to be provided in header information and DMA registry consistent with the logic circuits. In review of the art of record at the time of filing, Peter Alfke (XAPP 091 Nov 24, 1997) and Mueller et al. (VLDB Aug 24, 2009)(each of record in parent application) together provide evidence that communication networks comprising memory, switches in circuits and FPGAs were all well known in the art. More specifically, together they provide a system using coupled FPGAs to replace CPUs for data analysis were also known prior to the filing date of the instant application. For example, Alfke teaches that different generations of FPGAs were known and that providing them in series could be designed and successfully configured to work together. Mueller et al provide suggestions and greater detail on using FPGA in a variety of architectures and specifically for FPGAs use in sorting networks and in parallel processing for specific data processing (versus the general use CPU) in computing systems. Mueller et al. provide various considerations in the design of the architecture for use of the FPGAs, memory, with the CPU and other circuits in which it may be used. Mueller et al. provides examples of architectures and advantages to the use of FPGAs (for example how the flexibility of the configuration can be modified through instruction to the SRAM bits). A review of the art for different architectures provide for systems such as Accolade Technology and the PCIE Gen 3 family of Packet Processing Adapters. The Accolade's ANIC-40K3 at the time was the industry's first PCIE Gen 3 FPGA based packet capture and application acceleration adapter capable of transferring 40 Gbps across a PCI Express bus. The ANIC-40K3 comprised quad 10 GigE ports over 8 PCI Express Gen 3 lanes with 8 GB on board DDR3 DRAM buffer. For the operation, the APP version 5.0 was implemented in a State-of-the-Art FPGA introducing unique features including Hash Based Packet Classification supporting up to 48 million flows, Traffic Management and De-duplication. Another example, Renesas provided the hardware design guide for the 89HPES16T4G2 & 89HPES12T3G2. In review, this document provides system design guidelines for IDT 89HPES16T4G2 PCI Express® (PCIe®) 2.0 base specification compliant switch device to create a system architecture comprising SMBus Interfaces which are capable for the Master SMBus to interface and provide a connection for an optional external serial EEPROM used for initialization and optional external I/O expanders.
2Also, for a slave SMBus interface provides full access to all software visible registers in the
PES16T4G2, allowing every register in the device to be read or written by an external SMBus master, and also for the slave SMBus to also be used to preload the serial EEPROM used for initialization. Similarly, Texas Instruments provided for the KeyStone Architecture Peripheral Component Interconnect Express (PCIe) and provided a user guide that describes the features, architecture, and details of the Peripheral Component Interconnect Express (PCIe). For TI, it provided for a 3rd Generation I/O Interconnect technology succeeding ISA and PCI bus that is designed to be used as a general-purpose serial I/O interconnect in multiple market segments,
including desktop, mobile, server, storage and embedded communications as illustrated in the figure:
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Given the various architecture known in the art and that the claims encompass the component parts of a PCIe switch, communication lines, memory circuits and logic circuits set up into a system, it would have been prima facie obvious to one having ordinary skill in the art at the time the invention was made to provide necessary design and architecture of the components to effectively operate. One having ordinary skill in the art would have been motivated to provide such systems with a number and variety of architectures and specifically for FPGAs use in sorting networks and in parallel processing for specific data process as suggested in Muller. Given the level of skill in the art demonstrated by the many available configurations and systems, there would have been a reasonable expectation of success to provide a PCIe switch, communication lines, memory circuits and logic circuits, with additional processor circuits to achieve any variety of architectures and capable of serving in networks and in parallel processing for specific data processes
Thus, the claimed invention as a whole was clearly prima facie obvious.
Conclusion
No claim is allowed.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph T Woitach whose telephone number is (571)272-0739. The examiner can normally be reached Mon-Fri; 8:00-4:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Karlheinz R Skowronek can be reached at 571 272-9047. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Joseph Woitach/Primary Examiner, Art Unit 1687
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