DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Newly added amendments to claim 17 read, “clockable switch to enable or disable the inverters at least partially concurrently with the differential input pair”.
Not only is this amendment unclear as no detail is given as to what the differential input pair is doing while the switch is enabling or disabling the inverters, but there is no detail of this in the specification. Nowhere in the specification is it clearly taught that inverters are enabled or disabled concurrently, simultaneously, or the like, with the differential input pair.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102a(1) as being anticiapted by Mandal (US 2015/0043681).
Referring to Claim 1, Mandal teaches a sense amplifier latch (see paragraph 14 which shows a sense amplifier circuit and paragraph 25 which shows the latching function), comprising:
a first stage having a differential input pair and cross-coupled transistors coupled to the differential input pair (see differential inputs 204 and 206 in fig. 2A and the cross coupled transistors 214 and 216 where paragraph 19 shows the transistors 204 and 206 as a differential input pair), wherein the differential input pair uses transistors of a common polarity with those of the cross-coupled transistor pair (see paragraphs 19 and 21 which shows transistors 204, 206, 214, and 216 all as PMOS transistors and therefore, having a common polarity); and a second stage coupled to the first stage such that the first stage is to fold in to the second stage forming a cascode amplifier (see paragraph 25 which shows the sampler circuit with two stages and a folded cascode amplifier), wherein the second stage comprises cross-coupled inverters (see cross-coupled inverters 210 and 212 in fig. 2A) including a clockable switch to enable or disable the inverters (see paragraph 15 which shows clockable switch circuit 104 which is able to deactivate the tail switch sense amplifier circuit 106 where this circuit is shown in fig. 2A and includes both the cross-coupled inverters and differential pair meaning both elements are disabled).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 5, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mandal in view of van den Berg (US 2009/0284286).
Referring to Claim 17, Mandal teaches a system comprising:
a sampler 102 (fig. 1) including:
a first stage having a differential input pair and cross-coupled transistors coupled to the differential input pair (see differential inputs 204 and 206 in fig. 2A and the cross coupled transistors 214 and 216 where paragraph 19 shows the transistors 204 and 206 as a differential input pair); and a second stage coupled to the first stage such that the first stage is to fold in to the second stage forming a cascode amplifier (see paragraph 25 which shows the sampler circuit with two stages and a folded cascode amplifier), wherein the second stage comprises cross-coupled inverters (see cross-coupled inverters 210 and 212 in fig. 2A) that each include a clockable switch to enable or disable the inverters at least partially concurrently with the differential input pair (see paragraph 15 which shows clockable switch circuit 104 which is able to deactivate the tail switch sense amplifier circuit 106 where this circuit is shown in fig. 2A and includes both the cross-coupled inverters and differential pair meaning both elements are concurrently disabled).
Mandal does not teach a memory, a processor coupled to the memory, and an antenna communicatively coupled to the processor. Van den Berg teaches a memory, a processor coupled to the memory, and an antenna communicatively coupled to the processor, wherein the processor includes a receiver which comprises: an analog front-end (see paragraph 7 which shows the frequency synthesizer as part of all modern communications system which are known in the art to include an antenna, memory, processor, and an analog front end); a summing node coupled to an output of the analog front-end (see 608 of fig. 6); and a sampler coupled to the summing node (see 602 of fig. 6). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of van den Berg to the device of Mandal in order to better achieve a more desired sampling output for the device.
Referring to Claim 4, van den Berg also teaches a first device coupled in parallel to a transistor of the first inverter, and also coupled to a supply rail (see transistor 310 in parallel to inverter 302 in fig. 3 and paragraph 43 which shows the device coupled to a supply rail due to rail-to-rail voltages). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of van den Berg to the device of Mandal in order to better achieve a more desired sampling output for the device.
Referring to Claim 5, van den Berg also teaches a second device coupled in parallel to a transistor of the second inverter, and also coupled to the supply rail (see transistor 312 in parallel to inverter 304 in fig. 3 and paragraph 43 which shows the device coupled to a supply rail due to rail-to-rail voltages). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of van den Berg to the device of Mandal in order to better achieve a more desired sampling output for the device.
Claim(s) 8, 9, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mandal and van den Berg, and further in view of Putzeys et al. (US 2020/0389135).
Referring to Claims 8 and 20, the combination of Mandal and van den Berg does not teach a cross-talk cancellation circuitry coupled to the differential pair. Putzeys teaches a cross-talk cancellation circuitry coupled to the differential pair (see paragraph 25 which shows circuitry which eliminates cross talk between differential inputs). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Putzeys to the modified device of Mandal and van den Berg in order to reduce noise and interference in the amplifying circuit.
Referring to Claim 9, Putzeys also teaches a high-pass filter coupled to the cross-talk cancellation circuitry coupled to the differential pair (see paragraph 25 which shows the circuitry to eliminate cross talk including a high pass filter).
Claim(s) 6, 7, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mandal, van den Berg, and Putzeys, and further in view of Liu (US 2006/0186928).
Referring to Claim 6, the combination of Mandal, van den Berg, and Putzeys does not teach a first driver coupled to the transistor of the first inverter; and a second driver coupled to the transistor of the second inverter. Liu teaches a first driver coupled to the transistor of the first inverter; and a second driver coupled to the transistor of the second inverter (see driving voltages Vin and Vip applied to transistors N1 and N2). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Liu to the modified device of Mandal, van den Berg, and Putzeys in order to provide optimal calibrated outputs of the device elements.
Referring to Claim 7, the combination of Mandal, van den Berg, and Putzeys does not teach a first transistor coupled to the differential input pair and cross-coupled transistors, wherein the first transistor is controllable by a first clock; and a second transistor coupled to the differential input pair and a reference supply, and controllable by a second clock, wherein the second clock is an inverse of the first clock. Liu teaches a first transistor coupled to the differential input pair and cross-coupled transistors, wherein the first transistor is controllable by a first clock; and a second transistor coupled to the differential input pair and a reference supply, and controllable by a second clock, wherein the second clock is an inverse of the first clock (see claim 11 which shows a transistor with a gate coupled to a clock signal and another transistor with a gate coupled to an inverse clock signal). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Liu to the modified device of Mandal, van den Berg, and Putzeys in order to provide optimal calibrated outputs of the device elements.
Referring to Claim 10, Liu also teaches a voltage offset control circuitry coupled to the differential pair (see fig. 2 and paragraph 25 which shows circuity to adjust voltages when voltage offsets occur). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Liu to the modified device of Mandal, van den Berg, and Putzeys in order to provide optimal calibrated outputs of the device elements.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4-10, 17, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE YUN whose telephone number is (571)272-7860. The examiner can normally be reached 9am-5pm.
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/EUGENE YUN/Primary Examiner, Art Unit 2648