Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-16, and 18 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 07/06/2023. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/10/2023 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/12/2025, 07/12/2025, and 09/29/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16, and 18 are rejected 35 U.S.C. 103 as being unpatentable over Bshara et al. (US Pat No. 10162793 B1, hereinafter referred to as Bshara) in view of Hormuth et al. (USPGPUB No. 2013/0325998 A1, hereinafter referred to as Hormuth) and further in view of Jreji et al. (USPGPUB No. 2015/0331473 A1, hereinafter referred to as Jreji) and further in view of Breakstone et al. (US Pat No. 10255215 B2, hereinafter referred to as Breakstone) and further in view of Breakstone et al. (US Pat No. 9798636 B2, hereinafter referred to as Breakstone’636) supported by Non-Patent Literature “NVM Express Moves Into The Future”.
Referring to claim 1, Bshara discloses a device comprising {“host device 102” (see Fig. 3, Col 9, lines 50-52); or another such device “architecture 1200”, see Fig. 12, Col 24, lines 29-36}:
an interface {“service provider” subcomponent interface “communication connection 1224”, see Fig. 12, Col, lines}, the interface including a connection to a component {plurality of components “user devices 1204”, see Fig. 12, Col 26, lines 22-24}, the component external to the device {second connection(s) “network 1208”, see Fig. 12, Col 25, lines 18-20};
a circuit configured to {“hardware modules”, see Fig. 12, Col 27, lines 41-42}:
wherein the first mode includes a protocol used by the device {“either in real-time or in an asynchronous mode prior to any user interaction”, see Fig. 12, Col 27, lines 47-49} to communicate across the connection {“communication with each other over a communication [connection] channel 420”, see Fig. 4, Col 10, lines 7-9};
Bshara does not appear to explicitly disclose configure the device to use the second mode based at least in part on selection of the second mode by the circuit, wherein the first operation includes a protocol, and wherein the second mode includes a second protocol.
However, Hormuth discloses configure the device to use the second mode based {“multi-function PCIe modules 121 and 131” (see Fig. 1, [0026]).} at least in part on selection of the second mode by the circuit {“non-storage 314”, see Fig. 3, [0043].}, wherein the first mode includes a protocol {“P2P endpoint 122 can be identified as function 1”, [0026].}, and wherein the second mode includes a second protocol {“RRDMA endpoint 124”, see Fig. 1, [0079].}.
Bshara and Hormuth are analogous because they are from the same field of endeavor, managing peripheral devices.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Bshara and Hormuth before him or her, to modify Bshara’s “architecture 1200” (see Fig. 12) incorporating Hormuth’s “multi-function PCIe module 121” (see Fig. 1, [0023]).
The suggestion/motivation for doing so would have been to incorporate information handling systems including a variety of hardware and software resources that can be configured to process, store, and communicate information and can include one or more computer systems, graphics interface systems, data storage systems, and networking systems (Hormuth [0003], last 7 lines).
Therefore, it would have been obvious to combine Hormuth with Bshara to obtain the invention as specified in the instant claim(s).
However neither Bshara nor Hormuth does not appear to explicitly disclose circuitry via the configured to:
select a first mode based at least in part on a first signal from a component, the first signal received via the connector;
a second mode based at least in part on a second signal from the component, the second signal received via the connector;
configure the device to use the first mode based at least in part on selection of the first mode by the circuit;
configure the device to use the second mode based mode based at least in part on selection of the second mode by the circuit.
Furthermore, Jreji discloses circuitry via the configured to {“CPU 101 is coupled to service processor 102”, [0021], see Fig. 1}:
select a first mode {“ monitor the state [MODE] of an IHS”, [0019]} based at least in part on a first signal from a component {“ solid state hybrid drives (SSHD) combine the features of SSDs and HDDs”, [0018]}, the first signal received via the connector {signals via connector as claimed “via several interface and to an array of PCIe SSDs 105”, see Fig. 1, [0021]};
a second mode based {“determine the source of NVMe power management”, see Fig. 2 [0027]} at least in part on a second signal from the component {“ polling and/or receiving events about PCIe SSD 105 usage, see Fig. 2 [0028] }, the second signal received via the connector {“ metrics data received from other sources within an IHS”, see Fig. 2 [0028]};
configure the device to use the first mode {“ any change from PCIe/CPU/Memory usage data or statistics”, [0029]} based at least in part on selection of the first mode by the circuit {“whether there has been any change from an application profile monitoring from the ISM, or whether any adjustments are needed”, [0029]};
configure the device to use the second mode {“a mathematical calculation may be performed to assign weights to the various performance and metrics data received by service processor 102”, block 206 [0030] see Fig. 2} based mode based at least in part on selection of the second mode by the circuit {“the result may be mapped to a power control value [in the respective first or second mode] or limit either directly or via a look-up table”, [0028]}.
Bshara/Hormuth and Jreji are analogous because they are from the same field of endeavor, managing peripheral devices.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Bshara/Hormuth and Jreji before him or her, to modify Bshara/Hormuth’s device incorporating Jreji’s “managing power to NVMe devices 105” (see Fig. 2, [0028]).
The suggestion/motivation for doing so would have been to incorporate developed systems and methods for smartly managing the power provided to PCIe SSDs for achieving the bigger goal of optimizing an IHS' power consumption by dynamically regulating power to these devices depending upon input/output (I/O) workload (Jreji [0004]).
Therefore, it would have been obvious to combine Jreji with Bshara/Hormuth to obtain the invention as specified in the instant claim(s).
However neither one of the group consisting of Bshara, Hormuth, and Jreji appears to explicitly disclose wherein the circuit configured to configured the device to use the second mode based at least in part on selection of the first mode by the circuit, including enabling the first connection; including enabling the second connection, the second connection different from the first connection;
Furthermore, Breakstone discloses wherein the circuit configured to configured the device {the circuit “power controller 621” to configure the device “storage device 610” (see Fig. 6)} to use the second mode of operation based {a plurality of operation modes “storage drives incorporate low power modes, such as idle modes” (Col 20, lines 58-60} at least in part on selection of the first mode of operation by the circuit {first mode “usage statistics can be employed to selectively power down elements of a particular storage device [610]” (Col 20, lines 53-55, see Fig. 6)}, including enabling the first connection {first connection “include non-PCIe signaling, such as sideband interfaces 649 or other interfaces”, see Fig. 6, Col 8, lines 19-20 }; including enabling the second connection {“Auxiliary PCIe interface 660 can be used for cluster interconnect and can terminate at external connectors, such as mini-Serial Attached SCSI (SAS) connectors which are employed to carry [second connection] PCIe signaling over mini-SAS cabling.”, see Fig. 6, Col 8, lines 20-24}}, the second connection different from the first connection {first and second different connection(s) “Signaling for auxiliary PCIe interface 660 can be included in a same physical connector as PCIe interface 640 (such as a U.2 connector) or can be included in a separate connector than that of PCIe interface 640.”, see Fig. 6, Col 8, lines 13-16};
Bshara/Hormuth/Jreji and Breakstone are analogous because they are from the same field of endeavor, managing peripheral devices.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Bshara/Hormuth and Breakstone before him or her, to modify Bshara/Hormuth/Jreji’s device incorporating Jreji’s “managing power to NVMe devices 105” (see Fig. 2, [0028]).
The suggestion/motivation for doing so would have been to utilize and employ power holdup and power management features to ensure reliability and enhanced data handling during power interruptions in enhanced data storage devices herein also employ solid state memory devices, such as solid state drives, solid state M.2 form factor memory devices/drives, or other non-volatile type of data storage devices advantageously incorporated into a compact storage drive or expansion card that can interface with one or more host systems for handling of storage operations (Breakstone Col 2, line 54- Col 3, line 3).
Therefore, it would have been obvious to combine Breakstone with Bshara/Hormuth/Jreji to obtain the invention as specified in the instant claim(s).
However neither one of the group consisting of Bshara, Hormuth, Jreji, and Breakstone appears to explicitly disclose wherein the device is configured to modify a use of an Ethernet port of the device based at least in part on the selection of the first mode.
Furthermore, Breakstone’636 discloses wherein the device is configured to modify a use of an Ethernet port {“over Ethernet control plane links 1340-1344” stem from a respective Ethernet port, see Fig. 13, Col 41, lines 16-18} of the device based at least {modifying use “layer-2 (Ethernet) routing table entries pointing to the crashed node and generates new layer-2 (Ethernet) routing tables entries that point to the new owning peer as the destination for [PCIe devices] IOs that access the SSDs/LBAs contained on the transferred SSD”, see Fig. 13, Col 40, lines 56-60} in part on the selection of the first mode {“Power control module 531 can selectively enable/disable power [modes] for each power link.”, see Fig. 5, Col 15, lines 37-38}.
Bshara/Hormuth/Jreji/Breakstone and Breakstone’636 are analogous because they are from the same field of endeavor, managing peripheral devices.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Bshara/Hormuth and Breakstone before him or her, to modify Bshara/Hormuth/Jreji/Breakstone’s system incorporating Breakstone’636’s “operating system backend software”, Ethernet routing tables and respective Ethernet control plane links 1340-1344 (see Fig. 13).
The suggestion/motivation for doing so would have been to While software increase the levels of redundant paths that can be changed too in situations where a hardware path fails software can set up the next path of redundancy for another failure event by utilizing a table included in each processor that tells it which SSD it owns normally and which it supports when there is a failover situation (Breakstone’636 Col 22, lines 41-46).
Therefore, it would have been obvious to combine Breakstone’636 with Bshara/Hormuth/Jreji/Breakstone to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Hormuth discloses wherein the circuit is configured to determine the first mode from the signal via a pin on the connector {“low pin count bus”, see Fig. 2 [0033]}.
As per claim 3, the rejection of claim 1 is incorporated and Breakstone discloses wherein a first of the first connection includes a plurality of Peripheral Component Interconnect Express (PCIe) lanes {“configured to carry PCIe signaling of auxiliary PCIe interface 660.”, Col 8, lines 16-18} and or Serial Attached Small Computer System Interface (SCSI) (SAS) pins {“MiniSAS HD cables are employed that drive 12 Gb/s versus 6 Gb/s of standard SAS cables.”, see Fig. 6, Col 8, lines 23-27}.
As per claim 4, the rejection of claim 3 is incorporated and Hormuth discloses wherein, based at least in part on the first mode being an Non-Volatile Memory Express (NVMe) mode of operation {“NVME interface 232”, see Fig. 2 [0028]}, the device is configured to use two lanes of the PCIe lanes as both a data plane {“node 191 via a backplane”, see Fig. 1 [0024]} and a control plane for a host {“BMC that operates to provide platform management”, see Figs. 2-3, [0077]; “Ethernet interfaces”, see Fig. 3 [0042]}.
As per claim 5, the rejection of claim 3 is incorporated and Hormuth discloses wherein, based at least in part on the first mode being an Non-Volatile Memory Express over Fabric (NVMeoF) mode of operation {“NVME interface 232”, see Fig. 2 [0028]}, the second circuitry is configured to use two lanes of the PCIe lanes as a control plane for a host {“BMC that operates to provide platform management”, see Figs. 2-3, [0077]}, and to use a set of the SAS pins as an Ethernet port {“Ethernet interfaces”, see Fig. 3 [0042]} for a data plane for the host {“node 191 via a backplane”, see Fig. 1 [0024]}.
Referring to claims 6-9 are method claims reciting claim functionality corresponding to the device claims of claims 1-5, respectively, thereby rejected under the same rationale as claims 1-5 recited above.
Referring to claims 10-14 are system claims reciting claim functionality corresponding to the device claims of claims 1-5, respectively, thereby rejected under the same rationale as claims 1-5 recited above.
As per claim 15, the rejection of claim 1 is incorporated and Jreji discloses wherein the device is configured to communicate with the component using the protocol {“this feature provides a user with flexibility to choose to either manage the device power from CPU 101 or service processor 102 at any point in time”, [0027]}.
As per claim 16, the rejection of claim 6 is incorporated and Jreji discloses wherein the device is configured to communicate with the component using the first mode {“single port NVMe mode, a dual port NVMe mode, a single port NVMeoF mode, and a dual port NVMeoF mode”, [0029]}.
As per claim 18, the rejection of claim 10 is incorporated and Jreji discloses wherein the device is configured to communicate with the component using the first mode {“this feature provides a user with flexibility to choose to either manage the device power from CPU 101 or service processor 102 at any point in time”, [0027]}.
Response to Arguments
Applicant’s arguments, filed on 08/25/2025, have been considered however rendered moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references indicative of the current state of the art: US 11042496 B1, US 10013388 B1, US 10063073 B2, and US 10180889 B2.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.A.B./
Examiner
Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184