Office Action Predictor
Application No. 17/234,471

ULTRA THIN DIELECTRIC PRINTED CIRCUIT BOARDS WITH THIN LAMINATES AND METHOD OF MANUFACTURING THEREOF

Non-Final OA §103
Filed
Apr 19, 2021
Examiner
CARLEY, JEFFREY T.
Art Unit
3729
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Sanmina Corporation
OA Round
7 (Non-Final)
74%
Grant Probability
Favorable
7-8
OA Rounds
3y 4m
To Grant
49%
With Interview

Examiner Intelligence

74%
Career Allow Rate
576 granted / 784 resolved
Without
With
+-24.2%
Interview Lift
avg trend
3y 4m
Avg Prosecution
41 pending
825
Total Applications
career history

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
37.7%
-2.3% vs TC avg
§102
31.9%
-8.1% vs TC avg
§112
28.1%
-11.9% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/09/2025 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 7-12 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Dudnikov, in view of Scott et al. (US 20140209469 A1). Regarding claim 7, Dudnikov discloses an *ultra-thin dielectric **printed circuit board (PCB), comprising: a first conductive layer (106) comprising a first side (fig. 2: bottom, as viewed) and a second side (top) opposite the first side, the first conductive layer detachably coupled on the first side to a disposable base (208) by an adhesive layer (206, which can be “polymer”) between and in direct contact with the first side of the first conductive layer and the disposable base (fig. 2; pars. 0062 and 0064); a patterned second conductive layer (102) comprising a first side (bottom) and a second side (top) opposite the first side; a first ultra-thin dielectric layer (104) coupled to the second side of the first conductive layer and to the first side of the second conductive layer, where the first ultra-thin dielectric layer is positioned between and in direct contact with the second side of the first conductive layer and the first side of the second conductive layer across the entirety of second side of the first conductive layer and the entirety of the first side of the second conductive layer (fig. 2; par. 0062), and a portion of the first ultra-thin dielectric layer that is positioned between the second side of the first conductive layer and the first side of the second conductive layer is thinner (0.5 mils) than the first conductive layer (which can be 0.25 to 6 mils and is selected as being between 0.7 mils and 6 mils) between the first side and the second side of the first conductive layer and thinner than the second conductive layer (which can be 0.25 to 6 mils and is selected as being between 0.7 mils and 6 mils) between the first side and the second side of the second conductive layer (0.5 mils < 6 mils) (par. 0059); a dielectric filler (108/108’) filling the patterned second conductive layer (pars. 0057 and 0060). Dudnikov, however does not expressly disclose the adhesive layer facilitating [potential future] detachment of the disposable base by peeling the disposable base from the first conductive layer. *Note: regarding the term “ultra-thin” in the claims, there is not a currently recognized art standard or definition, or even an agreed upon size range for what is or is not considered to be ultra-thin. The instant disclosure does provide information as to what “may” be considered ultra-thin (please see: spec, pars. 0009 and 0020). Because the specification indicates that ultra-thin dielectric layers “may have a thickness of 50 micron or less” (emphasis added), this also means that ultra-thin layers “may” have a thickness of more than 50 microns. As a result of the applicants use of the hedging “may” language, the disclosure of the specification does not amount to a special definition. As such, a reasonable interpretation of the “ultra-thin dielectric layer” limitation, at least for claims 7-10 and 15, is any dielectric layer which is not disclosed as being “thick” or “very large” or something of the like which would indicate that the disclosed prior art dielectric layer is not thin. In this instance, the entire product of Dudnikov is disclosed explicitly as being “thin” and the layers which are defined in terms of thickness are disclosed as being one 0.5-5 mils, which is in the sub 50 micron range. **Note: The Applicant indicates in the preamble that the product is a printed circuit board (PCB), however nothing in the claim requires any structures that are explicitly required by a PCB. As such, the preamble is not found to have patentable weight, based upon the lack of a nexus of connection between the preamble and the body of the claim. In planning future amendments, the Applicant is cautioned that there is actually not a single instance in the original specification wherein a PCB itself is provided. Instead, the specification repeatedly discloses provision of a “printed circuit board structure” (emphasis added), which is significantly more broad than a PCB itself, and includes any structure used in or on a PCB, e.g. a capacitive stack. Scott teaches that it is well known to provide a similar PCB (pars. 0028-0029), comprising at least: a first conductive layer (nanowires), the first conductive layer detachably coupled on the first side to a disposable base (substrate) by an adhesive layer (polymer resin) between and in direct contact with the first side of the first conductive layer and the disposable base, the adhesive layer facilitating [potential future] detachment of the disposable base by peeling the disposable base from the first conductive layer (Abstract; figs. 1-10; pars. 0039, 0049-0052). Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to have modified the current invention of Dudnikov to incorporate the intended peeling capability of the adhesive polymer of Scott. POSITA would have realized that semi-additive techniques involving polymer peeling adhesives can be easily and readily employed to achieve the desired final product size, capability of being completed in situ, reusability of carrying substrate, thus predictably decreasing manufacturing time and cost. Moreover, there is no indication in the instant disclosure that any special adhesive layer was devised or that any surprising results were derived from simply using the old PCB with a polymer adhesive layer of Dudnikov with the well-known peelable polymer adhesive layer of Scott. This combination would have been easily performed with knowledge of the commonly understood advantages and with reasonable expectations of success. Regarding claim 8, Dudnikov in view of Scott teaches the PCB of claim 7 as detailed above, and Dudnikov further discloses at least one additional conductive layer (202) and at least one additional ultra-thin dielectric layer (204) coupled to the second conductive layer (fig. 2; par. 0062). Regarding claim #, Dudnikov in view of Scott teaches the PCB of claim 8 as detailed above, and Dudnikov further discloses that at least one ultra-thin dielectric layer is thinner than at least one adjacent conductive layer (par. 0028). Regarding claim 10, Dudnikov in view of Scott teaches the PCB of claim 8 as detailed above, and Dudnikov further discloses that each ultra-thin dielectric layer is thinner than at least one adjacent conductive layer (pars. 0028 and 0059). Regarding claim 11, Dudnikov in view of Scott teaches the PCB of claim 7 as detailed above, and Dudnikov further discloses that the ultra-thin dielectric layer has a thickness of 50 micron or less while the first and second conductive layers are each more than 50 micron thick (0.5 mils = 12.7 micron < 50 micron; 6 mils = 152.4 micron > 50 micron) (pars. 0028 and 0059). Regarding claim 12, Dudnikov in view of Scott teaches the PCB of claim 7 as detailed above, and Dudnikov further discloses that the ultra-thin dielectric layer has thickness of 20 micron or less while the first and second conductive layers are each more than 20 micron thick (0.5 mils = 12.7 micron < 20 micron; 6 mils = 152.4 micron > 20 micron) (pars. 0028 and 0059). Regarding claim 14, Dudnikov in view of Scott teaches the PCB of claim 7 as detailed above, and Dudnikov further discloses that the first and second conductive layers each have a thickness of 3 micron, 5 micron, 9 micron, 12 micron, 0.5 ounce copper, 1 ounce copper, or 2 ounce copper (0.5 oz copper is 0.7 mils thick, which is within the disclosed range of the conductive layer in Dudnikov and remains thicker than the dielectric layer, which is 0.5 mils thick) (par. 0059). Regarding claim 15, Dudnikov in view of Scott teaches the PCB of claim 7 as detailed above, and Dudnikov further discloses that the first conductive layer is patterned, and the first conductive layer, the first ultra-thin dielectric layer, and the second conductive layer comprise at least a portion of a first subassembly structure (100), and further comprising: a patterned outer conductive layer (202) coupled to the first subassembly structure, opposite the first conductive layer, to form a first subassembly core (200) (fig. 2; par. 0062). Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Dudnikov, in view of Scott, further in view of Utsumi et al. (US 2003/0213615 A1). Regarding claim 13, Dudnikov in view of Scott teaches all of the elements of the current invention as detailed above with respect to claim 7. Dudnikov further discloses that the ultra-thin dielectric layer has thickness of very close to 10 micron or less (0.5 mils = 12.7 micron), and the first and second conductive layers are each more than 10 microns thick (6 mils = 152.4 micron > 10 micron) (pars. 0028 and 0059). The modified Dudnikov, however, does not explicitly disclose that the ultra-thin dielectric layer has thickness of 10 micron or less. Utsumi teaches that it is well known to provide a closely related ultra-thin dielectric printed circuit board (PCB) (21) (Title; Abstract; fig. 6), comprising: a first conductive layer (103) removably coupled on a first side (fig. 6: bottom, as viewed) to a disposable base (104) (fig. 6; par. 0071); a patterned second conductive layer (106); a first *ultra-thin (6 µm) dielectric layer (22, including 23 and/or 24) coupled to a second side (top, as viewed) of the first conductive layer and to a first side (bottom, as viewed) of the second conductive layer, where the first ultra-thin dielectric layer is positioned between and in direct contact with the second side of the first conductive layer and the first side of the second conductive layer across the entirety of second side of the first conductive layer and first side of the second conductive layer (fig. 6; pars. 0071 and 0074: “an adherent insulator 24 [is] present only between dielectric film 23 and first conductor formation substrate 104”; “wiring board 2 has a structure corresponding to the structure of wiring board 1 of the first embodiment, provided that a dielectric 22 lacks second adherent insulator 4b”), and the first ultra-thin dielectric layer is thinner (6 µm) than the first conductive layer (18 µm) and the second conductive layer (18 µm) (par. 0074); a dielectric filler (107, including epoxy glass, 105) filling the patterned second conductive layer (fig. 6; pars. 0046 and 0071). Utsumi further teaches that the ultra-thin dielectric layer has thickness of 10 micron or less (6 µm) while the first and second conductive layers are each more than 10 micron thick (18 µm) (pars. 0047-0049). Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to have further modified the current invention of Dudnikov to incorporate the preferred dielectric and conductor thicknesses of Utsumi, since it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In the instant application there is no indication of surprising results from using the well-known product of Dudnikov with the old preferred dimensions of Utsumi. PHOSITA would have realized that this combination could readily be made without any experimentation, in order to simply meet the design requirements and conductivity/impedance specifications of the intended product. Allowable Subject Matter Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not reasonably teach all of the limitations of claim 7 in conjunction with the requirements of a third conductive layer comprising a first side and a second side opposite the first side, the third conductive layer detachably coupled on the first side to the disposable base on a side of the disposable base opposite from the first conductive layer, the third conductive layer coupled to the disposable base by another adhesive layer between and in direct contact with the first side of the third conductive layer and the disposable base, the other adhesive layer facilitating detachment of the disposable base by peeling the disposable base from the third conductive layer; a patterned fourth conductive layer comprising a first side and a second side opposite the first side; a second ultra-thin dielectric layer coupled to the second side of the third conductive layer and to the first side of the fourth conductive layer, where the second ultra-thin dielectric layer is positioned between and in direct contact with the second side of the third conductive layer and the first side of the fourth conductive layer across the entirety of second side of the third conductive layer and the entirety of the first side of the fourth conductive layer Response to Arguments Applicant's arguments filed 12/09/2025 have been fully considered but they are not persuasive. The Applicant has asserted that: “The Office Action argues that the second conductive foil 106 and the fourth conductive foil 208 may be peeled from each other after being coupled, but Applicant submits that there is no support for the Examiner's assertion to such aspects. Although Applicant recognizes that a conductive layer may be removed by grinding, ablation, and etching, such removal is not a detachment of the layer from another layer, nor does the thin second dielectric layer 206 facilitate detachment of the second conductive foil 106 by peeling the fourth conductive foil 208 from the second conductive foil 106”. Respectfully, this argument is not persuasive for numerous reasons. Respectfully, please note that the secondary reference now cited to Scott, explicitly discloses a removable conductive substrate connected to a conductive layer by way of a peelable polymer adhesive. The previously and currently cited primary reference to Dudnikov, by the Applicant’s own admission, also discloses a conductive substrate connected to a conductive layer by way of an adhesive. The adhesive layer of Dudnikov is expressly disclosed as being a polymer, exactly as in Scott. As such, these structures are patentably indistinct and the adhesive layer is identical. In Scott it is expressly disclosed that the adhesive polymer layer is peelable and therefore it is quite obvious that the intended capability of the adhesive in the claim is also met by Dudnikov in view of the teaching of Scott. The Applicant is respectfully reminded that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In this instance, the claims do not differentiate the materials of the claimed structures, and Scott serves to demonstrate that the adhesive polymer layer of Dudnikov was well known in its ability to be peeled from a conductive substrate, thus demonstrating that the prior art is in fact, capable of being peeled in the same manner as the intended capability of the claim. Further, the applicant is advised that it has been held that the recitation that an element is “capable of” performing a function is not a positive limitation, but only requires the ability to so perform. It does not constitute a limitation in any patentable sense. The ability to so perform has clearly been demonstrated by the prior art and especially the teaching of Scott. Further still, the applicant is respectfully advised that, while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In this instance, the structure and the function have been demonstrated in the prior art Finally, the applicant is respectfully advised that products of identical structure or chemical composition (polymer adhesive of both Dudnikov and Scott), or produced by identical or substantially identical processes, cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims (e.g. intended capability of being peeled) are necessarily present. When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not. According to all of the above, and especially in light of the newly applied prior art rejections, the Applicant’s arguments are not found to be compelling and the currently applied prior art rejections have demonstrated that the prior art teaches each and every claimed limitation. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the concurrently mailed PTO-892, as all of those cited references are considered to be pertinent to the claimed invention. For example, Oh et al. (US 2012/0038053 A1) is held to be of particular relevance to the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeffrey T Carley whose telephone number is (571)270-5609. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sunil Singh can be reached at (571)272-3460. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEFFREY T CARLEY/Primary Examiner, Art Unit 3729
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Prosecution Timeline

Apr 19, 2021
Application Filed
Mar 20, 2023
Non-Final Rejection — §103
Aug 22, 2023
Response Filed
Oct 23, 2023
Final Rejection — §103
Jan 29, 2024
Request for Continued Examination
Feb 04, 2024
Response after Non-Final Action
Mar 21, 2024
Non-Final Rejection — §103
Jul 24, 2024
Response Filed
Sep 17, 2024
Final Rejection — §103
Nov 22, 2024
Response after Non-Final Action
Jan 17, 2025
Request for Continued Examination
Jan 21, 2025
Response after Non-Final Action
Apr 07, 2025
Non-Final Rejection — §103
Jul 10, 2025
Response Filed
Sep 09, 2025
Final Rejection — §103
Dec 09, 2025
Request for Continued Examination
Dec 19, 2025
Response after Non-Final Action
Jan 06, 2026
Non-Final Rejection — §103
Apr 01, 2026
Response Filed

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Prosecution Projections

7-8
Expected OA Rounds
74%
Grant Probability
49%
With Interview (-24.2%)
3y 4m
Median Time to Grant
High
PTA Risk
Based on 784 resolved cases by this examiner