DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is responsive to amendment filed on 05/04/2026. Claims 16-17, and 47-56, and 58-61 are pending. The amendment have overcome the claims objection as set forth in previous office action.
Response to Arguments
In response to Applicant’s argument regarding rejection under 35 U.S.C. 102 on page 8, “Applicant proposes that the Examiner's interpretation of "coupled" is overly broad and inconsistent with the definition of "coupled" as defined in paragraph [0035] of the specification. For two given elements to be "coupled," paragraph [0035] requires that a functional relationship exists between the coupled elements and that any intervening components must not substantially alter the functional relationship between the coupled elements.”
Examiner respectfully disagrees because paragraph [0035] does not provide an explicitly definition of “couple” since [0035] uses the term “may”, such language indicates a possibility or a probability, which fails to provide an explicit definition for the term “couple” to be carried into a claim. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims unless the specification explicit defines the meaning of a term.
Applicant further asserted on page 8 regarding the mapping of AN NMOS drain and AN PMOS drain is coupled through the B PMOS and BN NMOS in Mittal’s circuit 304 and this gate and page 9, “This gate-dependent connection is fundamentally incompatible with the "coupled" relationship defined in paragraph [0035] of the specification. Under [0035], intervening components must not "substantially alter the functional relationship" between coupled elements. In Mittal, the B and BN transistors do precisely that: they interrupt and conditionally control the signal path between the AN NMOS and AN PMOS drains. When B or BN are in non-conducting states, the drains are not connected at all. When they are in conducting states, the path is mediated entirely by the B/BN transistor stack logic that controls whether the signal passes. This conditional gating fundamentally alters the functional relationship that is required by [0035].”
Examiner respectfully disagrees because as explained above, the description of the term “coupled” in [0035] fails to provide an explicit definition for the term “coupled” since it uses the term “may” and provide examples. Accordingly, applicant relies on limitations that are not recited in the rejected claim(s) (i.e., intervening components must not “substantially alter the functional relationship” between coupled elements). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant further asserted on page 9, “An additional and dispositive consideration is that the Examiner's interpretation would render Mittal's circuit functionally inoperable as an adder. In an adder circuit, the B and BN signals are primary input signals that are expected to be applied to the circuit at specific times to perform the addition function. If, as the Examiner proposes, the B and BN transistors gate and conditionally control the internal connection between the AN NMOS and AN PMOS drains, then the connectivity of these internal nodes would be dependent on the B and BN input signals. This creates an unintended functional dependency where changes in primary input B signal states would interrupt or alter the internal signal coupling that is intended to be unconditional. Such conditional gating of internal node connectivity would corrupt the circuit's ability to function correctly as an adder, introducing spurious signal dependencies that are not contemplated by the circuit design. The specification at paragraph [0016] explicitly describes the invention's advantage as reusing "internally generated logic signals" to generate both sum and carry-out outputs. The Examiner's reading of Mittal would destroy this intended functionality by making internal node connectivity contingent on primary input control signals.”
Examiner respectfully disagrees because first, the claims 47-49 merely recite a circuit that having components and do not recite any limitation related to an adder or performing addition. Thus, again applicant’s argument is relying on limitation that is not recited in the rejected claims. Second, the circuit in figure 3 of Mittal is an implementation of an adder (see [0021]). Thus, it is unclear how the implementation of Mittal figure 3 would be inoperable as an adder or corrupt the circuit’s ability to function correctly as an adder as Applicant asserted above. Furthermore, applicant’s asserted of [0016] for the invention’s advantage as reusing “internally generated logic signals” to generate both sum and carry outputs, where [0016] describes “the full adder reuses internally generated logic signal, e.g., b(XNOR)ci and b(XOR)ci, to generate both the sum signal (s) and the carry-out signal (co)”, as figure 3 of Mittal also illustrates the internally generated logic signals in circuit 304 [i.e., A(XOR)B and A(XNOR)B] is being reuse to generate both sum and carry out signal in circuit 306 and 308 respectively. Moreover, such recitation of [0016] is not recited in the claim. Applicant is reminded that although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claim Interpretation
Examiner interprets the phrase “coupled to” as recited in the claims as connected directly or indirectly through intervene components.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 47-56 and 59-61 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mittal et al - US 20200144245 (hereinafter Mittal).
Regarding claim 47, Mittal teaches a circuit (figure 3 illustrates a circuit 300) comprising:
a first inverter having an input and an output (figure 3 circuit 300 comprises circuit 302 having an inverter for A to AN [i.e., a first inverter having an input and an output]);
a first pass gate having a first input, a second input, a third input and an output (figure 3 circuit 304 comprises a transmission gate [i.e., a first pass gate] having AN input [i.e., a first input], B input, BN input and an output) wherein the output of the first inverter is coupled to the first input of the first pass gate (figure 3 circuit 304 AN [i.e., the output of the first inverter] coupled to the first input AN of the transmission gate);
a first P-type Metal Oxide Semiconductor (PMOS) transistor having a gate, source and drain (figure 3 circuit 304 includes PMOS and NMOS stack having 4 transistors connected in series, wherein the top PMOS [i.e., a first PMOS transistor] having gate, source and drain, wherein AN is input as gate, hereinafter as AN PMOS) wherein the drain of the first PMOS transistor is coupled to the output of the first pass gate (figure 3 circuit 304 AN PMOS having drain coupled to the output of the transmission gate) and the gate of the first PMOS transistor is coupled to the output of the first inverter (figure 3 circuit 304 AN PMOS having gate coupled to AN [i.e., the output of the first inverter]);
a first N-type Metal Oxide Semiconductor (NMOS) transistor having a gate, source and drain (figure 3 circuit 304 illustrates the bottom NMOS [i.e., first NMOS transistor] of PMOS and NMOS stack, wherein AN input as gate, hereinafter AN NMOS) wherein the drain of the first NMOS transistor is coupled to the drain of the first PMOS transistor and to the output of the first pass gate (figure 3 circuit 304 illustrates drain of AN NMOS and drain of AN PMOS are coupled via B PMOS and BN NMOS transistors as illustrated in the PMOS and NMOS stack and also coupled to the output of the transmission gate), and the gate of the first NMOS transistor is coupled to the output of the first inverter (figure 3 circuit 304 the gate of AN NMOS is coupled to AN [i.e., the output of the first inverter]);
a second inverter having an input and an output (figure 3 circuit 304 inverter that generate AXNORB [i.e., a second inverter] having an input and an output) wherein the input of the second inverter is coupled to the drain of the first PMOS transistor, to the drain of the first NMOS transistor and to the output of the first pass gate (figure 3 circuit 304 input of the AXNORB inverter is coupled to the drain of AN PMOS [i.e., drain of the first PMOS], drain of AN NMOS [i.e., drain of the first NMOS] and output of the transmission gate [i.e., output of the first pass gate]);
a second NMOS transistor having a gate, drain and source (figure circuit 304 illustrates BN NMOS [i.e., a second NMOS transistor] of the PMOS and NMOS stack) wherein the drain of the second NMOS transistor is coupled to the source of the first NMOS transistor (figure 3 circuit 304 drain of BN NMOS is coupled to the source of AN NMOS of the PMOS and NMOS stack [i.e., drain of the first NMOS]);
a second PMOS transistor having a gate, source and drain (figure circuit 304 illustrates B PMOS [i.e., a second PMOS transistor] of the PMOS and NMOS stack) wherein the drain of the second PMOS transistor is coupled to the source of the first PMOS transistor (figure 3 circuit 304 drain of B PMOS is coupled to source of AN PMOS [i.e., the first PMOS]); and
a third PMOS transistor having a gate, source and drain (figure 3 circuit 304 the top PMOS of the transmission gate, wherein the top PMOS receives BN for gate input, such top PMOS corresponds to a third PMOS) wherein the drain of the third PMOS transistor is coupled to the drain of the second NMOS transistor and to the source of the first NMOS transistor (figure 3 circuit 304 the drain of top PMOS of the transmission gate coupled to drain of BN NMOS [i.e., the second NMOS] and the source of AN NMOS [i.e., the first NMOS]).
Regarding claim 48, Mittal teaches the circuit of claim 47 further comprising;
a second pass gate having a first input, a second input, a third input and an output (figure 3 circuit 308 top transmission gate [i.e., a second pass gate] having AXORB, AXNORB, and BN as first, second, and third inputs, respectively, and an output) wherein the first input of the second pass gate is coupled to the input of the second inverter, to the drain of the first PMOS transistor and to the drain of the first NMOS transistor (figure 3 circuit 308 the AXORB input of the top transmission gate is coupled to AXORB [i.e., input of the second inverter], to the drain of AN PMOS and to the drain of AN NMOS of the PMOS and NMOS stack as illustrated in circuit 304);
a third pass gate having a first input, a second input, a third input and an output (figure 3 circuit 308 bottom transmission gate [i.e., a third pass gate] having AXNORB, AXORB, and CIN as input respectively, and an output) wherein the first input of the third pass gate is coupled to the output of the second inverter (figure 3 circuit 308 AXNORB input of the bottom transmission is coupled to AXNORB [i.e., the output of the second inverter]); and
a third inverter having an input and an output wherein the input of the third inverter is coupled to the output of the second pass gate and to the output of the third pass gate (figure 3 circuit 308, inverter that generates CO [i.e., a third inverter] having input coupled to the top and bottom transmission gates).
Regarding claim 49, Mittal teaches the circuit of claim 48 further comprising;
a fourth inverter having an input and an output (figure 3 circuit 302 illustrates a ci inverter that converts to CIN [i.e., a fourth inverter having an input and an output]);
a fourth pass gate having a first input, a second input, a third input and an output (figure 3 circuit 306 illustrates a transmission gate having CIN, AXORB, AXNORB as 3 inputs and an output) wherein the first input of the fourth pass gate is coupled to the output of the fourth inverter (figure 3 circuit 306 CIN input of the transmission gate [i.e., the first input of the fourth pass gate] is coupled to CIN [i.e., output of the fourth inverter]), the second input of the fourth pass gate is coupled to the drain of the first PMOS transistor (figure 3 circuit 306 AXORB input of the transmission gate [i.e., the second input of the fourth pass gate] is coupled to drain of AN PMOS of the PMOS and NMOS stack in circuit 304 [i.e., the first PMOS transistor] via the AXORB signal), the third input of the fourth pass gate is coupled to the output of the second inverter (figure 3 circuit 306 AXNORB input of the transmission gate [i.e., the third input of the fourth pass gate] is coupled to AXNORB, wherein AXNORB as illustrated in circuit 304 is output of the inverter [i.e., output of the second inverter]);
a fifth pass gate having a first input, a second input, a third input and an output (figure 3 circuit 306 illustrates PMOS and NMOS stack in series having at least 3 inputs and an output, wherein transistor acts like a switch that allows signal to pass depends on the input of the gate. Thus, such PMOS AND NMOS stack in series corresponds to a fifth pass gate) wherein the first input of the fifth pass gate is coupled to the output of the first inverter (figure 3 circuit 306 the PMOS and NMOS stack includes an NMOS having an AXORB input [i.e., the first input of the fifth pass gate] coupled to AXORB, which is also coupled to AN [i.e., the output of the first inverter] as illustrated in figure 3 circuit 304), second input of the fifth pass gate is coupled to the output of the second inverter (figure 3 circuit 306 the PMOS and NMOS stack includes a PMOS having an AXNORB input [i.e., the second input of the fifth pass gate] is coupled to AXNORB [i.e., output of the second inverter]) and the third input of the fifth pass gate is coupled to the drain of the first PMOS transistor (figure 3 circuit 306 the PMOS and NMOS stack includes an NMOS having CIN input [i.e., the third input of the fifth pass gate] is coupled to the AXORB, which is coupled to the drain of the AN PMOS [i.e., the first PMOS transistor] as illustrated in circuit 304); and
a fifth inverter having an input and an output wherein the input of the fifth inverter is coupled to the output of the fourth pass gate and to the output of the fifth pass gate (figure 3 circuit 306 the inverter that generate SUM [i.e., a fifth inverter having an input and an output], wherein the input of SUM inverter is coupled to output of transmission gate [i.e., output of fourth pass gate] and the output of PMOS and NMOS stack [i.e., output of the fifth pass gate]).
Claim 50 recites an apparatus having similar limitation as the apparatus of claims 47-49. Thus, it is rejected for the same reasons. Furthermore, Mittal also teaches an adder (figure 3 [0021] describes a full adder circuit)
Regarding claim 51, Mittal teaches the adder of claim 50, wherein the first inverter comprises a PMOS transistor having a gate, drain and a source, and an NMOS transistor having a gate, drain and a source, wherein the gates of the NMOS and PMOS transistors are coupled the input of the first inverter, and drains of the NMOS and PMOS transistors are coupled the output of the first inverter (figure 3 circuit 302 illustrates AN inverter that invert A to AN having PMOS AND NMOS, wherein the gates of NMOS AND PMOS transistors are coupled to the input and drains are coupled to the output of the AN inverter).
Regarding claim 52, Mittal teaches the adder of claim 50, wherein the second inverter comprises a PMOS transistor having a gate, drain and a source, and an NMOS transistor having a gate, drain and a source, wherein the gates of the NMOS and PMOS transistors are coupled the input of the second inverter, and drains of the NMOS and PMOS transistors are coupled the output of the second inverter (figure 3 circuit 304 illustrates inverter that generates AXNORB having PMOS AND NMOS, wherein the gates of NMOS AND PMOS transistors are coupled to the input and drains are coupled to the output of the AXNORB inverter).
Regarding claim 53, Mittal teaches the adder of claim 50, wherein the third inverter comprises a PMOS transistor having a gate, drain and a source, and an NMOS transistor having a gate, drain and a source, wherein the gates of the NMOS and PMOS transistors are coupled the input of the third inverter, and drains of the NMOS and PMOS transistors are coupled the output of the third inverter (figure 3 circuit 308 illustrates inverter that generates CO having PMOS AND NMOS, wherein the gates of NMOS AND PMOS transistors are coupled to the input and drains are coupled to the output of the CO inverter).
Regarding claim 54, Mittal teaches the adder of claim 50, wherein the fourth inverter comprises a PMOS transistor having a gate, drain and a source, and an NMOS transistor having a gate, drain and a source, wherein the gates of the NMOS and PMOS transistors are coupled the input of the fourth inverter, and drains of the NMOS and PMOS transistors are coupled the output of the fourth inverter (figure 3 circuit 302 illustrates inverter that generates CIN having PMOS AND NMOS, wherein the gates of NMOS AND PMOS transistors are coupled to the input and drains are coupled to the output of the CIN inverter).
Regarding claim 55, Mittal teaches the adder of claim 50, wherein the fifth inverter comprises a PMOS transistor having a gate, drain and a source, and an NMOS transistor having a gate, drain and a source, wherein the gates of the NMOS and PMOS transistors are coupled the input of the fifth inverter, and drains of the NMOS and PMOS transistors are coupled the output of the fifth inverter (figure 3 circuit 306 illustrates inverter that generates SUM having PMOS AND NMOS, wherein the gates of NMOS AND PMOS transistors are coupled to the input and drains are coupled to the output of the SUM inverter).
Regarding claim 56, Mittal teaches the adder of claim 50, wherein the first pass gate comprises a PMOS transistor having a gate, drain and a source, and an NMOS transistor having a gate, drain and a source, wherein the drains of the NMOS and PMOS transistors are coupled to each other, and sources of the NMOS and PMOS transistors are coupled to each other (figure 3 circuit 304 illustrates transmission gate having input AN, B, and BN [i.e., the first pass gate] having a PMOS transistor and a NMOS transistor, wherein the drains are coupled to each other and the sources are coupled to each other).
Regarding claim 58, Mittal teaches the adder of claim 50, wherein the second pass gate comprises a PMOS transistor having a gate, drain and a source, and an NMOS transistor having a gate, drain and a source, wherein the drains of the NMOS and PMOS transistors are coupled to each other, and sources of the NMOS and PMOS transistors are coupled to each other (figure 3 circuit 308 illustrates top transmission gate having input BN, AXORB, AXNORB [i.e., the second pass gate] having a PMOS transistor and a NMOS transistor, wherein the drains are coupled to each other and the sources are coupled to each other).
Regarding claim 59, Mittal teaches the adder of claim 50, wherein the third pass gate comprises a PMOS transistor having a gate, drain and a source, and an NMOS transistor having a gate, drain and a source, wherein the drains of the NMOS and PMOS transistors are coupled to each other, and sources of the NMOS and PMOS transistors are coupled to each other (figure 3 circuit 308 illustrates bottom transmission gate having input CIN, AXORB, AXNORB [i.e., the third pass gate] having a PMOS transistor and a NMOS transistor, wherein the drains are coupled to each other and the sources are coupled to each other).
Regarding claim 60, Mittal teaches the adder of claim 50, wherein the fourth pass gate comprises a PMOS transistor having a gate, drain and a source, and an NMOS transistor having a gate, drain and a source, wherein the drains of the NMOS and PMOS transistors are coupled to each other, and sources of the NMOS and PMOS transistors are coupled to each other (figure 3 circuit 306 illustrates a transmission gate having input CIN, AXORB, AXNORB [i.e., the fourth pass gate] having a PMOS transistor and a NMOS transistor, wherein the drains are coupled to each other and the sources are coupled to each other.
Regarding claim 61, Mittal teaches the adder of claim 50, wherein the fifth pass gate comprises a PMOS transistor having a gate, drain and a source, and an NMOS transistor having a gate, drain and a source, wherein the drains of the NMOS and PMOS transistors are coupled to each other, and sources of the NMOS and PMOS transistors are coupled to each other (figure 3 circuit 308 illustrates a PMOS and NMOS stack [i.e., the fifth pass gate] having an AXNORB PMOS and an AXORB NMOS transistor, wherein the drains of the PMOS and NMOS coupled to each other and the sources of the PMOS and NMOS are coupled to each other).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUY DUONG whose telephone number is (571)272-2764. The examiner can normally be reached Mon-Friday 7:30-5:30.
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/HUY DUONG/Examiner, Art Unit 2183 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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