DETAILED ACTIONS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/16/2025 has been entered.
Response to Amendment
The amendment filed 12/16/2025 has been entered. Claims 3, 5, and 11 are cancelled. Claims 1-2, 4, 6-10 and 12-23 remain pending in the application.
Response to Arguments
Applicant’s arguments with respect to claims 1, 13, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 8, 13-14, 16, 18, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schnebly et al., (US 2009/0147861 A1), hereinafter referred to as Schnebly.
Claim 1
Schnebly disclose a circuit (Schnebly, [0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”), comprising:
a memory (Schnebly, Fig. 2, memory 270); and
a processor (Schnebly, Fig. 2, processor 220) coupled to the memory (Schnebly, Fig. 2, memory 270) and configured to:
receive a data stream comprising a video that comprises multiple frames (Schnebly, [0008], “acquiring a sequence of video frames”);
compare data values (Schnebly, Fig. 4, [0034], “At operation 408, the extracted code from operation 404 and the code generated in operation 406 are compared.”, [0030], “The code may be a single value or a vector of values.”) representing a single image pixel at a specified location (Schnebly, [0007], “code is embedded into one or more pixels of a video frame with each subsequent frame of the video containing the next value in the code sequence. These codes can be embedded in place of the color codes for one or more pixels of each frame”, [0020], “The first pixel 110, and optionally the last pixel 120, may be used when embedding a frame freeze detection code according to the embodiments described herein”, [0031], “The code may be inserted into a single pixel, or multiple pixels of the video frame 105”, Fig. 4, step 404 “extract code value from frame”, the same code is extracted from the image which now represents that pixel) in a first frame of the frames (Schnebly, [0008], “acquiring a sequence of video frames”, [0007], “codes can be embedded in place of the color codes for one or more pixels of each frame”) to a single image pixel stored in the memory (Schnebly, Fig. 4, step 406 “generate next code value”, [0034], “The routine 400 continues from operation 404 to operation 406, where the image verification system 252 generates the next expected frame freeze code value to be compared to the frame freeze code value embedded within the received frame”, [0030], “From operation 302, the routine 300 continues to operation 304, where the image encoding system 212 generates the next frame freeze code value. The frame freeze code generator may be a simple counter, such that the code embedded into one frame 105 is simply one value greater than the code embedded into the previous frame 105”, all the frames are stored in memory therefore the codes that are generated are also stored in memory);
determine that the data stream (Schnebly, [0008], “acquiring a sequence of video frames”) includes incorrect data responsive to the data values representing the single image pixel at the specified location in the first frame differing from the single image pixel stored in the memory (Schnebly, Fig.4, step 410 and 412, if the codes or data values do not match, a fault is generated, [0034], “If the extracted code does not match the expected code, then it can be concluded that there is some type of system fault”); and
determine that the data stream includes correct data responsive to the data values representing the single image pixel at the specified location in the first frame matching the single image pixel stored in the memory (Schnebly, Fig.4, step 410 and 414, if the codes or data values do match, a fault is not generated, [0034], “If the extracted code matches the expected code, then it is reasonable to conclude that the video stream is not frozen or locked-up”).
Claim 2
Schnebly discloses the circuit of claim 1 (Schnebly, [0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”), wherein the processor (Schnebly, Fig. 2, processor 220) is further configured to provide a signal responsive (Schnebly, [0035], “If there is a fault concluded at operation 410, the routine 400 proceeds to operation 412 where a fault condition is generated and presented to the operator and the operation 400 ends”) to determining that the data value representing the image pixel at the specified location in the first frame differs from the data value representing the image pixel stored in the memory (Schnebly, Fig.4, step 410 and 412, if the codes or data values do not match, a fault is generated, [0034], “If the extracted code does not match the expected code, then it can be concluded that there is some type of system fault”).
Claim 4
Schnebly discloses the circuit of claim 2 (Schnebly, [0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”), wherein the signal (Schnebly, [0035], “If there is a fault concluded at operation 410, the routine 400 proceeds to operation 412 where a fault condition is generated and presented to the operator and the operation 400 ends”) comprises generating a visual output indicating the data stream includes incorrect data (Schnebly, [0008], “A fault indication is presented when the comparison does not match, [0028], “a fault indication may be presented to the operator using the video display 100, a lamp, LED, siren, buzzer, or other indicator of system fault.”).
Claim 8
Schnebly discloses the circuit of claim 1 (Schnebly, [0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”), further comprising: an image generator configured to generate and output the data stream (Schnebly, [0022], “frame freeze detection system 200 includes a camera 210, image encoding system 212, image verification system 252, and a video display 100”, [0023], “It should be appreciated that the image encoding system 212 may be a part of the camera 210, or may be located within a computer system that is directly, or remotely, connected to the camera 210”); and a receiver configured to receive and decode the data stream to display the video (Schnebly, [0026], “The image verification system 252 receives the encoded video from the image encoding system 212 and utilizes the embedded codes to verify video image continuity and detect frame freeze when it occurs. The image verification system 252 may include a display processor 260, memory 270, and storage 280., [0035], “Optionally, the coded pixels may be removed prior to displaying the frame”).
Claim 13
Schnebly discloses a system (Schnebly, Fig. 2), comprising:
a memory (Schnebly, Fig. 2, memory 270);
first circuitry (Schnebly, Fig. 2, camera 210) configured to generate at least two video streams each comprising multiple frames (Schnebly, [0022], “The camera 210 may be any kind of conventional camera capable of capturing and transmitting video data that includes sequential video frames 105. Examples include but are not limited to a digital charge coupled device (CCD) based camera, an infrared camera, a night vision camera, or any other type of image acquiring device. The camera 210 may have switches or other configuration setting mechanisms for configuring or manipulating aspects of the embodiments described herein. For example, the camera 210 may have a switch to turn on (and off) the code embedding mechanism. The camera 210 may have another switch or configuration setting to select the pixel(s) of each frame (such as the upper left-hand pixel) where the code values are to be embedded.”, the camera is allowed to capture multiple video streams, Fig. 3 shows processing both current frame and next frame);
encoder circuitry (Schnebly, Fig. 2, image encoding system 212) coupled to the first circuitry (Schnebly, Fig. 2, camera 210) and configured to generate an output of the encoder circuitry (Schnebly, [0023], “Each frame of the source video is encoded to include embedded sequential code values within one or more pixels by the image encoding system 212.”), the output having encoded packets that include information from the at least two video streams (Schnebly, [0023], “Each frame of the source video is encoded to include embedded sequential code values within one or more pixels by the image encoding system 212. It should be appreciated that the image encoding system 212 may be a part of the camera 210, or may be located within a computer system that is directly, or remotely, connected to the camera 210. The image encoding system 212 may include a source processor 220, memory 230, and storage 240.” The camera can capture more than one video); and
second circuitry (Schnebly, Fig. 2, image verification system 252) coupled to the memory (Schnebly, Fig. 2, memory 270), wherein the second circuitry (Schnebly, Fig. 2, image verification system 252) is configured to:
receive the output of the encoder circuitry (Schnebly, [0026], “The image verification system 252 receives the encoded video from the image encoding system 212 and utilizes the embedded codes to verify video image continuity and detect frame freeze when it occurs”);
compare data values (Schnebly, Fig. 4, [0034], “At operation 408, the extracted code from operation 404 and the code generated in operation 406 are compared.”, [0030], “The code may be a single value or a vector of values.”) representing a single image pixel at a specified location (Schnebly, [0007], “code is embedded into one or more pixels of a video frame with each subsequent frame of the video containing the next value in the code sequence. These codes can be embedded in place of the color codes for one or more pixels of each frame”, [0020], “The first pixel 110, and optionally the last pixel 120, may be used when embedding a frame freeze detection code according to the embodiments described herein”, [0031], “The code may be inserted into a single pixel, or multiple pixels of the video frame 105”, Fig. 4, step 404 “extract code value from frame”, the same code is extracted from the image which now represents that pixel) in a first frame of the frames (Schnebly, [0008], “acquiring a sequence of video frames”, [0007], “codes can be embedded in place of the color codes for one or more pixels of each frame”) to a single image pixel stored in the memory (Schnebly, Fig. 4, step 406 “generate next code value”, [0034], “The routine 400 continues from operation 404 to operation 406, where the image verification system 252 generates the next expected frame freeze code value to be compared to the frame freeze code value embedded within the received frame”, [0030], “From operation 302, the routine 300 continues to operation 304, where the image encoding system 212 generates the next frame freeze code value. The frame freeze code generator may be a simple counter, such that the code embedded into one frame 105 is simply one value greater than the code embedded into the previous frame 105”, all the frames are stored in memory therefore the codes that are generated are also stored in memory);
determine that the output of the encoder circuitry (Schnebly, Fig. 2) includes incorrect data responsive to the data values representing the single image pixel at the specified location in the first frame differing from the single image pixel stored in the memory (Schnebly, Fig.4, step 410 and 412, if the codes or data values do not match, a fault is generated, [0034], “If the extracted code does not match the expected code, then it can be concluded that there is some type of system fault”); and
determine that the output of the encoder circuitry (Schnebly, Fig. 2) includes correct data responsive to the data values representing the single image pixel at the specified location in the first frame matching the single image pixel stored in the memory (Schnebly, Fig.4, step 410 and 414, if the codes or data values do match, a fault is not generated, [0034], “If the extracted code matches the expected code, then it is reasonable to conclude that the video stream is not frozen or locked-up”).
Claim 14
Schnebly discloses the system of claim 13 (Schnebly, Fig. 2), further comprising:
first decoder circuitry (Schnebly, Fig. 2, Image verification system 252) having a first stream input configured to receive the output of the encoder circuitry (Schnebly, [0026], “The image verification system 252 receives the encoded video from the image encoding system 212 and utilizes the embedded codes to verify video image continuity and detect frame freeze when it occurs”), the first decoder circuitry (Schnebly, Fig. 2, Image verification system 252) having a first output configured to couple to a first display to display a first of the video streams ( Schnebly, Fig. 4, step 410 and 414, if the codes or data values do match, a fault is not generated and the video is displayed, [0034], “If the extracted code matches the expected code, then it is reasonable to conclude that the video stream is not frozen or locked-up”, [0035], “However, if there was no fault concluded at operation 410, then the routine 400 proceeds to operation 414, where the frame 105 is displayed on the video display 100. Optionally, the coded pixels may be removed prior to displaying the frame.”) having a second output configured to forward the output of the encoder circuitry (Schnebly, Fig.4, step 410 and 412, if the codes or data values do not match, a fault is generated, [0034], “If the extracted code does not match the expected code, then it can be concluded that there is some type of system fault”, [0028], “when the codes do not match, a fault indication may be presented to the operator using the video display 100, a lamp, LED, siren, buzzer, or other indicator of system fault”), and the first decoder circuitry (Fig. 2, Image verification system 252) and second decoder circuitry having a second stream input coupled to the second output of the first decoder circuitry (Schnebly, Fig.4, step 410 and 412, if the codes or data values do not match, a fault is generated, [0034], “If the extracted code does not match the expected code, then it can be concluded that there is some type of system fault”, [0028], “when the codes do not match, a fault indication may be presented to the operator using the video display 100, a lamp, LED, siren, buzzer, or other indicator of system fault”, the output of the first decoder system could go to the second decoder circuitry which could be another display, siren or an LED), the second decoder circuitry having a first output configured to couple to a second display to display a second of the video streams (Schnebly, Fig. 2, display 100 is has an input from the image verification system 252, [0035], “However, if there was no fault concluded at operation 410, then the routine 400 proceeds to operation 414, where the frame 105 is displayed on the video display 100. Optionally, the coded pixels may be removed prior to displaying the frame.”).
Claim 16
Schnebly discloses the system of claim 14 (Schnebly, Fig. 2), wherein responsive to determining that the output of the encoder circuitry includes incorrect data (Schnebly, Fig.4, step 410 and 412, if the codes or data values do not match, a fault is generated, [0034], “If the extracted code does not match the expected code, then it can be concluded that there is some type of system fault”), the second circuitry is further configured to generate and output an interrupt indicating that the output of the encoder circuitry includes incorrect data (Schnebly, [0028], “when the codes do not match, a fault indication may be presented to the operator using the video display 100, a lamp, LED, siren, buzzer, or other indicator of system fault”).
Claim 18
Schnebly discloses a method (Fig. 3 and Fig. 4), comprising:
receiving a video stream comprising multiple frames (Schnebly, [0008], “acquiring a sequence of video frames”);
comparing data values (Schnebly, Fig. 4, [0034], “At operation 408, the extracted code from operation 404 and the code generated in operation 406 are compared.”, [0030], “The code may be a single value or a vector of values.”) representing a single image pixel at a specified location (Schnebly, [0007], “code is embedded into one or more pixels of a video frame with each subsequent frame of the video containing the next value in the code sequence. These codes can be embedded in place of the color codes for one or more pixels of each frame”, [0020], “The first pixel 110, and optionally the last pixel 120, may be used when embedding a frame freeze detection code according to the embodiments described herein”, [0031], “The code may be inserted into a single pixel, or multiple pixels of the video frame 105”, Fig. 4, step 404 “extract code value from frame”, the same code is extracted from the image which now represents that pixel) in a first frame of the frames (Schnebly, [0008], “acquiring a sequence of video frames”, [0007], “codes can be embedded in place of the color codes for one or more pixels of each frame”) to a single image pixel stored in the memory (Schnebly, Fig. 4, step 406 “generate next code value”, [0034], “The routine 400 continues from operation 404 to operation 406, where the image verification system 252 generates the next expected frame freeze code value to be compared to the frame freeze code value embedded within the received frame”, [0030], “From operation 302, the routine 300 continues to operation 304, where the image encoding system 212 generates the next frame freeze code value. The frame freeze code generator may be a simple counter, such that the code embedded into one frame 105 is simply one value greater than the code embedded into the previous frame 105”, all the frames are stored in memory therefore the codes that are generated are also stored in memory);
determining that the video stream (Schnebly, [0008], “acquiring a sequence of video frames”) includes incorrect data responsive to the data values representing the single image pixel at the specified location in the first frame differing from the single image pixel stored in a memory (Schnebly, Fig.4, step 410 and 412, if the codes or data values do not match, a fault is generated, [0034], “If the extracted code does not match the expected code, then it can be concluded that there is some type of system fault”);
determining that the video stream (Schnebly, [0008], “acquiring a sequence of video frames”) includes correct data responsive to the data values representing the single image pixel at the specified location in the first frame matching the single image pixel stored in a memory (Schnebly, Fig.4, step 410 and 414, if the codes or data values do match, a fault is not generated, [0034], “If the extracted code matches the expected code, then it is reasonable to conclude that the video stream is not frozen or locked-up”); and
taking action responsive to determining that the video stream includes incorrect data (Schnebly, [0028], “when the codes do not match, a fault indication may be presented to the operator using the video display 100, a lamp, LED, siren, buzzer, or other indicator of system fault”).
Claim 21
Schnebly discloses an apparatus (Schnebly, Fig. 2) comprising:
a circuit (Schnebly, Fig. 2, Image Verification System 252) configured to:
compare sampled data (Schnebly, Fig. 4, [0034], “At operation 408, the extracted code from operation 404 and the code generated in operation 406 are compared.”, [0030], “The code may be a single value or a vector of values.”) representing a single image pixel (Schnebly, [0007], “code is embedded into one or more pixels of a video frame with each subsequent frame of the video containing the next value in the code sequence. These codes can be embedded in place of the color codes for one or more pixels of each frame”, [0020], “The first pixel 110, and optionally the last pixel 120, may be used when embedding a frame freeze detection code according to the embodiments described herein”, [0031], “The code may be inserted into a single pixel, or multiple pixels of the video frame 105”, Fig. 4, step 404 “extract code value from frame”, the same code is extracted from the image which now represents that pixel) in a first frame of the video streams (Schnebly, [0008], “acquiring a sequence of video frames”, [0007], “codes can be embedded in place of the color codes for one or more pixels of each frame”) to a single image pixel stored in a memory (Schnebly, Fig. 4, step 406 “generate next code value”, [0034], “The routine 400 continues from operation 404 to operation 406, where the image verification system 252 generates the next expected frame freeze code value to be compared to the frame freeze code value embedded within the received frame”, [0030], “From operation 302, the routine 300 continues to operation 304, where the image encoding system 212 generates the next frame freeze code value. The frame freeze code generator may be a simple counter, such that the code embedded into one frame 105 is simply one value greater than the code embedded into the previous frame 105”, all the frames are stored in memory therefore the codes that are generated are also stored in memory);
determine that the sampled data includes incorrect data responsive to the sampled data differing from an expected image pixel data value stored in the memory (Schnebly, Fig.4, step 410 and 414, if the codes or data values do match, a fault is not generated, [0034], “If the extracted code matches the expected code, then it is reasonable to conclude that the video stream is not frozen or locked-up”); and
determine that the sampled data includes correct data responsive to the sampled data matching the expected image pixel data value stored in the memory (Schnebly, Fig.4, step 410 and 414, if the codes or data values do match, a fault is not generated, [0034], “If the extracted code matches the expected code, then it is reasonable to conclude that the video stream is not frozen or locked-up”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Schnebly in view of Fletcher et al. (US 2017/0255504 A1), hereinafter referred to as Fletcher.
Claim 6
Schnebly discloses the circuit of claim 1 (Schnebly, [0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”), wherein the specified location is determined by the processor according to random sampling of a pixel within a programmed region.
Schnebly does not explicitly disclose wherein the specified location is determined by the processor according to random sampling of a pixel within a programmed region.
However, Fletcher teaches wherein the specified location is determined by the processor according to random sampling of a pixel within a programmed region (Fletcher, [0007], “the present invention provides fault detection in that a video processor embeds an encoded carryover pixel (COP) within the digital video stream that is sent directly to the AMLCD. Preferably, the COP data is embedded in a blanking period within the video stream in such a manner that it is not visible on the display.”, [0014], “Various methods may be used to encode the COP data into consecutive video frames in a sequential manner, such as pseudorandom binary sequence (PRBS) encoding or a similar method”).
Schnebly and Fletcher are considered to be analogous to the claimed invention because it is in the same field of video error detection. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit as taught by Schnebly to incorporate the teachings of Fletcher wherein the specified location is determined by the processor according to random sampling of a pixel within a programmed region. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to make the circuit more robust (Yammine, Section VI. A).
Claim 7
The combination of Schnebly in view of Fletcher discloses the circuit of claim 6 (Schnebly, [0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”), wherein the programmed region (Fletcher, [0007], “the present invention provides fault detection in that a video processor embeds an encoded carryover pixel (COP) within the digital video stream that is sent directly to the AMLCD. Preferably, the COP data is embedded in a blanking period within the video stream in such a manner that it is not visible on the display.”, [0014], “Various methods may be used to encode the COP data into consecutive video frames in a sequential manner, such as pseudorandom binary sequence (PRBS) encoding or a similar method”) is received by the processor as input specifying horizontal and vertical coordinates defining the region (Schnebly, [0007], “For example, the upper left-hand corner pixel and lower right-hand corner pixel may be replaced with the sequential code. Other selections of edge, or corner pixels, or even any other pixel may be used to embed the codes.”, the coordinate of upper-left hand corner is going to be 1x1). The proposed combination as well as the motivation for combining the Schnebly and Fletcher references presented in the rejection of Claim 6, apply to Claim 7 and are incorporated herein by reference. Thus, the circuit recited in Claim 7 is met by Schnebly and Fletcher.
Claims 9-10, 15, 17, 19, and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Schnebly in view of Bettagere et al. (US 2016/0117557 A1), hereinafter referred to as Bettagere.
Claim 9
Schnebly discloses the circuit of claim 1 ([0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”), wherein the processor (Fig. 2, processor 220).
Schnebly does not explicitly disclose further configured to modify the data stream to create a modified data stream comprising modified video responsive to determining that the video includes the data value of the image pixel at the specified location in the first frame that is different than the data value of the image pixel stored in the memory, and wherein the circuit further comprises: an image generator configured to generate and output the data stream; and a receiver configured to receive and decode the modified data stream to display the modified video.
However, Bettagere teaches further configured to modify the data stream to create a modified data stream comprising modified video responsive to determining that the video includes the data value of the image pixel at the specified location in the first frame that is different than the data value of the image pixel stored in the memory, and wherein the circuit (Bettagere, [0068], “In yet another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt is indicative of a data mismatch fault condition during the video sequence. In still another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt triggers at least one of adding an image overlay to Subsequent frames of the video sequence to provide notice of the data mismatch fault condition, activating an alarm to provide notice of the data mismatch fault condition, and initiating a data mismatch fault recovery operation to correct the data mismatch fault condition for the video sequence.”, adding an image overlay is analogous to modifying the image) further comprises: an image generator configured to generate and output the data stream (Bettagere, Fig. 16, video processor, 1442, display processing circuit, [0068], “In yet another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt is indicative of a data mismatch fault condition during the video sequence. In still another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt triggers at least one of adding an image overlay to Subsequent frames of the video sequence to provide notice of the data mismatch fault condition, activating an alarm to provide notice of the data mismatch fault condition, and initiating a data mismatch fault recovery operation to correct the data mismatch fault condition for the video sequence.”); and a receiver configured to receive (Bettagere, Fig. 16, video processor 1442) and decode the modified data stream to display the modified video (Bettagere, Fig. 14, video processor 1442 and display device 1438, [0068], “In yet another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt is indicative of a data mismatch fault condition during the video sequence. In still another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt triggers at least one of adding an image overlay to Subsequent frames of the video sequence to provide notice of the data mismatch fault condition, activating an alarm to provide notice of the data mismatch fault condition, and initiating a data mismatch fault recovery operation to correct the data mismatch fault condition for the video sequence.”).
Schnebly and Bettagere are considered to be analogous to the claimed invention because it is in the same field of video error detection. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit as taught by Schnebly to incorporate the teachings of Bettagere of further configured to modify the data stream to create a modified data stream comprising modified video responsive to determining that the video includes the data value of the image pixel at the specified location in the first frame that is different than the data value of the image pixel stored in the memory, and wherein the circuit further comprises: an image generator configured to generate and output the data stream; and a receiver configured to receive and decode the modified data stream to display the modified video. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to notify a possible frame freeze (Bettagere, [0026]).
Claim 10
Schnebly discloses the circuit of claim 9 ([0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”), wherein the processor (Schnebly, Fig. 2, processor 220) is further configured to generate and output an indicator responsive to determining that the video includes the data value of the image pixel at the specified location in the first frame that is different than the data value of the image pixel stored in the memory (Bettagere, [0068], “In yet another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt is indicative of a data mismatch fault condition during the video sequence. In still another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt triggers at least one of adding an image overlay to Subsequent frames of the video sequence to provide notice of the data mismatch fault condition, activating an alarm to provide notice of the data mismatch fault condition, and initiating a data mismatch fault recovery operation to correct the data mismatch fault condition for the video sequence.”, adding an image overlay is analogous to modifying the image), the indicator indicating that the video includes incorrect data (Bettagere, [0068], “the data mismatch fault interrupt triggers at least one of adding an image overlay to Subsequent frames of the video sequence to provide notice of the data mismatch fault condition, activating an alarm to provide notice of the data mismatch fault condition”), and wherein the circuit (Bettagere, Fig. 16) further comprises: an image generator configured to generate and output the data stream (Bettagere, Fig. 16, video processor, 1442, display processing circuit, [0068], “In yet another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt is indicative of a data mismatch fault condition during the video sequence. In still another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt triggers at least one of adding an image overlay to Subsequent frames of the video sequence to provide notice of the data mismatch fault condition, activating an alarm to provide notice of the data mismatch fault condition, and initiating a data mismatch fault recovery operation to correct the data mismatch fault condition for the video sequence.”); and a receiver configured to: receive and decode the data stream to display the video (Bettagere, Fig. 16, video processor 1442); receive the indicator (Bettagere, [0068], “the data mismatch fault interrupt triggers at least one of adding an image overlay to Subsequent frames of the video sequence to provide notice of the data mismatch fault condition, activating an alarm to provide notice of the data mismatch fault condition”); and modify display of the video based on the indicator (Bettagere, Fig. 14, video processor 1442 and display device 1438, [0068], “In yet another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt is indicative of a data mismatch fault condition during the video sequence. In still another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt triggers at least one of adding an image overlay to Subsequent frames of the video sequence to provide notice of the data mismatch fault condition, activating an alarm to provide notice of the data mismatch fault condition, and initiating a data mismatch fault recovery operation to correct the data mismatch fault condition for the video sequence.”, [0074], “The input parameters 1548 received by the image processing circuit 1446 may include an image overlay selection signal (see FIG. 16). The image overlay selection signal is associated with selection of an image overlay 1554 to be added to one or more Video frames of the video sequence by the image processing circuit 1446.”). The proposed combination as well as the motivation for combining the Schnebly and Bettagere references presented in the rejection of Claim 9, apply to Claim 10 and are incorporated herein by reference. Thus, the circuit recited in Claim 10 is met by Schnebly and Bettagere.
Claim 15
Schnebly discloses the system of claim 14 (Fig. 2), wherein responsive to determining that the output of the encoder circuitry includes incorrect data (Fig.4, step 410 and 412, if the codes or data values do not match, a fault is generated, [0034], “If the extracted code does not match the expected code, then it can be concluded that there is some type of system fault”.
Schnebly does not explicitly disclose the second circuitry is further configured to modify the output of the encoder circuitry prior to receipt of the output of the encoder circuitry by the first decoder circuitry.
However, Bettagere teaches the second circuitry is further configured to modify the output of the encoder circuitry prior to receipt of the output of the encoder circuitry by the first decoder circuitry (Bettagere, Fig. 14, [0068], “In yet another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt is indicative of a data mismatch fault condition during the video sequence. In still another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt triggers at least one of adding an image overlay to Subsequent frames of the video sequence to provide notice of the data mismatch fault condition, activating an alarm to provide notice of the data mismatch fault condition, and initiating a data mismatch fault recovery operation to correct the data mismatch fault condition for the video sequence.”, [0074], “The input parameters 1548 received by the image processing circuit 1446 may include an image overlay selection signal (see FIG. 16). The image overlay selection signal is associated with selection of an image overlay 1554 to be added to one or more Video frames of the video sequence by the image processing circuit 1446.”).
Schnebly and Bettagere are considered to be analogous to the claimed invention because it is in the same field of video error detection. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system as taught by Schnebly to incorporate the teachings of Bettagere wherein the second circuitry is further configured to modify the output of the encoder circuitry prior to receipt of the output of the encoder circuitry by the first decoder circuitry. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to notify a possible frame freeze (Bettagere, [0026]).
Claim 17
Schnebly discloses the system of claim 16 (Fig. 2).
Schnebly does not explicitly disclose wherein one of the first decoder circuitry or the second decoder circuitry is further configured to modify an output based on the interrupt.
However, Bettagere teaches wherein one of the first decoder circuitry or the second decoder circuitry is further configured to modify an output based on the interrupt (Bettagere, Fig. 13 and 14, when the data mismatch fault is activated, a data mismatch fault interrupt happens, [0042], “If the current video frame signature does not match the predetermined signature, an interrupt event is generated to indicate a data mismatch fault condition exists.”, [0068], “In yet another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt is indicative of a data mismatch fault condition during the video sequence. In still another further embodiment of the fault detection circuit 1100, the data mismatch fault interrupt triggers at least one of adding an image overlay to Subsequent frames of the video sequence to provide notice of the data mismatch fault condition, activating an alarm to provide notice of the data mismatch fault condition, and initiating a data mismatch fault recovery operation to correct the data mismatch fault condition for the video sequence.”).
Schnebly and Bettagere are considered to be analogous to the claimed invention because it is in the same field of video error detection. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system as taught by Schnebly to incorporate the teachings of Bettagere wherein one of the first decoder circuitry or the second decoder circuitry is further configured to modify an output based on the interrupt. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to notify a possible frame freeze (Bettagere, [0026]).
Claim 19
Schnebly discloses the method of claim 18 (Fig. 3 and Fig. 4).
Schnebly does not explicitly disclose wherein taking action responsive to determining that the video stream includes incorrect data comprises one of resetting the video stream, modifying the video stream, or generating an interrupt signal indicating that the video stream includes incorrect data.
However, Bettagere teaches wherein taking action responsive to determining that the video stream includes incorrect data comprises one of resetting the video stream, modifying the video stream, or generating an interrupt signal indicating that the video stream includes incorrect data (Bettagere, [0020], “FIG. 13, in combination with FIG. 11, is a block diagram of yet another exemplary embodiment of a fault detection circuit, [0064], “the reference frame signature value 1116 is a predetermined or programmable signature value 1316 associated with an image overlay (see FIG. 15) added to the video frame of the video sequence associated with the current frame signature value 1114.”, Fig. 13, the current frame signature value and predetermined signature value which is the reference frame signature value are compared, if it does not equal, the data mismatch fault intercept is activated, [0066], “The mismatch comparator 1306 is configured to activate a data mismatch fault interrupt 1333 after determining the current and predetermined or programmable frame signature values 1114, 1316 are not equal 1330.”).
Schnebly and Bettagere are considered to be analogous to the claimed invention because it is in the same field of video error detection. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method as taught by Schnebly to incorporate the teachings of Bettagere wherein taking action responsive to determining that the video stream includes incorrect data comprises one of resetting the video stream, modifying the video stream, or generating an interrupt signal indicating that the video stream includes incorrect data. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to notify a possible frame freeze (Bettagere, [0026]).
Claim 22
Schnebly discloses the circuit of claim 1 ([0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”).
Schnebly does not explicitly disclose wherein the data values representing the image pixel at the specified location are data values of the image pixel at the specified location.
However, Bettagere teaches wherein the data values representing the image pixel at the specified location are data values of the image pixel at the specified location (Bettagere, [0034], “for example, each pixel provided to the fault detection circuit may include 30 data bits, including 10 bits defining each of the R (red), G (green) and B (blue) color components for the pixel.”, [0035], “each pixel of the frame region for each video frame of a video sequence is passed to an MISR module like the exemplary embodiment shown in FIG. 7. In this embodiment, a 32-bit MISR with a 32-bit Galois linear feedback shift register (LFSR) and a tap polynomial defined by P(x)=X.sup.32+X.sup.22+X.sup.2+x+1 is used to generate a signature from a predetermined sequence of pixel data for the pixels in the frame region”, [0037], “video frame signature will be dependent on the RGB content of the pixels in the frame region and the pixel sequence. For captured content, this current video frame signature may be compared to one or more previous video frame signatures to detect freeze frame faults”)
Schnebly and Bettagere are considered to be analogous to the claimed invention because it is in the same field of video error detection. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit as taught by Schnebly to incorporate the teachings of Bettagere wherein the data values representing the image pixel at the specified location are data values of the image pixel at the specified location. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to improve fault detection technique (Bettagere, [0003]).
Claim 23
Schnebly discloses the circuit of claim 1 ([0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”).
Schnebly does not explicitly disclose wherein the data values of the image pixel at the specified location consist of red-green-blue (RGB) values of the image pixel at the specified location.
However, Bettagere teaches wherein the data values of the image pixel at the specified location consist of red-green-blue (RGB) values of the image pixel at the specified location (Bettagere, [0037], “At the end of the pixel sequence for the frame region, the 32-bit LFSR in the MISR module holds a signature for the frame region of the corresponding video frame. This current video frame signature will be dependent on the RGB content of the pixels in the frame region and the pixel sequence. For captured content, this current video frame signature may be compared to one or more previous video frame signatures to detect freeze frame fault”).
Schnebly and Bettagere are considered to be analogous to the claimed invention because it is in the same field of video error detection. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit as taught by Schnebly to incorporate the teachings of Bettagere wherein the data values of the image pixel at the specified location consist of red-green-blue (RGB) values of the image pixel at the specified location. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been to improve fault detection technique (Bettagere, [0003]).
Claims 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Schnebly in view of Seigneurbieux (US 2011/0025857 A1), hereinafter referred to as Seigneurbieux.
Claim 12
Schnebly discloses the circuit of claim 1 ([0029], “program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system”), wherein the processor (Fig. 2, processor 220).
Schnebly does not explicitly disclose further configured to determine that the data stream includes incorrect data responsive to the data values representing the image pixel at the specified location in a number of the multiple frames being different from the image pixel data values stored in the memory and the number of multiple frames exceeds a threshold number of frames.
However, Seigneurbieux teaches determine that the data stream includes incorrect data responsive to data values representing the image pixel at the specified location in a number of the multiple frames being different from the image pixel data values stored in the memory (Seigneurbieux, [0042], “In the above discussed example, the intensity and chromatic information of a single corresponding horizontal line of pixels within each image frame is analyzed. When the first two image frames are analyzed, it will be determined that the intensity and chromatic information of a horizontal line of pixels within each image frame exceeds the predetermined threshold, S. When the next three image frames that are snowy are analyzed, it will be determined that the intensity and chromatic information of a horizontal line of pixels within each image frame is below the predetermined thresh old, S. Therefore, each of these next three image frames will be determined to be snowy. However, at this point, the three consecutive frames that are determined to be snowy do not exceed the required three consecutive image frames as set by the threshold integer P. Yet when the next image frame that is snowy is analyzed, it will be determined that the intensity and chromatic information of a horizontal line of pixels within that image frame is additionally below the predetermined threshold, S. Thus, this next image frame will additionally be determined to be snow. At this point, the four consecutive frames that are determined to be Snowy are more than the required three consecutive image frames as set by the threshold integer P. Accordingly, in this case, the portion of the video stream will be determined to be either interrupted or too replete with interference to process the data., when it exceeds the predetermined threshold value which is analogous to the image pixel data values stored in the memory it also means that pixel value is different from that threshold value) and the number of the multiple frames exceeds a threshold number of frames (Seigneurbieux, [0040], “embodiments of the present invention may establish the threshold integer P of consecutive image frames within the video stream that are determined to be problematic (in this case, Snowy) before providing an indication that a portion of the video stream is likely to be problematic.”, [0041], “suppose that the threshold integer P is set to three, such that when three consecutive image frames within the video stream are determined to be snowy an indication will be provided that a portion of the video stream is likely to be either interrupted or too replete with interference to process the data.”).
Schnebly and Seigneurbieux are both considered to be analogous to the claimed invention because they are in the same field of video error detection. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus as taught by Schnebly to incorporate the teachings of Seigneurbieux determine that the data stream includes incorrect data responsive to data values representing the image pixel at the specified location in a number of the multiple frames being different from the image pixel data values stored in the memory and the number of the multiple frames exceeds a threshold number of frames. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been for more accurate error detection.
Claim 20
Schnebly discloses the method of claim 18 (Fig. 3 and Fig. 4).
Schnebly does not explicitly disclose further comprising determining that the video stream includes incorrect data responsive to the data values representing the image pixel at the specified location in a number of the frames being different from the image pixel stored in a memory and the number of the frames exceeds a tolerance threshold.
However, Seigneurbieux teaches determining that the video stream includes incorrect data responsive to data values representing the image pixel at the specified location in a number of the frames being different from the image pixel stored in a memory (Seigneurbieux, [0042], “In the above discussed example, the intensity and chromatic information of a single corresponding horizontal line of pixels within each image frame is analyzed. When the first two image frames are analyzed, it will be determined that the intensity and chromatic information of a horizontal line of pixels within each image frame exceeds the predetermined threshold, S. When the next three image frames that are snowy are analyzed, it will be determined that the intensity and chromatic information of a horizontal line of pixels within each image frame is below the predetermined thresh old, S. Therefore, each of these next three image frames will be determined to be snowy. However, at this point, the three consecutive frames that are determined to be snowy do not exceed the required three consecutive image frames as set by the threshold integer P. Yet when the next image frame that is snowy is analyzed, it will be determined that the intensity and chromatic information of a horizontal line of pixels within that image frame is additionally below the predetermined threshold, S. Thus, this next image frame will additionally be determined to be snow. At this point, the four consecutive frames that are determined to be Snowy are more than the required three consecutive image frames as set by the threshold integer P. Accordingly, in this case, the portion of the video stream will be determined to be either interrupted or too replete with interference to process the data., when it exceeds the predetermined threshold value which is analogous to the image pixel data values stored in the memory it also means that pixel value is different from that threshold value) and the number of the frames exceeds a tolerance threshold (Seigneurbieux, [0040], “embodiments of the present invention may establish the threshold integer P of consecutive image frames within the video stream that are determined to be problematic (in this case, Snowy) before providing an indication that a portion of the video stream is likely to be problematic.”, [0041], “suppose that the threshold integer P is set to three, such that when three consecutive image frames within the video stream are determined to be snowy an indication will be provided that a portion of the video stream is likely to be either interrupted or too replete with interference to process the data.”).
Schnebly and Seigneurbieux are both considered to be analogous to the claimed invention because they are in the same field of video error detection. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method as taught by Schnebly to incorporate the teachings of Seigneurbieux determine that the data stream includes incorrect data responsive to data values representing the image pixel at the specified location in a number of the multiple frames being different from the image pixel data values stored in the memory and the number of the multiple frames exceeds a threshold number of frames. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. The motivation for the proposed modification would have been for more accurate error detection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENISE G ALFONSO whose telephone number is (571)272-1360. The examiner can normally be reached Monday - Friday 7:30 - 5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amandeep Saini can be reached at (571)272-3382. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DENISE G ALFONSO/Examiner, Art Unit 2662
/AMANDEEP SAINI/Supervisory Patent Examiner, Art Unit 2662